[ /Title (CD74 HC137 , CD74 HCT13 7, CD74 HC237 , CD74 HCT23 7) /Subject (High Speed Data sheet acquired from Harris Semiconductor SCHS146F March 1998 - Revised October 2003 CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches Features Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes. A “Low” LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output Enable inputs (OE1 and OE0) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A0, A1, A2 inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other Output Enable input in its active state. In the CD74HC137 and CD74HCT137 the selected output is a “Low”; in the ’HC237 and CD74HCT237 the selected output is a “High”. • Select One of Eight Data Outputs - Active Low for CD74HC137 and CD74HCT137 - Active High for ’HC237 and CD74HCT237 • l/O Port or Memory Selector • Two Enable Inputs to Simplify Cascading • Typical Propagation Delay of 13ns at VCC = 5V, 15pF, TA = 25oC (CD74HC237) • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Ordering Information • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times TEMP. RANGE (oC) PACKAGE CD54HC237F3A -55 to 125 16 Ld CERDIP CD74HC137E -55 to 125 16 Ld PDIP CD74HC137PW -55 to 125 16 Ld TSSOP CD74HC137PWR -55 to 125 16 Ld TSSOP CD74HC137PWT -55 to 125 16 Ld TSSOP CD74HC237E -55 to 125 16 Ld PDIP CD74HC237M -55 to 125 16 Ld SOIC CD74HC237MT -55 to 125 16 Ld SOIC Description CD74HC237M96 -55 to 125 16 Ld SOIC The CD74HC137, CD74HCT137, ’HC237, and CD74HCT237 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic. CD74HC237NSR -55 to 125 16 Ld SOP CD74HC237PW -55 to 125 16 Ld TSSOP CD74HC237PWR -55 to 125 16 Ld TSSOP CD74HC237PWT -55 to 125 16 Ld TSSOP CD74HCT137E -55 to 125 16 Ld PDIP CD74HCT137MT -55 to 125 16 Ld SOIC CD74HCT137M96 -55 to 125 16 Ld SOIC CD74HCT237E -55 to 125 16 Ld PDIP PART NUMBER • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%, of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Pinout Functional Diagram CD54HC237 (CERDIP) CD74HC137 (PDIP, TSSOP) CD74HCT137 (PDIP, SOIC) CD74HC237 (PDIP, SOIC, SOP, TSSOP) CD74HCT237 (PDIP) TOP VIEW A0 A1 A2 A0 1 16 VCC A1 2 15 Y0 A3 3 14 Y1 LE 4 13 Y2 OE1 5 12 Y3 OE0 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 HC/HCT HC/HCT 237 137 15 Y0 Y0 1 2 3-BIT LATCH 3 14 1 OF 8 DECODER 13 12 4 LE 11 10 OE1 OE0 5 9 6 7 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 GND = 8 VCC = 16 ’HC137, ’HCT137 TRUTH TABLE INPUTS OUTPUTS LE OE0 OE1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X H H H H H H H H X L X X X X H H H H H H H H L H L L L L L H H H H H H H L H L L L H H L H H H H H H L H L L H L H H L H H H H H L H L L H H H H H L H H H H L H L H L L H H H H L H H H L H L H L H H H H H H L H H L H L H H L H H H H H H L H L H L H H H H H H H H H H L H H L X X X Depends upon the address previously applied while LE was at a logic low. H = High Voltage Level, L = Low Voltage Level, X = Don’t Care ’HC237, ’HCT237 TRUTH TABLE INPUTS OUTPUTS LE OE0 OE1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X L L L L L L L L X L X X X X L L L L L L L L L H L L L L H L L L L L L L L H L L L H L H L L L L L L L H L L H L L L H L L L L L L H L L H H L L L H L L L L L H L H L L L L L L H L L L L H L H L H L L L L L H L L L H L H H L L L L L L L H L L H L H H H L L L L L L L H H H L X X X Depends upon the address previously applied while LE was at a logic low. H = High Voltage Level, L = Low Voltage Level, X = Don’t Care 2 CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Functional Block Diagram A0 15 LE 1 A0 Y0 A0 p 14 n Y1 LE LE p 13 Y2 n 12 LE Y3 A1 2 A1 A1 LATCH A0 11 Y4 10 3 A2 Y5 A2 A2 LATCH A2 9 Y6 LE 7 4 LE Y7 LE 5 OE1 6 OE0 3 CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Package Thermal Impedance, θJA (see Note 1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V - 6 - - ±0.1 - ±1 - ±1 µA 4 CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS ICC VCC or GND 0 6 - - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V PARAMETER Quiescent Device Current HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS All 1.5 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Prerequisite For Switching Specifications PARAMETER HC TYPES An to LE Setup Time An to LE Hold Time 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tSU 2 50 - - 65 - 75 - ns 4.5 10 - - 13 - 15 - ns 6 9 - - 11 - 13 - ns 2 30 - - 40 - 45 - ns 4.5 6 - - 8 - 9 - ns 6 5 - - 7 - 8 - ns tH 5 CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Prerequisite For Switching Specifications PARAMETER (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tW 2 50 - - 65 - 75 - ns 4.5 10 - - 13 - 15 - ns 6 9 - - 1 - 13 - ns 4.5 10 - - 13 - 15 - ns LE Pulse Width HCT TYPES An to LE Setup Time tSU An to LE Hold Time CD74HCT137 tH 4.5 7 - - 9 - 11 - ns CD74HCT237 tH 4.5 5 - - 5 - 5 - ns tW 4.5 10 - - 13 - 15 - ns LE Pulse Width Switching Specifications Input tr, tf = 6ns PARAMETER HC TYPES Propagation Delay CD74HC137, CD74HCT137 SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF An to any Y Propagation Delay ’HC237, CD74HCT237 tPLH, tPHL CL = 50pF An to any Y -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 180 - 225 - 270 ns 4.5 - - 36 - 45 - 54 ns 6 - - 31 - 38 - 46 ns 2 - - 160 - 200 - 240 ns 4.5 - - 32 - 40 - 48 ns 6 - - 27 - 34 - 41 ns Address to Output CD74HC137 tPLH, tPHL CL = 15pF 5 5 15 - - - - - ns ’HC237 tPLH, tPHL CL = 15pF 5 - 13 - - - - - ns OE0 to any Y or Y OE1 to any Y or Y LE to any Y or Y Power Dissipation Capacitance, (Notes 3, 4) CD74HC137 ’HC237 Output Transition Time Input Capacitance tPLH, tPHL CL = 50pF tTLH, tTHL CL = 50pF tTLH, tTHL CL = 50pF 2 - - 145 - 180 - 220 ns 4.5 - - 29 - 36 - 44 ns 6 - - 25 - 31 - 38 ns 2 - - 145 - 180 - 220 ns 4.5 - - 29 - 36 - 44 ns 6 - - 25 - 31 - 38 ns 2 - - 190 - 240 - 285 ns 4.5 - - 38 - 48 - 57 ns 6 - - 32 - 41 - 48 ns - - - - - pF CPD CL = 15pF 5 - 19 CPD CL = 15pF 5 - 23 - - - - - pF tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns - - - 10 - 10 - 10 pF CI - 6 CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Switching Specifications Input tr, tf = 6ns (Continued) PARAMETER TEST CONDITIONS SYMBOL HCT TYPES Propagation Delay An to any Y or Y Address to Output -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 - - 38 - 48 - 57 ns tPLH, tPHL CL = 50pF tPLH, tPHL CL = 15pF 5 - 16 - - - - - ns OE0 to any Y (HC137) tPLH, tPHL CL = 50pF 4.5 - - 35 - 44 - 53 ns OE0 to any Y (HC237) tPLH, tPHL CL = 50pF 4.5 - - 33 - 41 - 60 ns OE1 to any Y (HC137) tTLH, tTHL CL = 50pF 4.5 - - 37 - 46 - 56 ns OE1 to any Y (HC237) tTLH, tTHL CL = 50pF 4.5 - - 35 - 44 - 53 ns LE to any Y (HC137) tTLH, tTHL CL = 50pF 4.5 - - 44 - 55 - 66 ns LE to any Y (HC237) tTLH, tTHL CL = 50pF 4.5 - - 42 - 53 - 63 ns Power Dissipation Capacitance, (Notes 3, 4) CD74HC137 ’HC237 Output Transition Time CPD CL = 15pF 5 - 19 - - - - - pF CPD CL = 15pF 5 - 23 - - - - - pF 22 ns 10 pF tTLH, tTHL CL = 50pF Input Capacitance CI 4.5 - 15 - - - 10 19 - 10 - NOTES: 3. CPD is used to determine the dynamic power consumption, per gate. 4. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tfCL trCL CLOCK tWL + tWH = 90% 10% I fCL CLOCK 50% 50% 1.3V 0.3V FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tf = 6ns tf = 6ns tr = 6ns VCC 90% 50% 10% GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL GND tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tr = 6ns 1.3V 1.3V tWL tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. tPHL 2.7V 0.3V GND tWL INPUT tfCL = 6ns I fCL 3V VCC 50% 10% tWL + tWH = trCL = 6ns tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 7 CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Test Circuits and Waveforms trCL tfCL trCL CLOCK INPUT (Continued) VCC 90% GND tH(H) GND tH(H) VCC DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.3V GND IC CL 50pF GND 90% tPLH 50% IC tSU(L) tPHL tPLH tREM VCC SET, RESET OR PRESET 1.3V 0.3V tH(L) DATA INPUT 3V 2.7V CLOCK INPUT 50% 10% tfCL CL 50pF FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 8 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-8860601EA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HC237F ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HC237F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD74HC137E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC137EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC137PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC137PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC137PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC137PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC137PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC137PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC137PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC137PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC137PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC237EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC237M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD74HC237NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC237PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT137E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT137EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT137M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT137M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT137M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT137MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT137MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT137MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT237E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT237EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing CD74HC137PWR TSSOP SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8.0 12.0 Q1 PW 16 2000 330.0 12.4 7.0 5.6 1.6 W Pin1 (mm) Quadrant CD74HC237M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC237NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HC237PWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 CD74HCT137M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC137PWR TSSOP PW 16 2000 346.0 346.0 29.0 CD74HC237M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC237NSR SO NS 16 2000 346.0 346.0 33.0 CD74HC237PWR TSSOP PW 16 2000 346.0 346.0 29.0 CD74HCT137M96 SOIC D 16 2500 333.2 345.9 28.6 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. 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