STMICROELECTRONICS M48T37Y

M48T37Y
M48T37V
5.0 or 3.3V, 256 Kbit (32 Kbit x8) TIMEKEEPER® SRAM
FEATURES SUMMARY
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INTEGRATED ULTRA-LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, AND BATTERY
FREQUENCY TEST OUTPUT FOR REAL
TIME CLOCK SOFTWARE CALIBRATION
YEAR 2000 COMPLIANT
AUTOMATIC POWER-FAIL CHIP
DESELECT and WRITE PROTECTION
WATCHDOG TIMER
WRITE PROTECT VOLTAGE
(VPFD = Power-Fail Deselect Voltage):
– M48T37Y: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V
– M48T37V: VCC = 3.0 to 3.6V
2.7V ≤ VPFD ≤ 3.0V
PACKAGING INCLUDES A 44-LEAD SOIC
AND SNAPHAT® TOP (to be ordered
separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY AND
CRYSTAL
MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
PROGRAMMABLE ALARM OUTPUT
ACTIVE IN THE BATTERY BACK-UP MODE
BATTERY LOW FLAG
RoHS COMPLIANCE
Lead-free components are compliant with the
RoHS directive.
Figure 1. Package
SNAPHAT (SH)
Battery/Crystal
44
1
SOH44 (MH)
44-pin SOIC
Rev 6.0
February 2006
1/29
M48T37Y, M48T37V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2.
Table 1.
Figure 3.
Figure 4.
Logic Diagram . . . . . . . .
Signal Names . . . . . . . .
SOIC Connections . . . . .
Block Diagram . . . . . . . .
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.....4
.....4
.....5
.....6
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Chip Enable Controlled, WRITE AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Programmable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Battery Low Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/29
M48T37Y, M48T37V
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . 21
. . . . 21
. . . . 21
. . . . 22
. . . . 23
. . . . 23
. . . . 23
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15.SOH44 – 44-lead Plastic Small Outline, 4-socket SNAPHAT, Package Outline. . . . . . . 24
Table 14. SOH44 – 44-lead Plastic Small Outline, 4-socket SNAPHAT, Package Mech. Data . . . 24
Figure 16.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 25
Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 25
Figure 17.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 26
Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 18. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
M48T37Y, M48T37V
SUMMARY DESCRIPTION
The M48T37Y/V TIMEKEEPER® RAM is a 32 Kb
x8 non-volatile static RAM and real time clock. The
monolithic chip is available in a special package
which provides a highly integrated battery backedup memory and real time clock solution.
The 44-lead, 330mil SOIC package provides sockets with gold-plated contacts at both ends for direct connection to a separate SNAPHAT housing
containing the battery and crystal. The unique design allows the SNAPHAT® battery/crystal package to be mounted on top of the SOIC package
after the completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed
to prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape &Reel
form. For the 44-lead SOIC, the battery/crystal
package (e.g., SNAPHAT) part number is “M4T28BR12SH” or “M4T32-BR12SH” (see Table
18., page 27).
Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery.
Figure 2. Logic Diagram
Table 1. Signal Names
VCC
15
8
A0-A14
W
E
DQ0-DQ7
M48T37Y
M48T37V
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
RST
Reset Output (Open Drain)
IRQ/FT
Interrupt / Frequency Test Output
(Open Drain)
WDI
Watchdog Input
E
Chip Enable
G
Output Enable
W
WRITE Enable
VCC
Supply Voltage
VSS
Ground
NC
Not connected Internally
RST
IRQ/FT
G
WDI
VSS
AI02172
4/29
A0-A14
M48T37Y, M48T37V
Figure 3. SOIC Connections
NC
RST
NC
NC
A14
A12
A7
A6
A5
A4
A3
NC
NC
WDI
A2
A1
A0
DQ0
DQ1
DQ2
NC
VSS
44
1
2
43
3
42
4
41
5
40
6
39
38
7
37
8
9
36
10
35
11 M48T37Y 34
12 M48T37V 33
13
32
14
31
15
30
16
29
17
28
27
18
26
19
20
25
24
21
23
22
VCC
NC
NC
NC
IRQ/FT
W
A13
A8
A9
A11
G
NC
NC
A10
E
NC
DQ7
DQ6
DQ5
DQ4
DQ3
NC
AI02174
5/29
M48T37Y, M48T37V
Figure 4. Block Diagram
IRQ/FT
WDI
OSCILLATOR AND
CLOCK CHAIN
16 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
POWER
A0-A14
32,752 x 8
SRAM ARRAY
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
VPFD
DQ0-DQ7
E
W
G
VCC
RST
VSS
AI03253
6/29
M48T37Y, M48T37V
OPERATION MODES
As Figure 4., page 6 shows, the static memory array and the quartz controlled clock oscillator of the
M48T37Y/V are integrated on one silicon chip.
The memory locations that provide user accessible BYTEWIDE™ clock information are in the
bytes with addresses 7FF1 and 7FF9h-7FFFh (located in Table 5., page 13). The clock locations
contain the century, year, month, date, day, hour,
minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until the year
2100), 30, and 31 day months are made automatically.
Byte 7FF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
Byte 7FF7h contains the watchdog timer setting.
The watchdog timer redirects an out-of-control microprocessor and provides a reset or interrupt to it.
Bytes 7FF2h-7FF5h are reserved for clock alarm
programming. These bytes can be used to set the
alarm. This will generate an active low signal on
the IRQ/FT pin when the alarm bytes match the
date, hours, minutes, and seconds of the clock.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ READ/WRITE memory
cells. The M48T37Y/V includes a clock control circuit which updates the clock bytes with current information once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T37Y/V also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single VCC supply for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls
below the Battery Back-up Switchover Voltage
(VSO), the control circuitry connects the battery
which maintains data and clock operation until valid power returns.
Table 2. Operating Modes
Mode
VCC
Deselect
WRITE
READ
4.5 to 5.5V
or
3.0 to 3.6V
READ
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
Deselect
VSO to VPFD (min)(1)
X
X
X
High Z
CMOS Standby
Deselect
≤ VSO(1)
X
X
X
High Z
Battery Back-up Mode
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
1. See Table 13., page 23 for details.
7/29
M48T37Y, M48T37V
READ Mode
The M48T37Y/V is in the READ Mode whenever
WRITE Enable (W) is high and Chip Enable (E) is
low. The unique address specified by the 15 Address Inputs defines which one of the 32,752 bytes
of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access
time (tAVQV) after the last address input signal is
stable, providing that the E and Output Enable (G)
access times are also satisfied. If the E and G access times are not met, valid data will be available
after the latter of the Chip Enable Access time
(tELQV) or Output Enable Access time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV.
If the Address Inputs are changed while E and G
remain active, output data will remain valid for Output Data Hold time (tAXQX) but will be indeterminate until the next Address Access.
Figure 5. READ Mode AC Waveforms
tAVAV
A0-A14
VALID
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00925
Note: WRITE Enable (W) = High.
Table 3. READ Mode AC Characteristics
Symbol
M48T37Y
M48T37V
–70
–100
Parameter(1)
Min
Max
Min
Unit
Max
tAVAV
READ Cycle Time
tAVQV
Address Valid to Output Valid
70
100
ns
tELQV
Chip Enable Low to Output Valid
70
100
ns
tGLQV
Output Enable Low to Output Valid
35
50
ns
70
100
ns
tELQX(2)
Chip Enable Low to Output Transition
5
10
ns
tGLQX(2)
Output Enable Low to Output Transition
5
5
ns
tEHQZ(2)
Chip Enable High to Output Hi-Z
25
50
ns
tGHQZ(2)
Output Enable High to Output Hi-Z
25
40
ns
tAXQX
Address Transition to Output Transition
10
10
ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF.
8/29
M48T37Y, M48T37V
WRITE Mode
er READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for
tWHDX afterward. G should be kept high during
The M48T37Y/V is in the WRITE Mode whenever
W and E are low. The start of a WRITE is referenced from the latter occurring falling edge of W or
E. A WRITE is terminated by the earlier rising
edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
a minimum of tEHAX from Chip Enable or tWHAX
from WRITE Enable prior to the initiation of anoth-
WRITE cycles to avoid bus contention; however, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs tWLQZ
after W falls.
Figure 6. WRITE Enable Controlled, WRITE AC Waveform
tAVAV
VALID
A0-A14
tAVWH
tAVEL
tWHAX
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00926
Figure 7. Chip Enable Controlled, WRITE AC Waveforms
tAVAV
VALID
A0-A14
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI00927
9/29
M48T37Y, M48T37V
Table 4. WRITE Mode AC Characteristics
Symbol
Parameter
M48T37Y
M48T37V
–70
–100
(1)
Min
Max
Min
Unit
Max
tAVAV
WRITE Cycle Time
70
100
ns
tAVWL
Address Valid to WRITE Enable Low
0
0
ns
tAVEL
Address Valid to Chip Enable Low
0
0
ns
tWLWH
WRITE Enable Pulse Width
50
80
ns
tELEH
Chip Enable Low to Chip Enable High
55
80
ns
tWHAX
WRITE Enable High to Address Transition
0
10
ns
tEHAX
Chip Enable High to Address Transition
0
10
ns
tDVWH
Input Valid to WRITE Enable High
30
50
ns
tDVEH
Input Valid to Chip Enable High
30
50
ns
tWHDX
WRITE Enable High to Input Transition
5
5
ns
tEHDX
Chip Enable High to Input Transition
5
5
ns
tWLQZ(2,3)
WRITE Enable Low to Output Hi-Z
25
50
ns
tAVWH
Address Valid to WRITE Enable High
60
80
ns
tAVEH
Address Valid to Chip Enable High
60
80
ns
WRITE Enable High to Output Transition
5
10
ns
tWHQX(2,3)
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
10/29
M48T37Y, M48T37V
Data Retention Mode
With valid VCC applied, the M48T37Y/V operates
as a conventional BYTEWIDE™ static RAM.
Should the Supply Voltage decay, the RAM will
automatically power-fail deselect, write protecting
itself when VCC falls within the VPFD (max), VPFD
(min) window. All outputs become high impedance, and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48T37Y/V may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which preserves data and powers the clock. The internal
button cell will maintain data in the M48T37Y/V for
an accumulated period of at least 7 years at room
temperature when VCC is less than VSO. As system power returns and VCC rises above VSO, the
battery is disconnected and the power supply is
switched to external VCC. Normal RAM operation
can resume tREC after VCC reaches VPFD (max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
11/29
M48T37Y, M48T37V
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER® registers should
be halted before clock data is read to prevent
reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so
updating the registers can be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register 7FF8h. As
long as a '1' remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and the time that
were current at the moment the halt command was
issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in
progress. Updating will resume within a second after the bit is reset to a '0.'
Setting the Clock
Bit D7 of the Control Register (7FF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them with the cor-
12/29
rect day, date, and time data in 24 hour BCD
format (see Table 5., page 13). Resetting the
WRITE Bit to a '0' then transfers the values of all
time registers (7FF1h, 7FF9h-7FFFh) to the actual
TIMEKEEPER counters and allows normal operation to resume. After the WRITE Bit is reset, the
next clock update will occur in approximately one
second.
Note: Upon power-up following a power failure,
both the WRITE Bit and the READ Bit will be reset
to '0.'
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. When reset to a '0,' the
M48T37Y/V oscillator starts within one second.
Note: It is not necessary to set the WRITE Bit
when setting or resetting the FREQUENCY TEST
Bit (FT) or the STOP Bit (ST).
M48T37Y, M48T37V
Table 5. Register Map
Data
Address
D7
7FFFh
D6
D5
D4
D3
D2
10 Years
D0
Year
Year
00-99
Month
Month
01-12
Date: Day of Month
Date
01-31
Day
01-7
Hours
Hours
00-23
7FFEh
0
0
7FFDh
0
0
7FFCh
0
FT
7FFBh
0
0
7FFAh
0
10 Minutes
Minutes
Min
00-59
7FF9h
ST
10 Seconds
Seconds
Sec
00-59
7FF8h
W
R
S
7FF7h
WDS
BMB4
BMB3
BMB2
BMB1
BMB0
RB1
RB0
Watchdog
7FF6h
AFE
0
ABE
0
0
0
0
0
Interrupts
7FF5h
RPT4
0
AIarm 10 Date
Alarm Date
Alarm Date
01-31
7FF4h
RPT3
0
AIarm 10 Hours
Alarm Hours
Alarm Hour
00-23
7FF3h
RPT2
Alarm 10 Minutes
Alarm Minutes
Alarm Min
00-59
7FF2h
RPT1
Alarm 10 Seconds
Alarm Seconds
Alarm Sec
00-59
100 Year
Century
00-99
7FF1h
7FF0h
0
D1
Function/Range
BCD Format
10 M
10 Date
0
0
0
10 Hours
Calibration
1000 Year
WDF
Day of Week
AF
Z
Keys: S = Sign Bit
FT = Frequency Test Bit
R = READ Bit
W = WRITE Bit
ST = Stop Bit
0 = Must be set to '0'
BL = Battery Low Flag (Read only)
BMB0-BMB4 = Watchdog Multiplier Bits
BL
Z
Z
Control
Z
Z
Flags
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT4 = Alarm Repeat Mode Bits
WDF = Watchdog Flag (Read only)
AF = Alarm Flag (Read only)
Z = '0' and are Read only
13/29
M48T37Y, M48T37V
Setting the Alarm Clock
Registers 7FF5h-7FF2h contain the alarm settings. The alarm can be configured to go off at a
predetermined time on a specific day of the month
or repeat every day, hour, minute, or second. It
can also be programmed to go off while the
M48T37Y/V is in the battery back-up mode of operation to serve as a system wake-up call.
RPT1-RPT4 put the alarm in the repeat mode of
operation. Table 6 shows the possible configurations. Codes not listed in the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.
Note: User must transition address (or toggle chip
enable) to see Flag Bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT1-RPT4, AF is set. If AFE is also set, the
alarm condition activates the IRQ/FT pin. To dis-
able alarm, write '0' to the Alarm Date registers
and RPT1-4. The alarm flag and the IRQ/FT output are cleared by a READ to the Flags Register
as shown in Figure 8. A subsequent READ of the
Flags Register is necessary to see that the value
of the Alarm Flag has been reset to '0.'
The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if an
alarm occurs and both the Alarm in Battery Backup Mode Enable (ABE) and the AFE are set. The
ABE and AFE bits are reset during power-up,
therefore an alarm generated during power-up will
only set AF. The user can read the Flag Register
at system boot-up to determine if an alarm was
generated while the M48T37Y/V was in the deselect mode during power-up. Figure 9., page 15 illustrates the back-up mode alarm timing.
Figure 8. Alarm Interrupt Reset Waveform
ADDRESS 7FF0h
A0-A14
15ns Min
ACTIVE FLAG BIT
IRQ/FT
AI01677B
Table 6. Alarm Repeat Modes
14/29
RPT4
RPT3
RPT2
RPT1
Alarm Activated
1
1
1
1
Once per Second
1
1
1
0
Once per Minute
1
1
0
0
Once per Hour
1
0
0
0
Once per Day
0
0
0
0
Once per Month
M48T37Y, M48T37V
Figure 9. Back-up Mode Alarm Waveforms
tREC
VCC
VPFD (max)
VPFD (min)
VSO
ABE, AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT
HIGH-Z
HIGH-Z
AI03254B
Calibrating the Clock
The M48T37Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not to exceed ±35 PPM
(parts per million) oscillator frequency error at
25 °C, which equates to about ±1.53 minutes per
month. With the calibration bits properly set, the
accuracy of each M48T37Y/V improves to better
than +1/–2 PPM at 25 °C.
The oscillation rate of any crystal changes with
temperature (see Figure 11., page 19). Most clock
chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. The M48T37Y/V design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Figure 12., page 19. The number of times pulses are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five-bit Calibration byte found
in the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order
bits (D4-D0) in the Control Register 7FF8h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125, 829, 120 (64 minutes x 60 seconds/
minute x 32,768 cycles/second) actual oscillator
cycles, that is +4.068 or –2.034 PPM of adjustment per calibration step in the calibration register.
Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the
Calibration Byte would represent +10.7 or –5.35
seconds per month which corresponds to a total
range of +5.5 or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T37Y/V may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known accurate reference (like WWW broadcasts). While that
may seem crude, it allows the designer to give the
end user the ability to calibrate his clock as his environment may require, even after the final product
is packaged in a non-user serviceable enclosure.
All the designer has to do is provide a simple utility
that accesses the Calibration Byte.
15/29
M48T37Y, M48T37V
The second approach is better suited to a manufacturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512 Hz when the
Stop Bit (ST, D7 of 7FF9h) is '0' the Frequency
Test Bit (FT, D6 of 7FFCh) is '1,' the Alarm Flag
Enable Bit (AFE, D7 of 7FF6h) is '0,' and the
Watchdog Steering Bit (WDS, D7 of 7FF7h) is '1'
or the Watchdog Register is reset (7FF7h=0).
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of 512.01024
Hz would indicate a +20 PPM oscillator frequency
error, requiring a –10(WR001010) to be loaded
into the Calibration Byte for correction.
Note: Setting or changing the Calibration Byte
does not affect the Frequency Test output frequency.
The IRQ/FT pin is an open drain output which requires a pull-up resistor for proper operation. A
500-10kΩ resistor is recommended in order to
control the rise time. The FT Bit is cleared on power-down.
For more information on calibration, see the Application Note AN934, “TIMEKEEPER Calibration.”
Watchdog Timer
The watchdog timer can be used to detect an outof-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the eight-bit Watchdog Register, address 7FF7h. The five bits (BMB4-BMB0) that
store a binary multiplier and the two lower order
bits (RB1-RB0) select the resolution, where
00 = 1/16 second, 01 = 1/4 second, 10 = 1 second,
and 11 = 4 seconds. The amount of time-out is
then determined to be the multiplication of the fivebit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register =
3x1, or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M48T37Y/V sets the Watchdog Flag (WDF) and generates a watchdog inter-
16/29
rupt or a microprocessor reset. WDF is reset by
reading the Flags Register (Address 7FF0h).
Note: User must transition address (or toggle chip
enable) to see Flag Bit change.
Reset will not occur unless the addresses are stable at the flag location for at least 15ns while the
device is in the READ Mode as shown in Figure
10., page 18.
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit. When set to a '0,' the
watchdog will activate the IRQ/FT pin when timedout. When WDS is set to a '1,' the watchdog will
output a negative pulse on the RST pin for a duration of tREC. The Watchdog Register, the FT Bit,
AFE Bit, and ABE Bit will reset to a '0' at the end of
a Watchdog time-out when the WDS bit is set to a
'1.'
The watchdog timer resets when the microprocessor performs a re-write of the Watchdog Register
or an edge transition (low to high / high to low) on
the WDI pin occurs. The time-out period then
starts over.
The watchdog timer is disabled by writing a value
of 00000000 to the eight bits in the Watchdog Register. Should the watchdog timer time-out, a value
of 00h needs to be written to the Watchdog Register in order to clear the IRQ/FT pin.
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied. The WDI
pin should be connected to VSS if not used.
Power-on Reset
The M48T37Y/V continuously monitors VCC.
When VCC falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for tREC after VCC passes VPFD. RST is
valid for all VCC conditions. The RST pin is an
open drain output and an appropriate resistor to
VCC should be chosen to control rise time (see
Figure 14., page 23).
M48T37Y, M48T37V
Programmable Interrupts
The M48T37Y/V provides two programmable interrupts: an alarm and a watchdog. When an interrupt condition occurs, the M48T37Y/V sets the
appropriate flag bit in the Flag Register 7FF0h.
The interrupt enable bits (AFE and ABE) in 7FF6h
and the Watchdog Steering (WDS) Bit in 7FF7h allow the interrupt to activate the IRQ/FT pin.
The Alarm flag and the IRQ/FT output are cleared
by a READ to the Flags Register. An interrupt condition reset will not occur unless the addresses are
stable at the flag location for at least 15ns while
the device is in the READ Mode as shown in Figure 8., page 14.
The IRQ/FT pin is an open drain output and requires a pull-up resistor (10kΩ recommended) to
VCC. The pin remains in the high impedance state
unless an interrupt occurs or the Frequency Test
Mode is enabled.
tery low monitoring tests during the next power-up
sequence.
If a battery low is generated during a power-up sequence, this indicates the battery voltage is below
2.5V (approximately), which may be insufficient to
maintain data integrity. Data should be considered
suspect and verified as correct. A fresh battery
should be installed. The SNAPHAT top may be replaced while VCC is applied to the device.
Note: This will cause the clock to lose time during
the interval the battery/crystal is removed.
Note: Battery monitoring is a useful technique only
when performed periodically. The M48T37Y/V
only monitors the battery when a nominal VCC is
applied to the device. Thus applications which require extensive durations in the battery back-up
mode should be powered-up periodically (at least
once every few months) in order for this technique
to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.
Battery Low Flag
The M48T37Y/V automatically performs periodic
battery voltage monitoring upon power-up. The
Battery Low Flag (BL), Bit D4 of the Flags Register
7FF0h, will be asserted high if the SNAPHAT®
battery is found to be less than approximately
2.5V. The BL Flag will remain active until completion of battery replacement and subsequent bat-
Initial Power-on Defaults
Upon application of power to the device, the following register bits are set to a '0' state: WDS;
BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; and FT
(see Table 7).
Table 7. Default Values
W
R
FT
AFE
ABE
WATCHDOG
Register(1)
Initial Power-up
(Battery Attach for SNAPHAT)(2)
0
0
0
0
0
0
Subsequent Power-up / RESET(3)
0
0
0
0
0
0
Power-down(4)
0
0
0
1
1
0
Condition
Note: 1.
2.
3.
4.
WDS, BMB0-BMB4, RBO, RB1.
State of other control bits undefined.
State of other control bits remains unchanged.
Assuming these bits set to '1' prior to power-down.
17/29
M48T37Y, M48T37V
VCC Noise And Negative Going Transients
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure
10) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values
below VSS by as much as one volt. These negative
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
18/29
Figure 10. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
M48T37Y, M48T37V
Figure 11. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
∆F = -0.038 ppm (T - T )2 ± 10%
0
F
C2
–120
T0 = 25 °C
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
Figure 12. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
19/29
M48T37Y, M48T37V
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 8. Absolute Maximum Ratings
Symbol
TA
TSTG
TSLD(1,2)
Parameter
Value
Unit
Grade 1
0 to 70
°C
Grade 6
–40 to 85
°C
SNAPHAT®
–40 to 85
°C
SOIC
–55 to 150
°C
260
°C
M48T37Y
–0.3 to 7
V
M48T37V
–0.3 to 4.6
V
M48T37Y
–0.3 to 7
V
M48T37V
–0.3 to 4.6
V
Ambient Operating Temperature
Storage Temperature (VCC Off, Oscillator
Off)
Lead Solder Temperature for 10 seconds
VIO
Input or Output Voltages
VCC
Supply Voltage
IO
Output Current
10
mA
PD
Power Dissipation
1
W
Note: 1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for
between 90 to 150 seconds).
2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
20/29
M48T37Y, M48T37V
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 9. Operating and AC Measurement Conditions
Parameter
M48T37Y
M48T37V
Unit
4.5 to 5.5
3.0 to 3.6
V
Grade 1
0 to 70
0 to 70
°C
Grade 6
–40 to 85
–40 to 85
°C
Load Capacitance (CL)
100
50
pF
Input Rise and Fall Times
≤ 10
≤ 10
ns
Input Pulse Voltages
0 to 3
0 to 3
V
1.5
1.5
V
Supply Voltage (VCC)
Ambient Operating Temperature (TA)
Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 13. AC Testing Load Circuit
645Ω
DEVICE
UNDER
TEST
(1)
CL = 100pF
CL includes JIG capacitance
1.75V
AI02325
Note: Excluding open-drain output pins
1. ; 50pF for M48T37V.
Table 10. Capacitance
Parameter(1,2)
Symbol
CIN
CIO(3)
Min
Max
Unit
Input Capacitance
10
pF
Input / Output Capacitance
10
pF
Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
21/29
M48T37Y, M48T37V
Table 11. DC Characteristics
Symbol
Parameter
M48T37Y
M48T37V
–70
–100
(1)
Test Condition
Min
ILI(2)
Input Leakage Current
ILO(3)
Output Leakage Current
Max
Min
Unit
Max
0V ≤ VIN ≤ VCC
±1
±1
µA
0V ≤ VOUT ≤ VCC
±1
±1
µA
Outputs open
50
33
mA
E = VIH
3
2
mA
E = VCC – 0.2V
3
2
mA
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
ICC2
Supply Current (Standby)
CMOS
VIL
Input Low Voltage
–0.3
0.8
–0.3
0.8
V
VIH
Input High Voltage
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VOL
VOH
Output Low Voltage
(standard)
IOL = 2.1mA
0.4
0.4
V
Output Low Voltage
(open drain)
IOL = 10mA
0.4
0.4
V
Output High Voltage
IOH = –1mA
2.4
2.4
V
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. WDI internally pulled down to VSS through a 100kΩ resistor.
3. Outputs deselected.
22/29
M48T37Y, M48T37V
Figure 14. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tRB
tDR
tREC
RST
INPUTS
VALID
OUTPUTS
VALID
VALID
DON'T CARE
HIGH-Z
VALID
AI03078
Table 12. Power Down/Up AC Characteristics
Parameter(1)
Symbol
Min
Max
Unit
tF(2)
VPFD (max) to VPFD (min) VCC Fall Time
300
µs
tFB(3)
VPFD (min) to VSS VCC Fall Time
10
µs
tR
VPFD (min) to VPFD (max) VCC Rise Time
10
µs
tRB
VSS to VPFD (min) VCC Rise Time
1
µs
VPFD (max) to RST High
40
tREC(4)
200
ms
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
4. tREC (min) = 20ms for Industrial Temperature Range - Grade 6 device.
Table 13. Power Down/Up Trip Points DC Characteristics
Parameter(1)
Symbol
VPFD
Power-fail Deselect Voltage
VSO
Battery Back-up Switchover Voltage
tDR(3)
Min
Typ
Max
Unit
M48T37Y
4.2
4.4
4.5
V
M48T37V
2.7
2.9
3.0
V
M48T37Y
VBAT
V
M48T37V
VPFD –100mV
V
7
YEARS
Grade 1
5
Grade 6
10(2)
Expected Data Retention Time
YEARS
Note: All voltages referenced to VSS.
1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - Grade 6 device).
3. At 25°C, VCC = 0V.
23/29
M48T37Y, M48T37V
PACKAGE MECHANICAL INFORMATION
Figure 15. SOH44 – 44-lead Plastic Small Outline, 4-socket SNAPHAT, Package Outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 14. SOH44 – 44-lead Plastic Small Outline, 4-socket SNAPHAT, Package Mech. Data
mm
inches
Symb
Typ
Min
A
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.46
0.014
0.018
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
44
e
CP
24/29
Max
0.81
0.032
44
0.10
0.004
M48T37Y, M48T37V
Figure 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
A1
eA
A2
A3
A
B
L
eB
D
E
SHTK-A
Note: Drawing is not to scale.
Table 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
9.78
Max
0.385
A1
6.73
7.24
0.265
0.285
A2
6.48
6.99
0.255
0.275
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
14.22
14.99
0.560
0.590
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
25/29
M48T37Y, M48T37V
Figure 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A1
eA
A2
A3
A
B
L
eB
D
E
SHTK-A
Note: Drawing is not to scale.
Table 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data
mm
inches
Symb
Typ
Min
A
Typ
Min
10.54
Max
0.415
A1
8.00
8.51
0.315
.0335
A2
7.24
8.00
0.285
0.315
A3
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Max
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
.0710
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
M48T37Y, M48T37V
PART NUMBERING
Table 17. Ordering Information Scheme
Example:
M48T
37Y
–70
MH
1
E
Device Type
M48T
Supply Voltage and Write Protect Voltage
37Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
37V = VCC = 3.0 to 3.6V; VPFD = 2.7 to 3.0V
Speed
–70 = 70ns (37Y)
–10 = 100ns (37V)
Package
MH(1) = SOH44
Temperature Range
1 = 0 to 70°C
6 = –40 to 85°C
Shipping Method
blank = Tubes (Not for New Design - Use E)
E = ECOPACK Package, Tubes
F = ECOPACK Package, Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)
Note: 1. The SOIC package (SOH44) requires the SNAPHAT® battery package which is ordered separately under the part number “M4TXXBR12SH” in plastic tube or “M4TXX-BR12SHTR” in Tape & Reel form (see Table 18).
Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
Table 18. SNAPHAT Battery Table
Part Number
Description
Package
M4T28-BR12SH
Lithium Battery (48mAh) SNAPHAT
SH
M4T32-BR12SH
Lithium Battery (120mAh) SNAPHAT
SH
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M48T37Y, M48T37V
REVISION HISTORY
Table 19. Document Revision History
Date
Version
December 1999
1.0
First Issue
07-Feb-00
2.0
From Preliminary Data to Data Sheet; Battery Low Flag paragraph changed; 100ns
speed class identifier changed (Tables 3, 4)
11-Jul-00
2.1
tFB changed (Table 12); watchdog timer paragraph changed
19-Jun-01
3.0
Reformatted; added temp./voltage info. to tables (Table 10, 11, 3, 4, 12, 13)
06-Aug-01
3.1
Fix text for Setting the Alarm Clock (Figure 8)
15-Jan-02
3.2
Fix footnote numbering (Table 17)
20-May-02
3.3
Modify reflow time and temperature footnote (Table 8)
31-Mar-03
4.0
v2.2 template applied; data retention condition updated (Table 13)
01-Apr-04
5.0
Reformatted; updated with Lead-free package information (Table 8, 17)
08-Feb-06
6.0
New template; updated Lead-free text; fixed DC Characteristics (Table 8, 11, 17)
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Revision Details
M48T37Y, M48T37V
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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