M48Z512A M48Z512AY, M48Z512AV 4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM Features ■ Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited WRITE cycles ■ 10 years of data retention in the absence of power ■ Automatic power-fail chip deselect and WRITE protection ■ Two WRITE Protect voltages: (VPFD = power-fail deselect voltage) – M48Z512A: VCC = 4.75 to 5.5V, 4.5V ≤ VPFD ≤ 4.75V – M48Z512AY: VCC = 4.5 to 5.5V, 4.2V ≤ VPFD ≤ 4.5V – M48Z512AV: VCC = 3.0 to 3.6V, 2.8V ≤ VPFD ≤ 3.0V ■ Battery internally isolated until power is applied ■ Pin and function compatible with JEDEC standard 512K x 8 SRAMs ■ SOIC package provides direct connection for a SNAPHAT top which contains the battery ■ SNAPHAT housing (battery) is replaceable ■ Equivalent Surface-Mount (SMT) solution requires a 28-pin M40Z300/W and a standalone 128K x8 LPSRAM (SNAPHAT® top to be ordered separately ■ PMDIP32 is an ECOPACK package 32 1 PMDIP32 (PM) Module Description The M48Z512A/Y/V ZEROPOWER® RAM is a non-volatile, 4,194,304-bit Static RAM organized as 524,288 words by 8 bits. The devices combine an internal lithium battery, a CMOS SRAM and a control circuit in a plastic, 32-pin DIP Module. For Surface-Mount environments ST provides an equivalent SMT solution consisting of a 28-pin, 330mil SOIC NVRAM Supervisor (M40Z300/W) and a 32-pin, (Type II TSOP, 10 x 20mm) 4Mb LPSRAM. Both 5V and 3V versions are available (see Table 2 on page 7). The unique design allows the SNAPHAT® battery package to be mounted on top of the SOIC package after the completion of the surfacemount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SNAPHAT battery package is shipped separately in plastic anti-static tubes or in Tape & Reel form. The part number is “M4Z32-BR00SH1. December 2006 Rev 6 1/24 www.st.com 1 Contents M48Z512A M48Z512AY M48Z512AV Contents 1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 Data Retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/24 M48Z512A M48Z512AY M48Z512AV List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Equivalent Surface-Mount (SMT) solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 READ mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WRITE mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power Down/Up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power Down/Up trip points dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PMDIP32 – 32-pin Plastic DIP Module, package mechanical data . . . . . . . . . . . . . . . . . . 18 SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, package mechanical data . . 19 SH – 4-pin SNAPHAT housing for 48mAh battery, package mechanical data . . . . . . . . . . 20 SH - 4-pin SNAPHAT housing for 120mAh battery, package mechanical data . . . . . . . . . 21 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3/24 List of figures M48Z512A M48Z512AY M48Z512AV List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. 4/24 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Hardware hookup for equivalent Surface-Mount (SMT) solution . . . . . . . . . . . . . . . . . . . . . 7 Chip Enable or Output Enable controlled, READ mode ac waveforms . . . . . . . . . . . . . . . . 9 Address controlled, READ mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE Enable controlled, WRITE ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chip Enable controlled, WRITE ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power Down/Up mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PMDIP32 – 32-pin Plastic DIP Module, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, package outline . . . . . . . . . . 19 SH – 4-pin SNAPHAT housing for 48mAh battery, package outline. . . . . . . . . . . . . . . . . . 20 SH – 4-pin SNAPHAT housing for 120mAh battery, package outline. . . . . . . . . . . . . . . . . 21 M48Z512A M48Z512AY M48Z512AV 1 Device overview Device overview Figure 1. Logic diagram VCC 19 8 A0-A18 W E DQ0-DQ7 M48Z512A M48Z512AY M48Z512AV G VSS AI02043 Table 1. Signal names A0-A18 DQ0-DQ7 Address Inputs Data Inputs/Outputs E Chip Enable Input G Output Enable Input W WRITE Enable Input VCC Supply voltage VSS Ground 5/24 Device overview Figure 2. M48Z512A M48Z512AY M48Z512AV DIP connections A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M48Z512A 8 M48Z512AY 9 M48Z512AV 10 11 12 13 14 15 16 VCC A15 A17 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 AI02044 Figure 3. Block diagram VCC A0-A18 POWER E VOLTAGE SENSE AND SWITCHING CIRCUITRY 512K x 8 SRAM ARRAY DQ0-DQ7 E W G INTERNAL BATTERY VSS 6/24 AI02045 M48Z512A M48Z512AY M48Z512AV Figure 4. Device overview Hardware hookup for equivalent Surface-Mount (SMT) solution (2)(3) THS VOUT SNAPHAT BATTERY(4) VCC M40Z300/W 4Mb LPSRAM DQ0-DQ7 E E1CON E E2CON E3CON E4CON A0-A18 A RST B W BL VSS VSS AI03631 1. For pin connections, see individual datasheet for M48Z300/300W at www.st.com. 2. Connect THS pin to VOUT if 4.2V ≤ VPFD ≤ 4.5V (M48Z512AY) or connect THS pin to VSS if 4.5V ≤ VPFD ≤ 4.75V (M48Z512A). 3. Connect THS pin to VSS if 2.8V ≤ VPFD ≤ 3.0V (M48Z512AV). 4. SNAPHAT® top ordered separately. Table 2. Equivalent Surface-Mount (SMT) solution NVRAM LPSRAM Supervisor THS pin(1) M48Z512A 5V 4Mb LPSRAM M40Z300 VSS M48Z512AY 5V 4Mb LPSRAM M40Z300 VOUT M48Z512AV 3V 4Mb LPSRAM M40Z300W VSS 1. Connection of Threshold Select pin (Pin 13) of Supervisor (M40Z300/300W). 7/24 Operating modes 2 M48Z512A M48Z512AY M48Z512AV Operating modes The M48Z512A/Y/V also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single VCC supply for an out of tolerance condition. When VCC is out of tolerance, the circuit WRITE protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the switchover voltage (VSO), the control circuitry connects the battery which maintains data until valid power returns. The ZEROPOWER® RAM replaces industry standard SRAMs. It provides the nonvolatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. Table 3. Operating modes(1) Mode Deselect WRITE READ READ VCC E G W DQ0-DQ7 Power 4.75 to 5.5V or 4.5 to 5.5V or 3.0 to 3.6V VIH X X High Z Standby VIL X VIL DIN Active VIL VIL VIH DOUT Active VIL VIH VIH High Z Active X X X High Z CMOS standby X X X High Z Battery back-up mode Deselect VSO to VPFD Deselect ≤ (min)(2) VSO(2) 1. See Table 11 on page 17 for details. 2. X = VIH or VIL; VSO = battery back-up switchover voltage. 2.1 READ mode The M48Z512A/Y/V is in the READ mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 4,194,304 locations in the static storage array. Thus, the unique address specified by the 19 Address Inputs defines which one of the 524,288 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E (Chip Enable) and G (Output Enable) access times are also satisfied. If the E and G access times are not met, valid data will be available after the later of Chip Enable Access time (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain low, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. 8/24 M48Z512A M48Z512AY M48Z512AV Figure 5. Operating modes Chip Enable or Output Enable controlled, READ mode ac waveforms tAVAV A0-A18 VALID tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 DATA OUT AI01221 1. WRITE Enable (W) = high. Figure 6. Address controlled, READ mode ac waveforms A0-A18 tAVAV tAVQV DQ0-DQ7 tAXQX DATA VALID AI01220 1. Chip Enable (E) and Output Enable (G) = low, WRITE Enable (W) = high. 9/24 Operating modes M48Z512A M48Z512AY M48Z512AV Table 4. READ mode ac characteristics (1) Symbol Parameter M48Z512A/Y -70 Min Max M48Z512A/Y/V -85 Min Unit Max tAVAV READ Cycle Time tAVQV Address Valid to Output Valid 70 85 ns tELQV Chip Enable low to Output Valid 70 85 ns tGLQV Output Enable low to Output Valid 35 45 ns 70 85 ns tELQX(2) Chip Enable low to Output Transition 5 5 ns tGLQX(2) Output Enable low to Output Transition 5 5 ns tEHQZ(2) Chip Enable high to Output Hi-Z tGHQZ(2) Output Enable high to Output Hi-Z tAXQX Address Transition to Output Transition 5 30 35 ns 20 25 ns 5 ns 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or -40 to 85°C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). 2. CL = 5pF. 2.2 WRITE mode The M48Z512A/Y/V is in the WRITE mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. 10/24 M48Z512A M48Z512AY M48Z512AV Figure 7. Operating modes WRITE Enable controlled, WRITE ac waveforms tAVAV A0-A18 VALID tAVWH tAVEL tWHAX E tWLWH tAVWL W tWHQX tWLQZ tWHDX DATA INPUT DQ0-DQ7 tDVWH AI01222 1. Output Enable (G) = high. Figure 8. Chip Enable controlled, WRITE ac waveforms tAVAV VALID A0-A18 tAVEH tAVEL tELEH tEHAX E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI01223 1. Output Enable (G) = high. 11/24 Operating modes Table 5. Symbol M48Z512A M48Z512AY M48Z512AV WRITE mode ac characteristics Parameter (1) M48Z512A/Y –70 Min Max M48Z512A/Y/V –85 Min Unit Max tAVAV WRITE cycle time 70 85 ns tAVWL Address Valid to WRITE Enable low 0 0 ns tAVEL Address Valid to Chip Enable low 0 0 ns tWLWH WRITE Enable pulse width 55 65 ns tELEH Chip Enable low to Chip Enable high 55 75 ns tWHAX WRITE Enable high to Address Transition 5 5 ns tEHAX Chip Enable high to Address Transition 15 15 ns tDVWH Input Valid to WRITE Enable high 30 35 ns tDVEH Input Valid to Chip Enable high 30 35 ns tWHDX WRITE Enable high to Input Transition 0 0 ns tEHDX Chip Enable high to Input Transition 10 10 ns tWLQZ(2)(3) WRITE Enable low to Output Hi-Z 25 30 ns tAVWH Address Valid to WRITE Enable high 65 75 ns tAVEH Address Valid to Chip Enable high 65 75 ns WRITE Enable high to Output Transition 5 5 ns tWHQX(2)(3) 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or -40 to 85°C; VCC = 4.75 to 5.5V, 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. CL = 5pF. 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. 2.3 Data Retention mode With valid VCC applied, the M48Z512A/Y/V operates as a conventional BYTEWIDE™ static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, WRITE protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as “don't care.” If power fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time tWP, WRITE protection takes place. When VCC drops below VSO, the control circuit switches power to the internal energy source which preserves data. The internal coin cell will maintain data in the M48Z512A/Y/V after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. WRITE protection continues for tER after VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can resume. For more information on battery storage life refer to the Application Note AN1012. 12/24 M48Z512A M48Z512AY M48Z512AV 2.4 Operating modes VCC noise and negative going transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (see Figure 9) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface-mount). Figure 9. Supply voltage protection tAVAV VALID A0-A18 tAVEH tAVEL tELEH tEHAX E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI01223 13/24 Maximum rating 3 M48Z512A M48Z512AY M48Z512AV Maximum rating Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6. Absolute maximum ratings Symbol Parameter TA Ambient operating temperature TSTG Storage temperature (VCC off) TBIAS Temperature under bias TSLD(1)(2) Value Grade 1 0 to 70 Grade 6 -40 to 85 Unit °C –40 to 85 Grade 1 0 to 70 Grade 6 –40 to 70 °C °C Lead solder temperature for 10 seconds 260 °C –0.3 to 7 V M48Z512A/512AY –0.3 to 7.0 V M48Z512AV –0.3 to 4.6 V VIO Input or Output voltages VCC Supply voltage IO Output current 20 mA PD Power dissipation 1 W 1. For DIP package: soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds). No preheating above 150°C, or direct exposure to IR reflow (or IR preheat) allowed, to avoid damaging the Lithium battery. 2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30 seconds). Caution: 14/24 Negative undershoots below –0.3V are not allowed on any pin while in the battery back-up mode. Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. M48Z512A M48Z512AY M48Z512AV 4 DC and ac parameters DC and ac parameters This section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. The parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7. Operating and ac measurement conditions(1) Parameter M48Z512A/512AY Supply voltage (VCC) M48Z512AV Unit 4.75 to 5.5V or 4.5 to 5.5 3.0 to 3.6 Grade 1 0 to 70 0 to 70 Grade 6 -40 to 85 -40 to 85 Load capacitance (CL) 100 50 pF Input rise and fall times ≤5 ≤ 5 ns 0 to 3 0 to 3 V 1.5 1.5 V Ambient operating temperature (TA) V °C Input pulse voltages Input and Output timing ref. voltages 1. Output Hi-Z is defined as the point where data is no longer driven. Figure 10. AC measurement load circuit 650Ω DEVICE UNDER TEST CL = 100pF or 30 pF CL includes JIG capacitance 1.75V AI03903 1. Excluding open drain output pins; 50pF for M48Z512AV. Table 8. Capacitance Parameter(1)(2) Symbol CIN CIO(3) Min Max Unit Input capacitance 10 pF Input/Output capacitance 10 pF 1. Effective capacitance measured with power supply at 5V (M48Z512A/Y) or 3.3V (M48Z512AV); sampled only, not 100% tested. 2. Outputs deselected. 3. At 25°C. 15/24 DC and ac parameters Table 9. Sym M48Z512A M48Z512AY M48Z512AV DC characteristics Test condition(1) Parameter M48Z512A/Y –70 Min ILI(2) Input leakage current ILO(2) Output leakage current Max M48Z512AV –85 Min Unit Max 0V ≤ VIN ≤ VCC ±1 ±1 µA 0V ≤ VOUT ≤ VCC ±1 ±1 µA E = VIL outputs open 115 50 mA E = VIH 10 4 mA E ≥ VCC – 0.2V 5 3 mA 0.6 V ICC Supply current ICC1 Supply current (standby) TTL ICC2 Supply current (standby) CMOS VIL Input low voltage –0.3 0.8 VIH Input high voltage 2.2 VCC + 0.3 VOL Output low voltage IOL = 2.1mA VOH Output high voltage IOH = –1mA –0.3 2.2 VCC + 0.3 0.4 2.4 V 0.4 V 2.2 V 1. Valid for ambient operating temperature: TA = 0 to 70°C or -40 to 85°C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). 2. Outputs deselected. Figure 11. Power Down/Up mode ac waveforms tF VCC VPFD (max) VPFD (min) VSO VSS tWP tDR tR tFB INPUTS RECOGNIZED (Including E) tRB DON'T CARE tER RECOGNIZED HIGH-Z OUTPUTS VALID VALID AI02385 16/24 M48Z512A M48Z512AY M48Z512AV Table 10. DC and ac parameters Power Down/Up ac characteristics Parameter(1) Symbol Min tF(2) VPFD (max) to VPFD (min) VCC fall time tFB(3) VPFD (min) to VSS VCC fall time Max 300 M48Z512A/Y 10 M48Z512AV 150 Unit µs µs tR VPFD (min) to VPFD (max) VCC rise time 10 µs tRB VSS to VPFD (min) VCC rise time 1 µs tWPT tER M48Z512A/Y 40 150 M48Z512AV 40 250 40 120 WRITE Protect time µs E Recovery time ms 1. Valid for ambient operating temperature: TA = 0 to 70°C or -40 to 85°C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/WRITE protection not occurring until 200µs after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. Table 11. Power Down/Up trip points dc characteristics Parameter(1)(2) Symbol VPFD VSO tDR (3) Power-fail deselect voltage Min Typ Max Unit M48Z512A 4.5 4.6 4.75 V M48Z512AY 4.2 4.3 4.5 V M48Z512AV 2.8 2.9 3.0 V M48Z512A/Y 3.0 V M48Z512AV 2.5 V Battery back-up switchover voltage Expected data retention time 10 Years 1. All voltages referenced to VSS. 2. Valid for ambient operating temperature: TA = 0 to 70°C or -40 to 85°C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). 3. At 25°C; VCC = 0V. 17/24 Package mechanical information 5 M48Z512A M48Z512AY M48Z512AV Package mechanical information Figure 12. PMDIP32 – 32-pin Plastic DIP Module, package outline A A1 B S L C eA e1 e3 D N E 1 PMDIP 1. Drawing is not to scale. Table 12. PMDIP32 – 32-pin Plastic DIP Module, package mechanical data mm inches Symb Typ Min Max A 9.27 9.52 A1 0.38 B 0.43 0.59 0.017 0.023 C 0.20 0.33 0.008 0.013 D 42.42 43.18 1.670 1.700 E 18.03 18.80 0.710 0.740 e1 2.29 2.79 0.090 0.110 e3 18/24 Typ Min Max 0.365 0.375 0.015 38.10 1.50 eA 14.99 16.00 0.590 0.630 L 3.05 3.81 0.120 0.150 S 1.91 2.79 0.075 0.110 N 32 32 M48Z512A M48Z512AY M48Z512AV Package mechanical information Figure 13. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, package outline A2 A C B eB e CP D N E H A1 α L 1 SOH-A 1. Drawing is not to scale. Table 13. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, package mechanical data mm inch Symbol Typ Min A Max Typ Min 3.05 Max 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.51 0.014 0.020 C 0.15 0.30 0.006 0.012 D 17.70 18.49 0.697 0.728 E 8.23 8.89 0.324 0.350 – – – – eB 3.20 3.61 0.126 0.142 H 11.51 12.70 0.453 0.500 L 0.41 1.27 0.016 0.050 α 0° 8° 0° 8° N 28 e CP 1.27 0.050 28 0.10 0.004 19/24 Package mechanical information M48Z512A M48Z512AY M48Z512AV Figure 14. SH – 4-pin SNAPHAT housing for 48mAh battery, package outline A1 A2 A eA A3 B L eB D E SHZP-A 1. Drawing is not to scale. Table 14. SH – 4-pin SNAPHAT housing for 48mAh battery, package mechanical data mm inches Symb Typ Min A Typ Min 9.78 Max 0.385 A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 A3 20/24 Max 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 14.22 14.99 0.560 0.590 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 M48Z512A M48Z512AY M48Z512AV Package mechanical information Figure 15. SH – 4-pin SNAPHAT housing for 120mAh battery, package outline A1 A2 A eA A3 B L eB D E SHZP-A 1. Drawing is not to scale. Table 15. SH - 4-pin SNAPHAT housing for 120mAh battery, package mechanical data mm inches Symb Typ Min A Max Typ Min 10.54 Max 0.415 A1 8.00 8.51 0.315 0.335 A2 7.24 8.00 0.285 0.315 A3 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.680 0.710 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 21/24 Part numbering 6 M48Z512A M48Z512AY M48Z512AV Part numbering Table 16. Ordering information scheme Example: M48Z 512AY –70 PM 1 Device type M48Z Supply voltage and WRITE Protect voltage 512A = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 512AY = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V 512AV = VCC = 3.0 to 3.6V; VPFD = 2.8 to 3.0V Speed –70 = 70ns (for M48Z512A/Y) –85 = 85ns (for M48Z512A/Y/V) Package(1) PM = PMDIP32 Temperature range 1 = 0 to 70°C 6 = -40 to 85°C 1. The SOIC package (SOH28) requires the battery package (SNAPHAT®) which is ordered separately under the part number “M4Zxx-BR00SH” in plastic tube or “M4Zxx-BR00SHTR” in Tape & Reel form. Caution: Do not place the SNAPHAT battery package “M4Zxx-BR00SH” in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you. Table 17. SNAPHAT battery table Part number 22/24 Description Package M4Z28-BR00SH Lithium battery (48mAh) SNAPHAT SH M4Z32-BR00SH Lithium battery (120mAh) SNAPHAT SH M48Z512A M48Z512AY M48Z512AV 7 Revision history Revision history Table 18. Revision history Date Version March 2000 1.0 First issue 19-Jul-00 1.1 M48Z12AV added 15-Jan-01 1.2 Changed LPSRAM device (Table 2) 19-Dec-01 2.0 Reformatted; added temperature information (Table 4, Table 5, Table 8, Table 9, Table 10, and Table 11); remove chipset option from Ordering Information (Table 16); remove reference to “clock” 08-Feb-02 2.1 Remove 85ns speed grade (Table 4, Table 5, and Table 9) 29-May-02 2.2 Modify reflow time and temperature footnotes (Table 6) 18-Nov-02 2.3 Modified SMT text (Figure 1, Figure 4, and Table 2) 17-Sep-03 2.4 Remove references to M68xxx (obsolete) part (Figure 4 and Table 2); update disclaimer 30-Nov-04 3.0 Reformatted; remove extended temperature references (Table 16) 21-Dec-04 4.0 Update Marketing Status for qualification, correct drawing (Figure 4 and Table 16) 22-Feb-05 5.0 IR reflow, SO package updates (Table 6) 21-Dec-2006 6 Revision Details Document reformatted. ECOPACK package text added on coverpage. Note 2 concerning Leaded SOIC package removed below Table 6. Updated PMDIP32 package mechanical data in Section 5: Package mechanical information; updated TA to include Grade 1 (0 to 70°C) and Grade 6 (-40 to 85°C). 23/24 M48Z512A M48Z512AY M48Z512AV Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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