STMICROELECTRONICS M54HC160K1

M54HC160
RAD-HARD SYNCHRONOUS
PRESETTABLE 4-BIT COUNTER
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HIGH SPEED:
fMAX = 62 MHz (TYP.) at VCC = 6V
LOW POWER DISSIPATION:
ICC =4µA(MAX.) at TA=25°C
HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 160
SPACE GRADE-1: ESA SCC QUALIFIED
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
DEVICE FULLY COMPLIANT WITH
SCC-9204-062
DESCRIPTION
The M54HC160 is an high speed CMOS
SYNCHRONOUS
BCD
DECADE
PRESETTABLE COUNTER fabricated with silicon
gate C2MOS technology.
DILC-16
FPC-16
ORDER CODES
PACKAGE
FM
EM
DILC
FPC
M54HC160D
M54HC160K
M54HC160D1
M54HC160K1
The CLOCK input is active on the rising edge.
Both LOAD and CLEAR inputs are active LOW.
Presetting is synchronous on the rising edge of
the clock, the function is cleared asynchronously.
Two enable inputs (TE and PE) and CARRY
output are provided to enable easy cascading of
counters, which facilities easy implementation of
N-bit counters without using external gates.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
March 2004
1/12
M54HC160
IEC LOGIC SYMBOLS
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN N°
SYMBOL
1
CLEAR
2
CLOCK
3, 4, 5, 6
7
10
9
14, 13, 12,
11
15
8
A, B, C, D
PE
TE
LOAD
Asynchronous Master
Reset
Clock Input (LOW to
HIGH, Edge-triggered)
Data Inputs
Count Enable Input
Count Enable Carry Input
Parallel Enable Input
QA to QD
Flip Flop Outputs
16
CARRY
GND
VCC
NAME AND FUNCTION
Terminal Count Output
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
FUNCTION
CLEAR
LOAD
PE
TE
CLOCK
QA
QB
QC
QD
L
X
X
X
X
L
L
L
L
RESET TO "0"
H
L
X
X
A
B
C
D
PRESET DATA
H
H
X
L
NO CHANGE
NO COUNT
H
H
L
X
NO CHANGE
NO COUNT
H
H
H
H
COUNT UP
COUNT
H
X
X
X
NO CHANGE
NO COUNT
X : Don’t Care
A, B, C, D: Logic level of data inputs
Carry: CARRY = TE·QA·QB·QC·QD
2/12
M54HC160
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
TIMING CHART
3/12
M54HC160
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Supply Voltage
Value
Unit
-0.5 to +7
V
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
V
DC Input Diode Current
± 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 25
mA
± 50
mA
VI
DC Input Voltage
VO
DC Output Voltage
IIK
ICC or IGND DC VCC or Ground Current
PD
Power Dissipation
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
V
300
mW
-65 to +150
°C
265
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Supply Voltage
VI
Input Voltage
VO
Output Voltage
Top
Operating Temperature
Input Rise and Fall Time
tr, tf
4/12
Value
Unit
2 to 6
V
0 to VCC
V
0 to VCC
V
-55 to 125
°C
VCC = 2.0V
0 to 1000
ns
VCC = 4.5V
0 to 500
ns
VCC = 6.0V
0 to 400
ns
M54HC160
DC SPECIFICATIONS
Test Condition
Symbol
VIH
VIL
VOH
VOL
II
ICC
Parameter
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage
Current
Quiescent Supply
Current
Value
TA = 25°C
VCC
(V)
Min.
2.0
4.5
6.0
2.0
4.5
6.0
Typ.
Max.
1.5
3.15
4.2
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
1.5
3.15
4.2
0.5
1.35
1.8
Max.
1.5
3.15
4.2
0.5
1.35
1.8
V
0.5
1.35
1.8
2.0
IO=-20 µA
1.9
2.0
1.9
1.9
4.5
IO=-20 µA
4.4
4.5
4.4
4.4
Unit
V
6.0
IO=-20 µA
5.9
6.0
5.9
5.9
4.5
IO=-4.0 mA
4.18
4.31
4.13
4.10
6.0
IO=-5.2 mA
5.68
2.0
IO=20 µA
0.0
0.1
0.1
0.1
4.5
IO=20 µA
0.0
0.1
0.1
0.1
6.0
IO=20 µA
0.0
0.1
0.1
0.1
4.5
IO=4.0 mA
0.17
0.26
0.33
0.40
6.0
IO=5.2 mA
0.18
0.26
0.33
0.40
6.0
VI = VCC or GND
± 0.1
±1
±1
µA
6.0
VI = VCC or GND
4
40
80
µA
5.8
5.63
V
5.60
V
5/12
M54HC160
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
Test Condition
Symbol
Parameter
tTLH tTHL Output Transition
Time
tPLH tPHL Propagation Delay
Time
(CLOCK - Q)
tPLH tPHL Propagation Delay
Time
(CLOCK - CARRY)
tPLH tPHL Propagation Delay
Time
(TE - CARRY)
tPHL
Propagation Delay
Time
(CLEAR - Q)
tPHL
Propagation Delay
Time
(CLEAR - CARRY)
fMAX
Maximum Clock
Frequency
tW(H)
tW(L)
Minimum Pulse
Width (CLOCK)
tW(L)
Minimum Pulse
Width (CLEAR)
ts
Minimum Set-up
Time
(LOAD, PE, TE)
ts
Minimum Set-up
Time
(A, B, C, D)
th
Minimum Hold
Time
(A, B - CK)
tREM
6/12
Minimum Removal
Time
VCC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Value
TA = 25°C
Min.
6.2
31
37
Typ.
Max.
25
7
6
48
16
14
57
19
16
39
13
11
60
20
17
72
24
20
18
53
62
18
6
6
24
7
6
40
10
8
20
5
3
75
15
13
125
25
21
150
30
26
100
20
17
150
30
26
200
40
34
18
4
3
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
95
19
16
155
31
26
190
38
32
125
25
21
190
38
32
250
50
43
5
25
30
75
15
13
75
15
13
100
20
17
75
15
13
0
0
0
50
10
9
Max.
110
22
19
190
38
32
225
45
38
150
30
26
225
45
38
300
60
51
4.2
21
25
95
19
16
95
19
16
125
25
21
95
19
16
0
0
0
65
13
11
Unit
ns
ns
ns
ns
ns
ns
MHz
110
22
19
110
22
19
150
30
26
110
22
19
0
0
0
75
15
13
ns
ns
ns
ns
ns
ns
M54HC160
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
VCC
(V)
Value
TA = 25°C
Min.
Typ.
Max.
10
CIN
Input Capacitance
5.0
5
CPD
Power Dissipation
Capacitance (note
1)
5.0
50
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
10
Unit
Max.
10
pF
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (CLOCK), (COUNT MODE)
(f=1MHz; 50% duty cycle)
7/12
M54HC160
WAVEFORM 2: MINIMUM PULSE WIDTH (CLEAR), REMOVAL TIME (CLEAR to CLOCK)
(PRESET MODE) (f=1MHz; 50% duty cycle)
WAVEFORM 3: SETUP AND HOLD TIMES (CLEAR MODE) (f=1MHz; 50% duty cycle)
8/12
M54HC160
WAVEFORM 4: SETUP AND HOLD TIMES (COUNTENABLE MODE) (f=1MHz; 50% duty cycle)
WAVEFORM 5: PROPAGATION DELAY TIMES (CASCADE MODE) (f=1MHz; 50% duty cycle)
9/12
M54HC160
DILC-16 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
2.1
2.71
0.083
0.107
a1
3.00
3.70
0.118
0.146
a2
0.63
1.14
0.025
B
1.82
2.39
0.072
b
0.40
0.45
0.50
0.016
0.018
0.020
b1
0.20
0.254
0.30
0.008
0.010
0.012
D
20.06
20.32
20.58
0.790
0.800
0.810
e
7.36
7.62
7.87
0.290
0.300
0.310
e1
0.88
2.54
0.035
0.045
0.094
0.100
e2
17.65
17.78
17.90
0.695
0.700
0.705
e3
7.62
7.87
8.12
0.300
0.310
0.320
F
7.29
7.49
7.70
0.287
0.295
0.303
I
3.83
0.151
K
10.90
12.1
0.429
0.476
L
1.14
1.5
0.045
0.059
0056437F
10/12
M54HC160
FPC-16 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
6.75
6.91
7.06
0.266
0.272
0.278
B
9.76
9.94
10.14
0.384
0.392
0.399
C
1.49
1.95
0.059
D
0.102
0.127
0.152
0.004
0.005
0.006
E
8.76
8.89
9.01
0.345
0.350
0.355
F
0.077
1.27
G
0.38
H
6.0
L
18.75
M
0.33
0.050
0.43
0.48
0.015
0.017
0.019
0.237
0.38
N
22.0
0.738
0.43
0.013
0.867
0.015
4.31
0.017
0.170
G
F
D
H
9
16
A
N
L
8
1
H
E
B
M
C
0016030E
11/12
M54HC160
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
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