STMICROELECTRONICS M65KA128AL

M65KA128AL
128Mbit (4 Banks x 2M x 16)
1.8V Supply, Low Power SDRAMs
Feature summary
■
128Mbit Synchronous Dynamic RAM
– Organized as 4 Banks of 2 MWords, each
16 bits wide
■
Supply Voltage
– VDD = 1.65V to 1.95V
– VDDQ = 1.65 to 1.95V for Input/Output
■
Synchronous Burst Read and Write
– Fixed Burst lengths: 1, 2, 4, 8 words or full
Page
– Burst Types: Sequential and Interleaved.
– Maximum clock frequency: 104MHz
– CAS Latency 2, 3
■
Automatic Precharge
■
Low Power features:
– PASR (Partial Array Self Refresh),
– Automatic TCSR (Temperature
Compensated Self Refresh)
– Driver Strength (DS)
– Deep Power-Down Mode
■
Delivery form: Unsawn Wafer
■
Auto Refresh and Self Refresh
■
LVCMOS Interface Compatible with
Multiplexed Addressing
■
Operating temperature
– –25°C to +90°C
Wafer
The M65KA128AL is only available as part of a Multi-Chip Package Product.
April 2006
Rev 3
1/53
www.st.com
1
Contents
M65KA128AL
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
4
2/53
2.1
Address Inputs (A0-A11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Bank Select Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Chip Select (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5
Column Address Strobe (CAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6
Row Address Strobe (RAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.8
Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9
Clock Enable (KE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10
Lower/Upper Data Input/Output Mask (LDQM/UDQM) . . . . . . . . . . . . . . 10
2.11
VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.12
VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.13
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.14
VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2
Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4
Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5
Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7
Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1
Mode Register Set command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2
Extended Mode Register Set command . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3
Bank (Row) Activate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4
Read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
M65KA128AL
5
Contents
4.5
Write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6
Precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7
Auto Precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.8
Burst Terminate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.9
Data Mask command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.10
Clock Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.11
Power-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.12
Auto Refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.13
Self Refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14
Deep Power-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1
Mode Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2
Extended Mode Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3/53
List of tables
M65KA128AL
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
4/53
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC Characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC Characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Self Refresh Current (IDD6) Values in Normal Operating Mode . . . . . . . . . . . . . . . . . . . . . 25
Synchronous AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Asynchronous AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
M65KA128AL
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Chip Enable Signal During Read, Write and Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Read with Precharge AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Read with Auto Precharge AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Clock Suspend During Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Random Column Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Random Row Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Column Interleaved Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Burst Column Read Followed by Auto Precharge AC Waveforms . . . . . . . . . . . . . . . . . . . 35
Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Byte Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Mode Register Set AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Clock Suspend During Burst Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Random Column Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Random Row Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Column Interleaved Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Burst Column Write Followed by Auto Precharge AC Waveforms . . . . . . . . . . . . . . . . . . . 43
Precharge Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Power-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Power-Down Mode and Clock Masking AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Deep Power-Down Entry AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Deep Power-Down Exit AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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Summary description
1
M65KA128AL
Summary description
The M65KA128AL is a 128 Mbit Low Power Synchronous DRAM (SDRAM) organized as 4
Banks of 2,097,152 Words of 16 bits each.
The Low Power SDRAM achieves low power consumption and high-speed data transfer
using the pipeline architecture. It is well suited for handheld battery powered applications
like PDAs, 2.5 and 3G mobile phones and handheld computers.
The device architecture is illustrated in Figure 2: Functional Block Diagram. The device uses
Burst mode to read and write data. It is capable of one, two, four, eight-word and full page,
sequential and interleaved Burst.
To minimize current consumption during self-refresh operations, the M65KA128AL includes
three system-accessible mechanisms configured via the Extended Mode Register:
●
Automatic Temperature Compensated Self Refresh (TCSR) is used to adapts the
refresh rate according to the operating temperature.
●
Partial Array Self Refresh (PASR) performs a limited refresh of a half bank, a quarter of
bank, one bank, two banks or all banks.
●
The Deep Power-Down (DPD) mode completely halts the refresh operation and
achieves minimum current consumption by cutting off the supply voltage from the
whole memory array.
The M65KA128AL is programmable through two registers, the Mode Register and the
Extended Mode Register:
●
The Mode Register is used to select the CAS Latency, the Burst Type (sequential or
interleaved) and the Burst Length. For more details, refer to Table 4: Mode Register
Definition, and to Section 4.1: Mode Register Set command.
●
The Extended Mode Register is used to program the Low Power features (PASR and
Driver Strength) to reduce the current consumption during the Self Refresh operations.
For more details, refer to Table 5: Extended Mode Register Definition, and to
Section 4.2: Extended Mode Register Set command.
The M65KA128AL is offered in unsawn wafer.
6/53
M65KA128AL
Figure 1.
Summary description
Logic Diagram
VDD VDDQ
12
16
A0-A11
DQ0-DQ15
2
BA0-BA1
E
RAS
M65KA128AL
CAS
K
KE
W
UDQM
LDQM
VSS VSSQ
AI12138
Table 1.
Signal Names
A0-A11
Address Inputs
BA0-BA1
Bank Select Inputs
DQ0-DQ15
Data Inputs/Outputs
K
Clock Input
KE
Clock Enable Input
E
Chip Select Input
W
Write Enable Input
RAS
Row Address Strobe Input
CAS
Column Address Strobe Input
UDQM
Upper Data Input/Output Mask
LDQM
Lower Data Input/Output Mask
VDD
Supply Voltage
VDDQ
Input/Output Supply Voltage
VSS
Ground
VSSQ
Input/Output Ground
7/53
Summary description
Figure 2.
M65KA128AL
Functional Block Diagram
PASR
Extended
Mode
Register
Self Refresh
Logic & Timer
K
Internal Row
Counter
KE
DQ0
...
I/O Buffer & Logic
Column Decoders
...
LDQM
Memory
Cell
Array
Sense AMP & I/O Gate
Column
PreDecoders
2 M x 16 Bank 0
...
Column
Active
2 M x 16 Bank 1
Row Decoders
UDQM
2 M x 16 Bank 2
Row Decoders
W
Refresh
2 M x 16 Bank 3
Row Decoders
CAS
State Machine
RAS
Row
PreDecoders
Row Decoders
Row Active
E
DQ15
Column Add
Counter
Bank Select
Address
Registers
Burst Length
Address Buffers
A0-A11/BA0-BA1
Mode
Register
Burst
Counter
CAS Latency
Data Out
Control
ai08974d
8/53
M65KA128AL
2
Signal descriptions
Signal descriptions
See Figure 1: Logic Diagram, and Table 1: Signal Names, for a brief overview of the signals
connected to this device.
2.1
Address Inputs (A0-A11)
The A0-A11 Address Inputs are used to select the row or column to be made active. If a row
is selected, all A0-A11 Address Inputs are used. If a column is selected, only the nine least
significant Address Inputs, A0-A8, are used. In this latter case, A10 determines whether
Auto Precharge is used. If A10 is High (set to ‘1’) during Read or Write, the Read or Write
operation includes an Auto Precharge cycle. If A10 is Low (set to ‘0’) during Read or Write,
the Read or Write cycle does not include an Auto Precharge cycle.
2.2
Bank Select Inputs (BA0-BA1)
The BA0 and BA1 Banks Select Inputs are used to select the bank to be made active.
The device must be enabled, the Row Address Strobe, RAS, must be Low, VIL, the Column
Address Strobe, CAS, and W must be High, VIH, when selecting the addresses. The
address inputs are latched on the rising edge of the clock signal, K.
2.3
Data Inputs/Outputs (DQ0-DQ15)
The Data Inputs/Outputs output the data stored at the selected address during a Read
operation, or are used to input the data during a write operation.
2.4
Chip Select (E)
The Chip Select input E activates the memory state machine, address buffers and decoders
when driven Low, VIL. When High, VIH, the device is not selected.
2.5
Column Address Strobe (CAS)
The Column Address Strobe, CAS, is used in conjunction with Address Inputs A8-A0 and
BA1-BA0, to select the starting column location prior to a Read or Write.
2.6
Row Address Strobe (RAS)
The Row Address Strobe, RAS, is used in conjunction with Address Inputs A11-A0 and
BA1-BA0, to select the starting address location prior to a Read or Write.
2.7
Write Enable (W)
The Write Enable input, W, controls writing.
9/53
Signal descriptions
2.8
M65KA128AL
Clock Input (K)
The Clock signal, K, is used to clock the Read and Write cycles. During normal operation,
the Clock Enable pin, KE, is High, VIH. The clock signal K can be suspended to switch the
device to the Self Refresh, Power-Down or Deep Power-Down mode by driving KE Low, VIL.
2.9
Clock Enable (KE)
The Clock Enable, KE, pin is used to control the synchronizing of the signals to Clock signal
K. The signals are clocked when KE is High, VIH When KE is Low, VIL, the signals are no
longer clocked and data Read and Write cycles are extended. KE is also involved in
switching the device to the Self Refresh, Power-Down and Deep Power-Down modes.
2.10
Lower/Upper Data Input/Output Mask (LDQM/UDQM)
Lower Data Input/Output Mask and Upper Data Input/Output Mask pins are input signals
used to control the Input and Output buffers, respectively.
During Read operations, LDQM and UDQM control the Output buffer. When both LDQM and
UDQM are High, VIH, the Output buffer is disabled. When held Low, VIL, the Output buffer is
enabled. LDQM and UDQM are used to mask the data read or written from or to the
memory array. LDQM Low, VIL, gates the data from or to the Lower Byte Data I/O (DQ0 to
DQ7) while UDQM Low, gates the data from or to the Upper Byte Data I/Os (DQ8 to DQ15).
During read operations, the latency between LDQM/UDQM High or Low and data output
disabled or enabled is two clock cycles. During write operations, there is no latency between
LDQM/UDQM stable and data input valid.
2.11
VDD Supply Voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (Read and Write).
2.12
VDDQ Supply Voltage
VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered
independently of VDD. VDDQ can be tied to VDD or can use a separate supply.
It is recommended to power-up and power-down VDD and VDDQ together to avoid certain
conditions that would result in data corruption.
2.13
VSS Ground
Ground, VSS, is the reference for the core power supply. It must be connected to the system
ground.
10/53
M65KA128AL
2.14
Signal descriptions
VSSQ Ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be
connected to VSS.
Note: Each device in a system should have VDD and VDDQ decoupled with a 0.1µF ceramic
capacitor close to the pin (high frequency, inherently low inductance capacitors should be as
close as possible to the package).
11/53
Operations
3
M65KA128AL
Operations
There are 7 operating modes that control the memory. Each of these is described in this
section, see Table 2: Operating Modes, for a summary.
3.1
Power-Up
The Low Power SDRAM has to be powered up and initialized in a well determined manner:
1.
Power must be applied to VDD and VDDQ simultaneously.
2.
After applying VDD and VDDQ, a minimum pause of 200µs must be respected before
the signals can be toggled.
3.
The Precharge command must then be issued to all banks. The Clock Enable input,
KE, and UDQM/LDQM must be held High until the Precharge command is issued to
make sure that DQ0-DQ15 remain high impedance.
4.
tRP after precharging all the banks, the Mode Register and the Extended Mode
Register must be set by issuing a Mode Register Set command and an Extended Mode
Register Set command, respectively. A minimum pause of tMRD must be respected
after each register set command.
5.
After configuring the registers, 2 or more Auto Refresh cycles must be executed before
the device is ready for normal operation.
The fourth and fifth steps can be swapped.
3.2
Burst Read
The Read Command is used to switch the device to Burst Read mode (see Section 4.4:
Read command for details). In Burst Read mode the data is output in bursts synchronized
with the clock. A valid Burst Read operation is initiated by driving E and CAS Low, VIL, and
by driving W and RAS High, VIH, at the positive edge of the clock signal, K.
Burst Read can be accompanied by an Auto Precharge cycle depending on the state of the
A10 Address Input. If A10 is High (set to ‘1’) when the Burst Read command is issued, the
Burst Read operation will be followed by an Auto Precharge cycle.
During Burst Read operation, the memory reads data from the activated bank. Different
Burst Types and Lengths can be programmed using the Mode Register bits (see
Section 5.1: Mode Register description). The Burst Types available are Sequential and
Interleaved, selected using Mode Register Bit A3. Possible Burst Lengths are 1-, 2-, 4-, 8Word and Full Page, selected using Mode Register Bits A2 to A0.
12/53
M65KA128AL
3.3
Operations
Burst Write
The Write Command is used to switch the device to Burst Write mode (see Section 4.5:
Write command for details). In Burst Write mode the data is input in bursts synchronized
with the clock. A valid Burst Write is initiated by driving E, CAS and W Low, VIL, and by
driving RAS High, VIH, at the positive edge of the clock signal, K.
Burst Write can be accompanied by an Auto Precharge cycle depending on the state of the
A10 Address Input. If A10 is High (set to ‘1’) when the Write command is issued, the Write
operation will be followed by an Auto Precharge cycle.
During Burst Write operation, the memory writes data to the activated bank. As for Burst
Read, different Burst Types and Lengths can be utilized, programmed in the same fashion.
3.4
Self Refresh
In Self Refresh mode, the data contained in the Low Power SDRAM memory array is
retained and refreshed. The Low Power SDRAM refresh cycles are asynchronous.
The Self-Refresh mode is entered by driving KE Low (set to ‘0’), with E, RAS, and CAS Low,
and W High (set to ‘1’). When in this mode, the device is not clocked any more.
The Self Refresh mode is exited by driving KE from Low to High, with E High, RAS, CAS
and W Don’t Care, or with E Low and RAS, CAS and W High.
3.5
Auto Refresh
The Auto Refresh mode is used to refresh the Low Power SDRAM in normal operation
mode whenever needed.
During an auto refresh operation, KE must be kept High, VIH and the address bits are “Don’t
Care” because the specific address bits are generated by the internal refresh address
counter.
3.6
Power-Down
In Power-Down mode, the current is reduced the Standby current.
For the memory to enter the Power-Down mode, KE must be held Low (set to ‘0’), after the
Precharge Time tRP, with E High (set to ‘1’), RAS, CAS and W Don’t Care, or with E Low,
RAS, CAS and W High.
The Power-Down mode is exited by driving KE High, with E High, RAS, CAS and W Don’t
Care, or with E Low and RAS, CAS and W High.
13/53
Operations
3.7
M65KA128AL
Deep Power-Down
The purpose of this mode is to achieve maximum power reduction by cutting the power
supply to the whole memory array. Data is no longer retained when the device enters Deep
Power-Down Mode.
The Low Power SDRAM is switched to Deep Power-Down mode by applying VIL to E and W,
and VIH to RAS and CAS on the rising edge of the clock, K, and by driving KE Low, VIL. For
more information, see Figure 25: Deep Power-Down Entry AC Waveforms.
The Low Power SDRAM is released from Deep Power-Down mode by applying VIH to KE,
with all other pins Don’t Care. Then a special sequence, is required before the device can
take any new command into account:
1.
Maintain No Operation status conditions (see Table 3 for a minimum time of 200µs,
2.
Issue a Precharge command to all the banks of the device (see Section 4.6: Precharge
command for details),
3.
Issue 2 or more Auto-Refresh commands,
4.
Issue a Mode Register Set command and an Extended Mode Register Set command to
initialize the Mode Register and the Extended Mode Register, respectively.
The third and fourth steps can be swapped.
The Deep Power-Down mode exit sequence is illustrated in Figure 26: Deep Power-Down
Exit AC Waveforms.
Table 2.
Operating Modes (1)
Operating Mode
KEn-1
KEn
E
RAS
CAS
W
A10
A9, A11
A0-A7
BA0-BA1
Burst Read
VIH
X
VIL
VIH
VIL
VIH
VIL
Valid
Start
Column
Address
Bank Select
Burst Write
VIH
X
VIL
VIH
VIL
VIL
VIL
Valid
Start
Column
Address
Bank Select
Self Refresh
VIH
VIL
VIL
VIL
VIL
VIH
X
X
Auto Refresh
VIH
VIH
VIL
VIL
VIL
VIH
X
X
Power-Down
VIH
VIL
VIL
VIH
VIH
VIH
X
X
VIH
X
X
X
Deep Power-Down
VIH
VIL
VIL
VIH
VIH
VIL
X
X
Device Deselect
VIH
X
VIH
X
X
X
No Operation
VIH
X
VIL
VIH
VIH
VIH
1. X = Don’t Care VIL or VIH.
14/53
X
X
X
X
X
M65KA128AL
4
Commands
Commands
There are 16 commands that control the memory. Refer to Table 3: Commands, in
conjunction with the text descriptions below and to Table 3: Commands.
4.1
Mode Register Set command
The Mode Register Set command is issued by applying VIL to E, RAS, CAS and W and by
setting BA1 to ‘0’, and BA0 to ‘0’.
The Mode Register Set command must be executed after the Power-Up sequence prior to
issuing a Bank (Row) Active command.
The execution of a Mode Register Set command will re-program the Mode Register,
modifying its contents.
4.2
Extended Mode Register Set command
The Extended Mode Register Set command is issued by applying VIL to E, RAS, CAS and
W, and then by setting BA1 to ‘1’, and BA0 to ‘0’.
The Extended Mode Register Set command must be executed after the Power-Up
sequence prior to issuing a Bank (Row) Active command.
The execution of an Extended Mode Register Set command will re-program the Extended
Mode Register, modifying its contents.
4.3
Bank (Row) Activate command
The Bank (Row) Active command is used to activate a row in a specific bank of the device.
This command is initiated by driving E and RAS Low, VIL, and driving CAS and W High, VIH,
at the positive edge of the clock signal, K. The value on BA1 and BA0 selects the bank, and
the value on A0-A11 selects the row. The selected row remains active for column access
until a Precharge command is issued to the bank containing the row.
A minimum time of tRCD is required after issuing the Bank (Row) Active command prior to
initiating Read and Write operations from and to the activated bank.
15/53
Commands
4.4
M65KA128AL
Read command
The Read command is used to switch the Low Power SDRAM to Burst Read mode (see
Section 3.2: Burst Read).
During Burst Read operation, the memory reads data from the activated bank. Inputs BA1
and BA0 are used to select a bank, Address inputs A8-A0 are used to select a starting
column location. The value at input A10 determines whether Auto Precharge is activated. If
Auto Precharge is selected, the row being accessed will be precharged at the end of the
Burst Read operation. If Auto Precharge is not selected, the row will remain active for
subsequent accesses. Different Burst Types and Lengths can be programmed using the
Mode Register bits (see Table 4: Mode Register Definition):
4.5
●
The Burst Types available are Sequential and Interleaved selected using Mode
Register Bit MR3.
●
Possible Burst Lengths are 1-, 2-, 4-, 8-Word and Full Page, selected using Mode
Register Bits MR0 to MR2.
Write command
The Write command is used to switch the Low Power SDRAM to Burst Write mode (see
Section 3.3: Burst Write).
During Burst Write operation, the memory writes data to the activated bank. Inputs BA1 and
BA0 inputs are used to select a bank, the A8-A0 Address Inputs are used to select a starting
column location. The value at the A10 input determines whether Auto Precharge is
activated. If Auto Precharge is selected, the row being accessed will be precharged at the
end of the Write burst. If Auto Precharge is not selected, the row will remain active for
subsequent accesses.
Burst Types and Lengths apply to Burst Write operation in the same manner as they do to
Burst Read operations.
4.6
Precharge command
The Precharge command is used to close the open row in a particular bank, or the open
rows in all the banks, depending on the value on the A10 Address Input. If A10 is High, at
VIH, when the Precharge command is issued, the command will be applied to all the banks,
closing all the open rows in these banks. If A10 is Low, at VIL, when the Precharge
command is issued, the command will be applied only to the selected bank, closing the
open row of this bank.
The Precharge command can also be used to terminate a Burst. Issued during a Burst
Read or Burst Write cycle, the Precharge command will interrupt the Burst operation and
close the active bank.
The precharge command can be issued any time after tRAS min. is satisfied. Soon after the
precharge command is issued, the precharge operation performed and the synchronous
DRAM enters the idle state after tRP is satisfied. The tRP parameter is the time required to
perform the precharge. The earliest timing in a read cycle that a precharge command can
be issued without losing any data in the burst is CL-1 clock cycles before the reference clock
that indicates the last data word is valid (see Figure 5)
16/53
M65KA128AL
Commands
In order to write all data to the memory cell correctly, the asynchronous parameter tDPL must
be satisfied. The tDPL (min.) specification defines the earliest time that a precharge
command can be issued.
After the Precharge command is issued, a minimum time of tRP is required before the
bank(s) are available.
4.7
Auto Precharge command
The Auto Precharge command is used to close the open row in a specific bank after a Read
or Write cycle. Read or Write with Auto Precharge is initiated if the A10 Address Input is
High, at VIH, when a Read or Write command is issued.
4.8
Burst Terminate command
The Burst Terminate command is used to terminate a Burst operation. A Burst operation can
be interrupted by using the Precharge command (see the Section 4.6: Precharge command
for details), or by issuing the Burst Terminate command. Issuing the Burst Terminate
command during a Burst Read or Write cycle will terminate the burst while leaving the bank
open.
4.9
Data Mask command
The Data Mask command is used to mask the Read or Write data. A Data Mask command
issued during a Read cycle will disable the data outputs, switching them to the highimpedance state after a delay of two clock cycles. A Data Mask command issued during a
Write cycle will disable the data inputs with no delay.
4.10
Clock Suspend command
The Clock Suspend command is used to interrupt the internal clock of the Low Power
SDRAM. The command is controlled by the Clock Enable input, KE, which is High, VIH, in
normal access mode. The Clock Suspend command is issued by driving KE Low, VIL thus
freezing the internal clock and extending data Read and Write cycles.
4.11
Power-Down command
The Power-Down command is used to put the device in Power-Down mode where the
operating current is reduced to the Standby current.
All banks must be precharged and a minimum time of tRP must elapse before issuing the
Power-Down command.
4.12
Auto Refresh command
The Auto Refresh command is used to put the device in Auto refresh mode (see Section 3.5:
Auto Refresh).
17/53
Commands
4.13
M65KA128AL
Self Refresh command
The purpose of the Self Refresh command is used to put the device in Self Refresh mode to
retain and refresh the data contained in the Low Power SDRAM memory array. In Self
Refresh mode, the Low Power SDRAM runs Refresh cycles asynchronously.
The Self Refresh cycle is performed according to the Extended Mode Register settings:
4.14
●
EMR3 to EMR4 bits configure the Refresh rate at which the memory array is refreshed
to perform a Temperature Compensated Self Refresh.
●
EMR0 to EMR2 configure the part of the memory array being refresh (Partial Array Self
Refresh).
Deep Power-Down command
The Deep Power-Down command is used to switch the Low Power SDRAM to Deep PowerDown Mode. This mode provides maximum power reduction as it cuts the power of the
entire memory array of the device. For more information on how the command is issued and
its exit sequence, see Section 3.7: Deep Power-Down, Figure 25: Deep Power-Down Entry
AC Waveforms, and Figure 26: Deep Power-Down Exit AC Waveforms.
Table 3.
Commands(1)
Command
KEn-1 KEn
E
RAS CAS
W
UDQM
LDQM
A10
A9,
A11
A0-A7
BA0BA1
DQ0DQ7
DQ8DQ15
Mode Register
Set(2)
VIH
X
VIL
VIL
VIL
VIL
X
X
Op Code
X
X
Extended Mode
Register Set(2)
VIH
X
VIL
VIL
VIL
VIL
X
X
Op Code
X
X
Bank (Row)
Active
VIH
X
VIL
VIL
VIH
VIH
X
X
Start Row Address
X
X
Word Read/Read
with Auto
Precharge
VIH
X
VIL
VIH
VIL
VIH
VIL
VIL
Upper Byte
Read/Read with
Auto Precharge
VIH
X
VIL
VIH
VIL
VIH
VIL
VIH
Lower Byte
Read/Read with
Auto Precharge
VIH
X
VIL
VIH
VIL
VIH
VIH
VIL
VIL
VIL
VIL
VIH
VIH
VIL
Word Write/Write
with Auto
Precharge
Upper Byte
Write/Write with
Auto Precharge
VIH
X
VIL
VIH
VIL
VIL
Lower Byte
Write/Write with
Auto Precharge
Write with Auto
Precharge
18/53
VIH
X
VIL
VIH
VIL
VIL
Bank
Select
VIL/VIH
X
Start
Column
Address
Bank
Select
VIL/VIH
X
Start
Column
Address
Bank
Select
Hi-Z
Output
Valid
VIL/VIH
X
Start
Column
Address
Bank
Select
Output
Valid
Hi-Z
VIL/VIH
X
Start
Column
Address
Bank
Select
VIL/VIH
X
Start
Column
Address
Bank
Select
Hi-Z
Input
Valid
VIL/VIH
(3)
X
Start
Column
Address
Bank
Select
Input
Valid
Hi-Z
VIH
X
Start
Column
Address
Bank
Select
X
X
(3)
(3)
(3)
(3)
(3)
Output
Valid
Input
Valid
M65KA128AL
Table 3.
Commands
Commands(1) (continued)
Command
KEn-1 KEn
E
RAS CAS
W
UDQM
LDQM
A10
A9,
A11
A0-A7
BA0BA1
DQ0DQ7
DQ8DQ15
Precharge All
Banks
VIH
X
VIL
VIL
VIH
VIL
X
X
VIH
X
X
X
X
Precharge
Selected Bank
VIH
X
VIL
VIL
VIH
VIL
X
X
VIL
X
V
X
X
Burst Terminate
VIH
VIH
VIL
VIH
VIH
VIL
X
X
X
X
X
X
Auto Refresh
VIH
VIH
VIL
VIL
VIL
VIH
X
X
X
X
X
X
Self Refresh
Entry
VIH
VIL
VIL
VIL
VIL
VIH
X
X
X
X
X
X
Self Refresh
Exit(4)
X
X
X
X
X
X
VIH
VIH
X
VIL
X
X
VIL
VIH
VIH
VIH
X
X
X
X
Power-Down
Entry(5)(6)
VIH
VIL
VIL
VIH
VIH
VIH
VIH
X
X
X
Power-Down
Exit(5)(6)
VIL
VIH
VIL
VIH
VIH
VIH
VIH
X
X
X
Deep PowerDown Entry
VIH
VIL
VIL
VIH
VIH
VIL
Deep PowerDown Exit
VIL
VIH
Clock Suspend
Entry
VIH
VIL
X
X
X
Clock Suspend
Exit
VIL
VIH
X
X
Data Mask /
Output Enable
VIH
X
X
Data Mask /
Output Disable
VIH
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VIL
VIL
X
X
X
X
X
X
X
VIH
VIH
X
X
Hi-Z
Hi-Z
X
1. X = Don’t Care VIL or VIH. V = Valid.
2. BA1 and BA0 must both be driven Low, VIL, to issue the Mode Register Set command. BA1 and BA0 must be driven High,
VIH and Low, VIL, respectively, to issue the Extended Mode Register Set Command.
3. To perform Read or Write operations with Autoprecharge, A10 must be held High, VIH.
4. The Self Refresh mode is exited by asynchronously driving KE from Low to High.
5. The Power-Down mode is exited by asynchronously driving KE from Low to High.
6. Banks must be precharged before issuing a Power-Down command.
19/53
Register descriptions
M65KA128AL
5
Register descriptions
5.1
Mode Register description
The Mode Register is used to select the CAS Latency (1, 2 or 3), the Burst Type (sequential,
interleaved), and the Burst Length (1-, 2-, 4-, 8-Word width or full page).
It is loaded by issuing a Mode Register Set command that programs A0 to A11 address bits.
The values placed on the address lines are then latched into the Mode Register. BA0-BA1
must be set to ‘0’.
See Table 4: Mode Register Definition, for more details.
Table 4.
Mode Register Definition
Address
Bits
Mode
Register Bit
Register
Description
A11-A7
-
-
A6-A4
MR6-MR4
Value
Bit Description
00000
010
2 Clock Cycles
CAS Latency Bits 011
3 Clock Cycles
Other configurations reserved
A3
A2-A0
MR3
MR2-MR0
0
Sequential
1
Interleaved
000
1 Word (A3 is Don’t Care)
001
2 Words (A3 is Don’t Care)
010
4 Words (A3 is Don’t Care)
011
8 Words (A3 is Don’t Care)
111
Full Page if A3 Low
Reserved if A3 High
Burst Type
Burst Length Bit
Other configurations reserved
BA1-BA0
20/53
-
-
00
M65KA128AL
5.2
Register descriptions
Extended Mode Register description
The Extended Mode Register is used to program Low Power self-refresh operation of the
device (PASR, DS, TCSR). It is used to select the area of the memory array refreshed
during Partial Array Self Refresh operations, and the driver strength.
It is loaded by issuing a Extended Mode Register Set command that programs A0 to A11
address bits. The values placed on the address lines are then latched into the Extended
Mode Register. BA0 and BA1 must be set to ‘0’ and ‘1’ respectively.
See Table 5: Extended Mode Register Definition, for more details.
Table 5.
Extended Mode Register Definition
Register
Address
Bits
Mode
Register Bit
Description
A11-A10
-
-
00
0
Enabled
EMR9
Auto
Temperature
Compensated
Self Refresh
(ATCSR)
1
Reserved
-
00
A9
A8-A7
A6-A5
A4-A3
A2-A0
-
EMR6-EMR5
Driver Strength
Bits
EMR4-EMR3
EMR2-EMR0
Value
Bit Description
00
Full Strength
01
1/2 Strength
10
1/4 Strength
11
1/8 Strength
00
Self Refresh
Area Bits
000
All Banks
001
Two Banks (BA1=0)
010
One Banks (BA0 and BA1 =0)
Other configurations reserved
BA1-BA0
-
-
10
21/53
Maximum rating
6
M65KA128AL
Maximum rating
Stressing the device above the ratings listed in Table 6: Absolute Maximum Ratings, may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 6.
Absolute Maximum Ratings
Value
Symbol
Unit
Min
Max
TJ
Junction Temperature
–25
90
°C
TSTG
Storage Temperature
–55
125
°C
Input or Output Voltage
–0.5
2.6
V
Supply Voltage
–0.5
2.6
V
VIO
VDD, VDDQ
22/53
Parameter
IOS
Short Circuit Output Current
50
mA
PD
Power Dissipation
1
W
M65KA128AL
7
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 7: Operating and AC Measurement Conditions. Designers should check that the
operating conditions in their circuit match the measurement conditions when relying on the
quoted parameters.
Table 7.
Operating and AC Measurement Conditions
M65KA128AL
Parameter(1)(2)
Units
Supply Voltage (VDD)
Input/Output Supply Voltage (VDDQ
)(3)
Junction Temperature (TJ)
Min
Typ
Max
1.65
1.8
1.95
V
1.65
1.8
1.95
V
90
°C
–25
Load Capacitance (CL)
30
pF
Output Impedance (Z0)
50
Ω
Input Rise/Fall Time (tR, tF)
1
ns
Input High Voltage (VIH)
1.6
V
Input Low Voltage (VIL)
0.2
V
VDDQ/2
V
Input and Output Timing Ref. Voltages
Output Transition Timing Reference Voltages
0.3VDDQ
0.7VDDQ
V
1. All voltages are referenced to VSS = 0V.
2. TJ = –25 to 90°C, f = 1MHz
3. VDDQ must not exceed the level of VDD.
Figure 3.
AC Measurement I/O Waveform
I/O Timing Reference Voltage
VDDQ
VDDQ/2
0V
Output Transition Timing Reference Voltage
VDDQ
0V
0.7VDDQ
0.3VDDQ
AI08009
23/53
DC and AC parameters
Table 8.
M65KA128AL
AC Measurement Load Circuit
DEVICE
UNDER
TEST
OUT
Z0
CL
CL includes probe capacitance
AI08008c
Table 9.
Capacitance(1)(2)
M65KA128AL
Symbol
Parameter
Pin
Max
K
2.0
3.5
pF
A0-A11, BA0, BA1, KE, E,
RAS, CAS, W, UDQM,
LDQM
2.0
3.8
pF
DQ0-DQ15
6.0
7.5
pF
CI1
Input Capacitance
CI2
CIO
Unit
Min
Data I/O Capacitance
1. TJ = 25°C, f = 1MHz
2. Sampled only, not 100% tested.
Table 10.
Symbol
DC Characteristics 1
Parameter
Test Condition(1)
Unit
Min
Max
ILI
Input Leakage Current
0V≤VIN ≤1.8V
–1
1
µA
ILO(2)
Output Leakage
Current
0V≤ VOUT ≤1.8V
–1.5
1.5
µA
VIL
Input Low Voltage
VIN = 0V
–0.3(3)
0.3
V
VIH
Input High Voltage
VIN = 0V
0.8VDDQ
VDDQ +
0.3(4)
V
VOL
Output Low Voltage
IOUT = 100µA, VIN = 0V
0.2
V
VOH
Output High Voltage
IOUT = –100µA, VIN = 0V
1. TJ = –25 to 90°C.
2. Data outputs are disabled.
3. VIL may undershoot to -1.0V for less that 5ns.
4. VIH may overshoot to 2.6V for less that 5ns.
24/53
M65KA128AL
VDDQ –
0.2
V
M65KA128AL
Table 11.
DC and AC parameters
DC Characteristics 2
Symbol
IDD1(2)
Test Condition(1)
Parameter
Operating Current
IDD2P
IDD2PS
IDD2N
IDD3PS
IDD3N
IDD3NS
IDD4(2)
IDD5(3)(4)
Unit
Burst length = 1, one bank active
tRC ≥ tRC(min), IOL = 0mA
36
mA
KE ≤VIL(max), tCK = 15ns
0.6
Standby Current in Power-Down Mode KE ≤VIL(max), tCK = ∞
Input signal stable
mA
0.5
KE ≥ VIH (min), E ≥ VIH (min), tCK = 15ns
Input signals are changed once in 30ns
Standby Current in Non Power-Down
Mode
IDD2NS
IDD3P
Typ
Active Standby Current in PowerDown Mode
3
mA
KE ≥ VIH (min), tCK = ∞
Input signals are stable
1
KE ≤VIL(max), tCK = 15ns
1
mA
KE ≤VIL(max), tCK = ∞
0.8
KE ≥ VIH (min), E ≥ VIH (min), tCK = 15ns
Active Standby Current in Non Power- Input signals are changed once in 30ns
Down Mode
KE ≥ V (min), t = ∞
IH
15
mA
CK
5
Input signals are stable
Burst Mode Current, CL=2
Burst Mode Current, CL=3
Auto Refresh Current, CL=2
Auto Refresh Current, CL=3
tCK ≥ tCK (min), IOL = 0mA
All banks active
35
mA
52
mA
tRC1 ≥ tRC1(min)
65
mA
See Table 12.
µA
10
µA
KE ≤0.2V
IDD6
Self Refresh Current
IDD7
See Figure 25: Deep Power-Down Entry
Standby Current in Deep Power-down
AC Waveforms, and Figure 26: Deep
Mode
Power-Down Exit AC Waveforms.
1. TJ = –25 to 90°C.
2. IDD1 and IDD4 depend on the output loading and cycle rates. All measurements are made with the output open and on
condition that the addresses are changed only once during tCK(min.).
3. The minimum value of tRC (RAS cycle time for Refresh operation) is shown in Table 14: Asynchronous AC Characteristics.
4. IDD5 is measured on condition that the addresses are changed only once during tCK (min.).
Table 12.
Self Refresh Current (IDD6) Values in Normal Operating Mode(1)
4 Banks
2 Banks
1 Bank
Temperature
Unit
Typ.
Max.
Typ.
Max.
Typ.
Max.
TJ < 40°C
150
130
120
µA
40°C < TJ ≤70°C
200
170
150
µA
70°C ≤TJ ≤90°C
600
350
220
µA
1. VDD = 1.8V, VDDQ = 1.8V, VSS = 0V, KE ≤0.2V.
25/53
DC and AC parameters
Table 13.
M65KA128AL
Synchronous AC Characteristics
Symbol
Parameter
Test Condition
Min
Max
Unit
CAS Latency = 3
7
ns
CAS Latency = 2
9
ns
tAC
Access Time From Clock
tAS
Address Setup Time
2
ns
tAH
Address Hold Time
1
ns
CAS Latency = 3
9.6
ns
tCK
Clock Period
CAS Latency = 2
15
ns
tCS
Command Setup Time
2
ns
tCH
Command Hold Time
1
ns
tCHW
Clock High Pulse Width
3
ns
tCLW
Clock Low Pulse Width
3
ns
tCKS
Clock Enable Setup Time
2
ns
tCKSP
Clock Enable Setup Time (Power-Down Exit)
2
ns
tCKH
Clock Enable Hold Time
1
ns
tDS
Data Input Setup Time
2
ns
tDH
Data Input Hold Time
1
ns
tOH
Data Output Hold Time
3
ns
tOLZ
Clock to Data Output Low-Z
0
ns
tOHZ
Clock to Data Output High-Z
26/53
CAS Latency = 3
3
7
ns
CAS Latency = 2
3
9
ns
M65KA128AL
Table 14.
DC and AC parameters
Asynchronous AC Characteristics
M65KA128AL
Symbol
Parameter
Min
tDPL
Data Input Valid to Precharge Command
tDAL
Data Input Valid to Bank/Row Activate
Command
tDQZ
Unit(1)
Max
2
tCK
CAS Latency = 3
2CLK + 28.5
ns
CAS Latency = 2
2CLK + 30
ns
UDQM or LDQM High to Data Output Hi-Z
2
tCK
tDQM
UDQM or LDQM High to Data Input Masked
0
tCK
tMRD
Mode Register Set Cycle Time
2
tCK
tRC
RAS Cycle Time
86
ns
tRCD
Delay Time, RAS Active to CAS Active
28.5
ns
tRAS
RAS Active Time
tRP
RAS Precharge Time
57
120,000
ns
28.5
ns
2
tCK
tRRD
Delay Time, RAS Active to RAS Bank Active
tRC1
Auto Refresh Exit Time
105
ns
Self Refresh Exit Time
105
ns
tRC2
(2)
tREF
tτ
tWTL
Refresh Time
Transition Time
Delay Time, Write Command to Data Input
1
0
64
ms
30
ns
tCK
1. The unit tCK is the system Clock cycle time.
2. A new command can be issued tRC after the Self Refresh mode is exited.
27/53
DC and AC parameters
AI09959b
Chip Enable Signal During Read, Write and Precharge
Write
in Bank A
Bank/Row Activate
in Bank A
DQ0-DQ15
Low
LDQM/
UDQM
Address
A10
Hi-Z
RAa
RAa
Low
BA1
BA0
W
CAS
RAS
E
KE
K
High
T0
T1
Low
T2
T3
T4
T5
Read
from Bank A
T6
CAa
T7
QAa1
T8
QAa2
T9
QAa3
T10
QAa4
DQN
T11
T12
DAb1
T13
DAb2
T14
DAb3
T15
DAb4
T16
CAb
T17
T18
Precharge
Bank A
T19
T20
T21
Figure 4.
M65KA128AL
1. The Chip Enable signal, E, must be issued at a minimum rate with respect to the other signals.
2. Burst Length = 4 Words, Latency = 3 clock cycles.
3. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAan= Data n read from Column a in Bank A,
DAan= Data n written to Column a in Bank A.
28/53
M65KA128AL
Figure 5.
DC and AC parameters
Read with Precharge AC Waveforms
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
tCK
K
tCLW
tCHW
KE
tCH
tCKS
tCKH
E
tCS
RAS
CAS
W
BA0
BA1
A10
Address
tAS
LDQM/
UDQM
tAH
Low
tAC
DQ0-DQ15
tOHZ
Hi-Z
DQN
tRCD
DQN+1
tOLZ
DQN+2
DQN+3
tOH
tRAS
tRP
tRC
Bank/Row Activate
in Bank A
Read
from Bank A
Precharge
in Bank A
Bank/Row Activate
in Bank A
AI09934c
1. Burst Length = 4 Words, Latency = 3 clock cycles.
29/53
DC and AC parameters
Figure 6.
M65KA128AL
Read with Auto Precharge AC Waveforms
Auto Precharge
Start from Bank C
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
tCK
K
tCHW
tCLW
KE
tCH
tCKS
tCKH
E
tCS
RAS
CAS
W
BA0
BA1
A10
Address
tAS
LDQM/
UDQM
Low
DQ0-DQ15
tAH
tOH
tAC
Hi-Z
DQN
tRCD
DQN+1
DQN+2
DQN+3
tOHZ
tOLZ
tRAS, tRRD
tRC
Bank/Row Activate
in Bank C
Read with Auto Precharge
from Bank C
Bank/Row Activate
in Bank D
Bank/Row Activate
in Bank C
AI09935c
1. Burst Length = 4 Words, Latency = 3 clock cycles.
30/53
Hi-Z
Low
RAa
RAa
Bank/Row Activate
in Bank A
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
T1
T2
CAa
T4
Read
from Bank A
T3
T5
T6
QAa1
T7
T9
Clock Suspended
during 1 cycle
QAa2
T8
QAa3
T11
T12
Clock Suspended
during 2 cycles
T10
T13
T15
T16
Clock Suspended
during 3 cycles
QAa4
T14
AI09947
End of
Read
Hi-Z
T17
Figure 7.
KE
K
T0
M65KA128AL
DC and AC parameters
Clock Suspend During Burst Read AC Waveforms
1. Burst Length = 4 Words, Latency = 3 clock cycles.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAan= Data n read from Column a in Bank A.
31/53
32/53
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
T5
QAa1
T6
T7
CAb
QAa3
T8
CAc
T9
QAc2
T13
QAc1
T12
QAb2
T11
QAb1
T10
QAc3
T14
QAc4
T15
T16
Read
from Bank A
Read
from Bank A
QAa2
Read
from Bank A
QAa4
DQN
Precharge
in Bank A
T17
Bank/Row Activate
in Bank A
RAa
CAa
T4
RAa
T3
RAa
T2
RAa
Bank/Row Activate
in Bank A
Hi-Z
Low
High
T1
T18
CAa
T20
Read
from Bank A
T19
AI09955
T21
Figure 8.
KE
K
T0
DC and AC parameters
M65KA128AL
Random Column Read AC Waveforms
1. Burst Length = 4 Words, Latency = 3 clock cycles.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAmn= Data n read from Column m in Bank A.
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
T5
T6
QBa1
T7
QBa2
T8
Read
from Bank B
T9
T10
Bank/Row Activate
in Bank A
QBa3 QBa4
RAa
CBa
T4
RBa
T3
RAa
T2
RBa
Bank/Row Activate
in Bank B
Hi-Z
Low
High
T1
T12
T13
Read
from Bank A
QBa8
T14
Precharge
in Bank B
QBa5 QBa6 QBa7
CAa
T11
QAa1
T15
T17
T18
T19
CBb
T20
T21
Bank/Row Activate
in Bank B
Read
from Bank A
AI09957
QAa2 QAa3 QAa4 QAa5 QAa6 QAa7
RBb
RBb
T16
Figure 9.
KE
K
T0
M65KA128AL
DC and AC parameters
Random Row Read AC Waveforms
1. Burst Length = 8 Words, Latency = 3 clock cycles.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAmn= Data n read from row m in Bank A.
33/53
34/53
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T5
Bank/Row Activate
in Bank D
Read
from Bank A
RDa
CAa
T4
RAa
T3
RDa
T2
RAa
T1
Bank/Row Activate
in Bank A
Hi-Z
Low
High
T0
T6
QAa2
CDa
T8
T9
Read
from Bank D
Read
from Bank A
Precharge
in Bank D
Precharge
in Bank A
T20
QAb4
T19
QAb3
T18
QAb2
T17
QAb1
T16
QDc2
T15
QDc1
T14
QDb2
CAb
T13
QDb1
T12
QDa2
CDc
T11
QAa4 QDa1
CDb
T10
Read
from Bank D
QAa3
Read
from Bank D
QAa1
DQN
T7
AI09520b
T21
DC and AC parameters
M65KA128AL
Figure 10. Column Interleaved Read AC Waveforms
1. Burst Length = 4 Words, Latency = 3 clock cycles.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAmn= Data n read from Column m in Bank A.
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T5
Bank/Row Activate
in Bank D
Read
from Bank A
RDa
CAa
T4
RAa
T3
RDa
T2
RAa
T1
Bank/Row Activate
in Bank A
Hi-Z
Low
High
T0
T6
CDa
T8
Read +
Auto Precharge
from Bank D
DQN
T7
T9
T11
T12
CAb
Auto Precharge
from Bank D
Read +
Auto Precharge
from Bank A
T10
T14
RDb
RDb
T15
T16
Autoprecharge Start
from Bank A
Bank/Row Activate
in Bank D
T13
T17
CDb
T19
Read +
Auto Precharge
from Bank D
T18
T20
AI09961b
T21
M65KA128AL
DC and AC parameters
Figure 11. Burst Column Read Followed by Auto Precharge AC Waveforms
1. Burst Length = 4 Words, Latency = 3 clock cycles.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A.
35/53
36/53
1. Burst Length = 4 Words.
Hi-Z
Low
T1
T2
T3
T4
tDH
T6
Bank/Row
Activate
in Bank B
T5
Write
+ Auto
Precharge
to Bank C
tRRD
tDS
tRCD
tCH, tAH
Bank/Row Activate
in Bank C
tCS, tAS
tCKS
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T0
T10
tDAL
tRAS
T9
Write to Bank B
T8
Auto Precharge
Start from Bank C
tRC
tRCD
DQN
T7
tDPL
T13
Precharge
in Bank B
T12
Bank/Row
Activate
in Bank C
tRC
T11
tCKH
T14
tRP
T16
Bank/Row
Activate
in Bank B
T15
AI09947
T17
DC and AC parameters
M65KA128AL
Figure 12. Write AC Waveforms
Hi-Z
Hi-Z
High
T1
T2
Bank/Row Activate
Read
in Bank D
from Bank D
DQ8-DQ15
DQ0-DQ7
UDQM
LDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T0
T3
T5
Lower Byte
Read
T4
T6
T8
Upper Byte
Read
tDQZ
T7
T10
Upper Byte
Write
T9
T13
T14
Read from
Bank D
Upper Byte
Write
T12
Lower Byte
Write
T11
T15
T17
Upper Byte
Read
T16
T18
T20
Upper Byte
Read
T19
AI09963c
T21
M65KA128AL
DC and AC parameters
Figure 13. Byte Write AC Waveforms
1. Burst Length = 4 Words.
37/53
DC and AC parameters
M65KA128AL
Figure 14. Mode Register Set AC Waveforms
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
K
High
KE
tMRD, 2 Clock Cycles (min)
E
RAS
CAS
W
BA0
BA1
A10
MR
Address
Data (2)
LDQM/
UDQM
DQ0-DQ15
Hi-Z
tRP
Precharge
All Banks
Mode Register
Set
Bank/Row
Activate
Valid
1. To program the Extended Mode Register, BA0 and BA1 must be set to ‘0’ and ‘1’ respectively, and A0 to A11 to the
Extended Mode Register Data.
2. MR Data is the value to be written to the Mode Register.
38/53
AI09948
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T1
Bank/Row Activate
in Bank A
Hi-Z
Low
RAa
RAa
T0
T2
T4
T5
T6
DAa2
Clock
Suspended
during 1 cycle
Write
to Bank A
DAa1
CAa
T3
T8
T9
DAa3
Clock Suspended
during 2 cycles
T7
T10
T12
T13
DAa4
Clock Suspended
during 3 cycles
T11
T14
T15
T16
AI09950
T17
M65KA128AL
DC and AC parameters
Figure 15. Clock Suspend During Burst Write AC Waveforms
1. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, DAan= Data n Written to Column a in Bank A.
39/53
40/53
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
DDa2
T7
DDa4
DQN
T6
DDa3
T5
CDb
CDc
T9
DDb2
T8
T14
Precharge
in Bank D
T13
DDc4
T12
DDc3
T11
DDc2
T10
T15
T16
Write
to Bank D
DDa1
Write
to Bank D
DDb1
Write
to Bank D
DDc1
T17
Bank/Row Activate
in Bank D
RDd
CDa
T4
RDa
T3
RDd
T2
RDa
T1
Bank/Row Activate
in Bank D
Hi-Z
Low
High
T0
T18
CDd
Write
to Bank D
T21
AI09956b
DDd2
T20
DDd1
T19
DC and AC parameters
M65KA128AL
Figure 16. Random Column Write AC Waveforms
1. Burst Length = 4 Words.
2. RDa = Address of Row a in Bank D, CDa = Address of Column a in Bank D, DDmn= Data n written to Column m in Bank D.
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
DAa2
T5
DAa3
T6
DAa4 DAa5
T7
T8
Write
to Bank A
DAa1
T9
T10
T12
Write
to Bank D
DDa4
T14
Precharge
in Bank A
DDa3
T13
DDa1 DDa2
CDa
T11
DAa7 DAa8
Bank/Row Activate
in Bank D
DAa6
RDa
CAa
T4
RAa
T3
RDa
T2
RAa
T1
Bank/Row Activate
in Bank A
Hi-Z
Low
High
T0
T18
CAb
T20
Write
to Bank A
T21
AI09958
DAb1 DAb2
T19
DDa7 DDa8
T17
DDa6
RAb
RAb
T16
Bank/Row Activate
in Bank A
DDa5
T15
M65KA128AL
DC and AC parameters
Figure 17. Random Row Write AC Waveforms
1. Burst Length = 8 Words.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, DAmn= Data n written to row m in Bank A.
41/53
42/53
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
DAa2
Write
to Bank B
DBa2
T8
CBa
DBa1
T7
DAa4
T6
DAa3
T5
Bank/Row Activate
in Bank B
Write
to Bank A
DQN
DAa1
RBa
CAa
T4
RAa
T3
RBa
T2
RAa
T1
Bank/Row Activate
in Bank A
Hi-Z
Low
High
T0
CBb
Write
to Bank B
Write
to Bank B
DAb2
T14
Write
to Bank A
DAb1
CAb
T13
DBc2
T12
DBc1
CBc
T11
DBb2
T10
DBb1
T9
T17
DBb4
T18
Precharge
in Bank A
DBb2 DBb3
T16
Write
to Bank B
DBb1
CBd
T15
T20
Precharge
in Bank B
T19
AI09521b
T21
DC and AC parameters
M65KA128AL
Figure 18. Column Interleaved Write AC Waveforms
1. Burst Length = 4 Words.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, DAmn= Data n written to Column m in Bank A.
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T5
Bank/Row
Activate
in Bank D
Write
to Bank A
DQN
RDa
CAa
T4
RAa
T3
RDa
T2
RAa
T1
Bank/Row Activate
in Bank A
Hi-Z
Low
High
T0
T6
CDa
T8
Write +
Auto Precharge
from Bank D
T7
T9
T10
CAb
T12
T13
Write +
Auto Precharge
from Bank A
Auto Precharge Start
from Bank D
T11
T14
T16
T17
T18
CDb
T19
Bank/Row
Write +
Activate
Auto Precharge
in Bank D
from Bank D
Auto Precharge Start
from Bank A
RDb
RDb
T15
T20
AI09962b
T21
M65KA128AL
DC and AC parameters
Figure 19. Burst Column Write Followed by Auto Precharge AC Waveforms
1. Burst Length = 4 Words
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A.
43/53
44/53
DQ0-DQ15
LDWM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
DAa2
T5
T6
T8
Write Masking
T7
T9
T10
T11
tRAS
Write to Bank A
DAa1
tDPL
DAa5
Precharge in Bank A
+
Write Terminated
DAa3 DQDAa4
N
Bank/Row Activate
in Bank A
tRP
RAb
CAa
T4
RAa
T3
RAb
tRCD
T2
RAa
T1
Bank/Row Activate
in Bank A
Hi-Z
High
T0
T12
CAb
tRAS
T14
Read from
Bank A
T13
T15
QAb2
T17
T19
T21
AI09524
Bank/Row Activate
in Bank A
RAc
RAc
T20
QAb3 DQQAb4
N
T18
Precharge in Bank A
+
Read Terminated
QAb1
T16
DC and AC parameters
M65KA128AL
Figure 20. Precharge Termination
1. Burst Length = 8 Words, Latency = 3 clock cycles.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAan= Data n read from Column a in Bank A,
DAan= Data n written to Column a in Bank A.
W
CAS
RAS
E
KE
K
High
DQ0-DQ15 Hi-Z
LDQM/
UDQM
Address
A10
BA1
BA0
1
T1
T2
Precharge
All Banks
High Level nedeed
1 Clock Cycle needed
T0
T6
EMR
Data (1)
T5
T7
tMRD
T8
Mode
Extended Mode
CBR
Register Set Register Set Auto Refresh
tRP
T4
MR
Data (1)
tMRD
T3
T9
tRC1
T10
T11
T13
CBR
Auto Refresh
T12
T14
T16
T17
T18
tRC1
T19
T20
T21
AI09960b
Bank/Row Activate
2 Refresh Cycles needed
T15
M65KA128AL
DC and AC parameters
Figure 21. Power-On Sequence
1. MR Data and EMR data are the values to be written to the Mode Register and the Extended Mode Register, respectively.
45/53
46/53
DQ0-DQ15
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T1
T2
1. Burst Length = 4 Words, Latency = 3 clock cycles.
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAan= Data n read from Column a in Bank A.
T4
CAa
T6
Read
from Bank A
T5
Power-Down
Exit
tCKSP
T3
ACTIVE STANDBY
Bank/Row
Activate
in Bank A
Power-Down
Entry
Hi-Z
Low
RAa
RAa
T0
T7
T8
QAa2
T10
Start of
Clock Masking
QAa1
T9
T12
End of
Clock Masking
QAa3
T11
T14
T15
Power-Down
Entry
Precharge
in Bank A
QAa4
T13
T17
T19
tCKSP
T18
PRECHARGE STANDBY
T16
T21
AI09951
Power-Down
Exit
T20
DC and AC parameters
M65KA128AL
Figure 22. Power-Down Mode and Clock Masking AC Waveforms
Hi-Z
DQ0-DQ15
T1
Precharge
Low
High
LDQM/
UDQM
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T0
T3
Auto Refresh
tRP
T2
T4
T5
tRC1
T6
Tn
Tn+1
Tn+3
Auto Refresh
Tn+2
Tn+4
Tn+5
tRC1
Tn+6
Tm
Bank/Row Activate
Read
Tm+7
AI09952c
Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6
M65KA128AL
DC and AC parameters
Figure 23. Auto Refresh
47/53
48/53
Low
Hi-Z
LDQM/
UDQM
DQ0-DQ15
Address
A10
BA1
BA0
W
CAS
RAS
E
KE
K
T0
T2
Precharge
(optional)
T1
T4
Self Refresh
Entry
tRP
T3
Tn+1
Self Refresh
Exit
Tn
tRC2
Tn+2
Tm+1
Self Refresh
Entry
(or Bank/Row
Activate)
Next Clock
Enable
Tm
Self Refresh
Exit
tRC2
Tk+2
Bank/Row
Activate
Tk+1
Next Clock
Enable
Tk
Tk+3
AI09953b
Tk+4
DC and AC parameters
M65KA128AL
Figure 24. Self Refresh
M65KA128AL
DC and AC parameters
Figure 25. Deep Power-Down Entry AC Waveforms
T0
T1
T3
T2
T4
T5
K
KE
E
RAS
CAS
W
A10
DQ0-DQ15
Hi-Z
tRP
Precharge All Banks
(optional)
Deep Power-Down
Entry
ai07720c
1. BA0, BA1 and address bits A0 to A11 (except A10) are ‘Don’t Care’.
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W
CAS
RAS
E
KE
K
High
T2
1 Clock Cycle needed
T1
Precharge
All Banks
(optional)
200µs
High Level nedeed
Deep
Power-Down
Exit
DQ0-DQ15 Hi-Z
LDQM/
UDQM
Address
A10
BA1
BA0
1
T0
T6
EMR
Data (1)
T5
T7
tMRD
T8
Mode
Extended Mode Auto Refresh
Register Set Register Set
(optional)
(optional)
(optional)
tRP
T4
MR
Data (1)
tMRD
T3
T9
tRC1
T10
T11
T13
Auto Refresh
(optional)
T12
T14
T16
T17
T18
tRC1
T19
T20
T21
AI09954c
Bank/Row Activate
2 Refresh Cycles needed
T15
DC and AC parameters
M65KA128AL
Figure 26. Deep Power-Down Exit AC Waveforms
1. MR Data and EMR data are the values to be written to the Mode Register and the Extended Mode Register, respectively.
M65KA128AL
8
Part numbering
Table 15.
Ordering Information Scheme
Example:
Part numbering
M65KA128AL
10
W
5
Device Type
M65 = Low Power SDRAM
Delivery Form
K = Wafer Form
Operating Voltage, Mode, Bus Width
A = VDD = VDDQ = 1.8V, Standard LPSDRAM, x16
Array Organization
128 = 4 Banks x 2Mbit x 16
Option 1
A = One Chip Enable
Option 2
L = L Die
Speed Class
10 = 10ns
Package
W = Unsawn Wafer
Temperature Range
5 = –25 to 90°C
For a list of available options (Speed, Package, etc.) or for further information on any aspect
of this device, please contact the ST Sales Office nearest to you.
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Revision history
9
M65KA128AL
Revision history
Table 16.
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Document revision history
Date
Revision
Changes
28-Nov-2005
1
First Issue.
05-Jan-2006
2
Wafer and die specifications section removed.
28-Apr-2006
3
Datasheet status updated to Full Datasheet.
M65KA128AL
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