M68AW511A 4 Mbit (512K x8) 3.0V Asynchronous SRAM FEATURES SUMMARY ■ ■ ■ ■ ■ ■ ■ SUPPLY VOLTAGE: 2.7 to 3.6V 512K x 8 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 55ns LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER Figure 1. Packages 32 1 TSOP32 Type II (NC) SO32 (MC) September 2004 1/21 M68AW511A TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Table 1. Figure 3. Figure 4. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 TSOP and SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 7. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.. . . . . . . . . . . . . 11 Figure 9. Chip Enable Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 10.Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 11.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 12.Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 13.TSOP 32 Type II - 32 lead Plastic Thin Small Outline Type II, Package Outline . . . . . . 17 Table 10. TSOP32 Type II - 32 lead Plastic Thin Small Outline Type II, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 14.SO32 - 32 lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data. . . . . . . . . . . . . . . . . . 18 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/21 M68AW511A REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3/21 M68AW511A SUMMARY DESCRIPTION The M68AW511A is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68AW511A is available in two different packages: 32-lead TSOP Type II and 32-lead SO. Figure 2. Logic Diagram Table 1. Signal Names VCC 19 DQ0-DQ7 M68AW511A E G VSS AI05445c 4/21 Address Inputs DQ0-DQ7 Data Input/Output E Chip Enable G Output Enable W Write Enable VCC Supply Voltage VSS Ground 8 A0-A18 W A0-A18 M68AW511A Figure 3. TSOP and SO Connections A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 8 9 16 32 M68AW511A 25 24 17 VCC A15 A18 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 AI05446c 5/21 M68AW511A Figure 4. Block Diagram A18 ROW DECODER MEMORY ARRAY VCC VSS A8 DQ7 I/O CIRCUITS COLUMN DECODER DQ0 A0 A7 E W G AI05916 6/21 M68AW511A OPERATION The M68AW511A has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E = High). An Output Enable (G) signal provides a high speed tri-state control, allowing fast read/write cy- cles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W and E as summarized in the Operating Modes table (Table 2). Read Mode The M68AW511A is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E) is asserted. This provides access to data from eight of the 4,194,304 locations in the static memory array, specified by the 19 address inputs. Valid data will be available at the eight output pins within tAVQV after the last stable address, providing G is Low and E is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (t ELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX, but data lines will always be valid at tAVQV. Write Mode The M68AW511A is in the Write mode whenever the W and E pins are Low. Either the Chip Enable input (E) or the Write Enable input (W) must be deasserted during Address transitions for subsequent write cycles. Write begins with the concurrence of Chip Enable being active with W low. Therefore, address setup time is referenced to Write Enable and Chip Enable as tAVWL and tAVEH respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by the earlier rising edge of E, or W. if the Output is enabled (E = Low and G = Low), then W will return the outputs to high impedance within t WLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for t DVEH before the rising edge of E, whichever occurs first, and remain valid for tWHDX or tEHDX. Table 2. Operating Modes Operation E W G DQ0-DQ7 Power Output Disabled VIL X VIH Hi-Z Active (ICC) Read VIL VIH VIL Data Output Active (ICC) Write VIL VIL X Data Input Active (ICC) Deselect VIH X X Hi-Z Standby (ISB) Note: X = VIH or VIL. 7/21 M68AW511A MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3. Absolute Maximum Ratings Symbol Value Unit 20 mA Ambient Operating Temperature –55 to 125 °C TSTG Storage Temperature –65 to 150 °C VCC Supply Voltage –0.5 to 4.6 V –0.5 to VCC +0.5 V 1 W IO (1) TA VIO (2) PD Parameter Output Current Input or Output Voltage Power Dissipation Note: 1. One output at a time, not to exceed 1 second of duration. 2. Up to a maximum operating VCC of 3.6V only. 8/21 M68AW511A DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 4. Operating and AC Measurement Conditions Parameter M68AW511A VCC Supply Voltage 2.7 to 3.6V Range 1 0 to 70°C Range 6 –40 to 85°C Ambient Operating Temperature Load Capacitance (CL) 30pF Output Circuit Protection Resistance (R1) 3.0kΩ Load Resistance (R2) 3.1kΩ Input Rise and Fall Times 1ns/V 0 to VCC Input Pulse Voltages VCC/2 Input and Output Timing Ref. Voltages VOL = 0.3VCC; VOH = 0.7VCC Input and Output Transition Timing Ref. Voltages Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit VCC I/O Timing Reference Voltage R1 VCC VCC/2 DEVICE UNDER TEST 0V OUT CL I/O Transition Timing Reference Voltage VCC 0V R2 0.7VCC 0.3VCC AI04831 CL includes JIG capacitance AI03853 9/21 M68AW511A Table 5. Capacitance CIN COUT Test Condition Parameter(1,2) Symbol Input Capacitance on all pins (except DQ) Output Capacitance Min Max Unit VIN = 0V 6 pF VOUT = 0V 8 pF Max Unit Note: 1. Sampled only, not 100% tested. 2. At TA = 25°C, f = 1MHz, VCC = 3.0V. Table 6. DC Characteristics Symbol Parameter Test Condition Min Typ ICC1 (1,2) Operating Supply Current VCC = 3.6V, f = 1/tAVAV, IOUT = 0mA 30 mA ICC2 (3) Operating Supply Current VCC = 3.6V, f = 1MHz, IOUT = 0mA 5 mA ILI Input Leakage Current ILO (4) Output Leakage Current 0V ≤VIN ≤VCC –1 1 µA 0V ≤VOUT ≤VCC –1 1 µA 10 µA VCC = 3.6V, E ≥ VCC – 0.2V, f=0 ISB Standby Supply Current CMOS VIH Input High Voltage 2.2 VCC + 0.3 V VIL Input Low Voltage –0.3 0.6 V VOH Output High Voltage IOH = –1mA VOL Output Low Voltage IOL = 2.1mA Note: 1. 2. 3. 4. 10/21 Average AC current, cycling at tAVAV minimum. E = VIL, VIN = V IH or VIL. E ≤0.2V, VIN ≤0.2V or VIN ≥ V CC – 0.2V. Output disable. 5 2.4 V 0.4 V M68AW511A Figure 7. Address Controlled, Read Mode AC Waveforms tAVAV VALID A0-A18 tAVQV tAXQX DATA VALID DQ0-DQ7 AI03034 Note: E = Low, G = Low, W = High. Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms tAVAV A0-A18 VALID tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI03035 Note: Write Enable (W) = High. 11/21 M68AW511A Figure 9. Chip Enable Controlled, Standby Mode AC Waveforms E ICC1 ICC2 tPU tPD 50% AI03036 12/21 M68AW511A Table 7. Read and Standby Mode AC Characteristics M68AW511A Symbol Parameter Unit 55 70 tAVAV Read Cycle Time Min 55 70 ns tAVQV Address Valid to Output Valid Max 55 70 ns tAXQX (1) Data hold from Address change Min 5 5 ns tEHQZ (2,3) Chip Enable High to Output Hi-Z Max 20 25 ns tELQV Chip Enable Low to Output Valid Max 55 70 ns Chip Enable Low to Output Transition Min 5 5 ns tGHQZ (2,3) Output Enable High to Output Hi-Z Max 20 25 ns tGLQV Output Enable Low to Output Valid Max 25 35 ns Output Enable Low to Output Transition Min 5 5 ns tPD Chip Enable High to Power Down Max 55 70 ns tPU Chip Enable Low to Power Up Min 0 0 ns tELQX (1) tGLQX (1) Note: 1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC. 2. At any given temperature and voltage condition, tEHQZ is less than t ELQX and tGHQZ is less than t GLQX for any given device. 3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 13/21 M68AW511A Figure 10. Write Enable Controlled, Write AC Waveforms tAVAV VALID A0-A18 tAVWH tWHAX tAVEL E tWLWH tAVWL W tWLQZ tWHQX tWHDX DQ0-DQ7 DATA INPUT tDVWH AI03037 Figure 11. Chip Enable Controlled, Write AC Waveforms tAVAV A0-A18 VALID tAVEH tAVEL tELEH tEHAX E tWLEH W tEHDX DQ0-DQ7 DATA INPUT tDVEH AI05914 14/21 M68AW511A Table 8. Write Mode AC Characteristics M68AW511A Symbol Parameter Unit 55 70 tAVAV Write Cycle Time Min 55 70 ns tAVEH Address Valid to Chip Enable High Min 45 60 ns tAVEL Address Valid to Chip Enable Low Min 0 0 ns tAVWH Address Valid to Write Enable High Min 45 60 ns tAVWL Address Valid to Write Enable Low Min 0 0 ns tDVEH Input Valid to Chip Enable High Min 25 30 ns tDVWH Input Valid to Write Enable High Min 25 30 ns tEHAX Chip Enable High to Address Transition Min 0 0 ns tEHDX Chip Enable High to Input Transition Min 0 0 ns tELEH Chip Enable Low to Chip Enable High Min 45 60 ns tELWH Chip Enable Low to Write Enable High Min 45 60 ns tWHAX Write Enable High to Address Transition Min 0 0 ns tWHDX Write Enable High to Input Transition Min 0 0 ns tWHQX (1) Write Enable High to Output Transition Min 5 5 ns tWLEH Write Enable Low to Chip Enable High Min 45 60 ns Write Enable Low to Output Hi-Z Max 20 25 ns Write Enable Low to Write Enable High Min 45 60 ns tWLQZ (1,2) tWLWH Note: 1. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 15/21 M68AW511A Figure 12. Low VCC Data Retention AC Waveforms DATA RETENTION MODE 3.6V VCC 2.7V VDR > 1.5V tCDR tR E ≥ VDR – 0.2V E AI05447 Table 9. Low VCC Data Retention Characteristics Symbol Parameter ICCDR (1) Supply Current (Data Retention) Test Condition VCC = 1.5V, E ≥ VCC – 0.2V, f = 0 (3) tCDR (1,2) Chip Disable to Power Down tR (2) VDR (1) Operation Recovery Time Supply Voltage (Data Retention) Min E ≥ VCC – 0.2V, f = 0 Max Unit 4.5 9 µA 0 ns tAVAV ns 1.5 V Note: 1. All other Inputs at V IH ≥ VCC –0.2V or VIL ≤0.2V. 2. Tested initially and after any design or process may affect these parameters. t AVAV is Read cycle time. 3. No input may exceed VCC +0.2V. 16/21 Typ M68AW511A PACKAGE MECHANICAL Figure 13. TSOP 32 Type II - 32 lead Plastic Thin Small Outline Type II, Package Outline D N E1 1 E N/2 b e A2 A C A1 α L CP TSOP-e Note: Drawing is not to scale. Table 10. TSOP32 Type II - 32 lead Plastic Thin Small Outline Type II, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 1.20 Max 0.047 A1 0.05 0.15 0.002 0.006 A2 0.95 1.05 0.037 0.041 b 0.30 0.52 0.012 0.020 C 0.12 0.21 0.005 0.008 CP 0.10 D 20.82 21.08 – – E 11.56 E1 0.004 0.820 0.830 – – 11.96 0.455 0.471 10.03 10.29 0.395 0.405 L 0.40 0.60 0.016 0.024 α 0° 5° 0° 5° N 32 e 1.27 0.050 32 17/21 M68AW511A Figure 14. SO32 - 32 lead Plastic Small Outline, Package Outline D 16 1 E 17 E1 32 A2 B C CP A1 e A L1 SO-C L Note: Drawing is not to scale. Table 11. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data millimeters inches Symbol Typ Min A Typ Min 3.00 Max 0.118 A1 0.10 A2 2.57 2.82 0.101 0.111 B 0.36 0.51 0.014 0.020 C 0.15 0.30 0.006 0.012 D 20.14 20.75 0.793 0.817 E 11.18 11.43 0.440 0.450 E1 13.87 14.38 0.546 0.566 – – – – L 0.58 0.99 0.023 0.039 L1 1.19 1.60 0.047 0.063 e CP 18/21 Max 1.27 0.004 0.10 0.050 0.004 M68AW511A PART NUMBERING Table 12. Ordering Information Scheme Example: M68AW511 A L 55 NC 6 T Device Type M68 Mode A = Asynchronous Operating Voltage W = 2.7 to 3.6V Array Organization 511 = 4 Mbit (512K x8) Option 1 A = 1 Chip Enable Option 2 L = L-Die M = M-Die Speed Class 55 = 55ns 70 = 70ns Package NC = TSOP32 Type II MC = SO32 Operative Temperature 1 = 0 to 70°C 6 = –40 to 85°C Shipping T = Tape & Reel Packing For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 19/21 M68AW511A REVISION HISTORY Table 13. Document Revision History Date Version August 2001 1.0 First Issue. 27-Sep-2001 2.0 55ns speed class replaces 70ns. 27-Feb-2002 3.0 From Preliminary Data to Data Sheet. 70ns speed class added. Temperature Range 1 (0 to 70°C) added. Block Diagram clarified (Figure 4). Operating and AC Measurement Conditions table clarified (Table 4). AC Measurement Load Circuit clarified (Figure 6). DC Characteristics table clarified (Table 6). Write, Read and Standby Mode AC Characteristics tables clarified (Table 8 and 7). Chip Enable Controlled, Write AC Waveforms clarified (Figure 11). Low VCC Data Retention AC Waveforms and Characteristics clarified (Figure 12 and Table 9). 01-Mar-2002 4.0 SO32 package added. 25-Mar-2002 5.0 Read and Standby Mode AC Characteristics table clarified (Table 7). Low VCC Data Retention AC Waveforms and Characteristics clarified (Figure 12 and Table 9). 26-Apr-2002 6.0 DC Characteristics Table clarified (Table 6). Write Mode AC Characteristics Table clarified (Table 8). 17-Jun-2002 6.1 Minor changes. 09-Sep-2002 6.2 Load Capacitance (CL) changed from 100pF to 30pF (Table 4). 02-Oct-2002 6.3 New part number added. 09-Oct-2002 6.4 Commercial code modified. 12-Jun-2003 6.5 Correction to wording in Operating Modes table. 7.0 Document structure modified: – Chapter OPERATION moved before chapter MAXIMUM RATING. – AC Characteristics Tables and waveforms moved to the DC/AC PARAMETERS section. tPU ad tPD updated in Table 7. 24-Sep-2004 20/21 Revision Details M68AW511A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 21/21