M74HC597 8 BIT LATCH/SHIFT REGISTER ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 50 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 597 DESCRIPTION The M74HC597 is an high speed CMOS 8 BIT PIPO SHIFT REGISTER fabricated with silicon gate C2MOS technology. This devices comes in a 16-pin package and consist of an 8-bit storage latch feeding a parallel in, serial out 8-bit shift register. Both the storage DIP SOP TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP M74HC597B1R M74HC597M1R T&R M74HC597RM13TR M74HC597TTR register and shift register have positive edge triggered clocks. The shift register also has direct load (from storage) and clear inputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/14 M74HC597 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 9 QH’ 10 SCLR 11 SCK 12 RCK 13 SLOAD 10 15, 1, 2, 3, 4, 5, 6, 7 8 16 SI Serial Data Outputs Asynchronous Reset Input (Active LOW) Shift Clock Input (LOW to HIGH Edge-triggered) Storage Clock Input (LOW to HIGH Edge-triggered) Parallel Data Input (Active Low) Serial Data Input A to H Parallel Data Inputs GND Vcc Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OUTPUT SI SCK SCLR SLOAD RCK X X X X L H H L X X L H H X H H H X X H H X STATE OF S.R. IS NOT CHANGED X X X X INPUT DATA ON A ~ H LINE IS STORED INTO INPUT REGISTER X X X X STORAGE REGISTER STATE IS NOT CHANGED X : Don’t Care 2/14 S.R. IS CLEARED TO "L" INPUT REGISTER DATA IS STORED INTO S.R. FIRST STAGE OF S.R. BECOMES "L" OTHER STAGES STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY FIRST STAGE OF S.R. BECOMES "H" OTHER STAGES STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY M74HC597 LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 3/14 M74HC597 TIMING CHART ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 25 mA VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current PD Power Dissipation Tstg Storage Temperature TL Lead Temperature (10 sec) V ± 50 mA 500(*) mW -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C 4/14 M74HC597 RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Value Supply Voltage VI Input Voltage VO Output Voltage Top Operating Temperature Input Rise and Fall Time tr, tf Unit 2 to 6 V 0 to VCC V 0 to VCC V -55 to 125 °C VCC = 2.0V 0 to 1000 ns VCC = 4.5V 0 to 500 ns VCC = 6.0V 0 to 400 ns DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH VOL II ICC Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Value TA = 25°C VCC (V) Min. 2.0 4.5 6.0 2.0 4.5 6.0 Typ. Max. 1.5 3.15 4.2 -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 Max. 1.5 3.15 4.2 0.5 1.35 1.8 V 0.5 1.35 1.8 2.0 IO=-20 µA 1.9 2.0 1.9 1.9 4.5 IO=-20 µA 4.4 4.5 4.4 4.4 6.0 IO=-20 µA 5.9 6.0 5.9 5.9 4.5 IO=-4.0 mA 4.18 4.31 4.13 4.10 5.68 Unit V V 6.0 IO=-5.2 mA 2.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=20 µA 0.0 0.1 0.1 0.1 6.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=4.0 mA 0.17 0.26 0.33 0.40 6.0 IO=5.2 mA 0.18 0.26 0.33 0.40 6.0 VI = VCC or GND ± 0.1 ±1 ±1 µA 6.0 VI = VCC or GND 4 40 80 µA 5.8 5.63 5.60 V 5/14 M74HC597 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (SCK - QH’) tPLH tPHL Propagation Delay Time (SCLR - QH’) tPLH tPHL Propagation Delay Time (SLOAD - QH’) tPLH tPHL Propagation Delay Time (RCK- QH’) fMAX tW(H) tW(L) tW(L) ts ts ts th tREM 6/14 Maximum Clock Frequency Minimum Pulse Width (SCK, RCK) Minimum Pulse Width (SCLR, SLOAD) Minimum Set-up Time (RCK SLOAD) Minimum Set-up Time (SI, SCK) Minimum Set-up Time (PI, RCK) Minimum Hold Time Minimum Removal Time TA = 25°C VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Value Min. Typ. Max. 75 15 13 145 29 25 175 35 30 175 35 30 210 42 36 6.0 30 35 30 8 7 78 20 16 90 24 20 80 22 18 112 30 24 12 48 50 20 7 4 25 7 5 48 12 10 20 5 4 20 5 4 SLOAD = "L" 12 4 3 -40 to 85°C -55 to 125°C Min. Min. Max. 95 19 16 180 36 31 220 44 37 220 44 37 265 53 45 4.8 24 28 75 15 13 75 15 13 100 20 17 75 15 13 75 15 13 0 0 0 75 15 13 Max. 115 23 20 220 44 37 265 53 45 265 53 45 315 63 54 4.0 20 24 95 19 16 95 19 16 125 25 21 95 19 16 95 19 16 0 0 0 95 19 16 Unit ns ns ns ns ns MHz 110 22 19 110 22 19 150 30 26 110 22 19 110 22 19 0 0 0 115 23 20 ns ns ns ns ns ns ns M74HC597 CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) Value TA = 25°C Min. Typ. Max. 10 CIN Input Capacitance 5.0 5 CPD Power Dissipation Capacitance (note 1) 5.0 60 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : MINIMUM PULSE WIDTH, PROPAGATION DELAY TIME(f=1MHz; 50% duty cycle) 7/14 M74HC597 WAVEFORM 2 : MINIMUM PULSE WIDTH, PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) WAVEFORM 3 : MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle) 8/14 M74HC597 WAVEFORM 4 : MINIMUM SETUP AND HOLD TIME (f=1MHz; 50% duty cycle) WAVEFORM 5 : PROPAGATION DELAY, MINIMUM PULSE WIDTH, REMOVAL TIME (f=1MHz; 50% duty cycle) 9/14 M74HC597 WAVEFORM 6: MINIMUM SETUP TIME (f=1MHz; 50% duty cycle) WAVEFORM 7: INPUT WAVEFORM (f=1MHz; 50% duty cycle) 10/14 M74HC597 Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 11/14 M74HC597 SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8° (max.) PO13H 12/14 M74HC597 TSSOP16 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0° L 0.45 A 0.60 0.0256 BSC 8° 0° 0.75 0.018 8° 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 13/14 M74HC597 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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