RHF1201 Rad-hard 12-bit 0.5 to 50 Msps A/D converter Features ■ Wide sampling range: 0.5Msps to 50Msps ■ OptimwattTM adaptive power: 44mW @ 0.5Msps, 100mW @ 50Msps ■ Input range: 2 Vpp differential ■ SFDR up to 75dB @ FS = 50Msps, Fin = 15MHz ■ 2.5V / 3.3V compatible digital I/O ■ Built-in reference voltage with external bias capability ■ Hermetic package ■ Rad-hard: 300 kRad(Si) TID ■ Failure immune (SEFI) and latchup immune (SEL) up to 120 MeV-cm2/mg at 2.7V and 125°C ■ Qml-V qualified, smd 5962-05217 SO-48 package Pin connections (top view) Applications ■ Digital communication satellites ■ Space data acquisition systems ■ Aerospace instrumentation ■ Nuclear and high-energy physics 1 48 24 25 Specifically designed for optimizing power consumption, the RHF1201 can dissipate as little as 100mW at 50Msps, while maintaining a high level of performance. Description It integrates a proprietary track-and-hold structure to ensure IF-sampling applications up to 150 MHz. The RHF1201 is a 12-bit 50MHz maximum sampling frequency analog to digital converter using pure (ELDRS-free) CMOS 0.25µm technology combining high performance, radiation robustness and very low power consumption. A voltage reference is integrated in the circuit to simplify the design and minimize external components. A tri-state capability is available on the outputs to allow common bus sharing. Output data can be coded in two different formats. The RHF1201 is based on a pipeline structure and digital error correction to provide excellent static linearity and achieve 10.3 effective bits at FS = 50Msps, and Fin = 15MHz. A Data Ready signal which is raised when the data is valid on the output can be used for synchronization purposes. June 2007 The RHF1201 is available in -55° C to +125° C temperature range, in a small 48-pin hermetic SO-48 package. Rev 2 1/18 www.st.com 18 Contents RHF1201 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 6 6 Electrical characteristics (unchanged after 300kRad) . . . . . . . . . . . . . . 7 7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.1 RHF1201 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.2 Driving the analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.3 8 7.2.1 Differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.2.2 Single-ended input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2.3 IF-sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reference connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.3.1 Internal reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.3.2 External reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.4 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5 Power consumption optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.6 Layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Static parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/18 RHF1201 1 Block diagram Block diagram Figure 1. Block diagram VREFP +2.5V +2.5V/3.3V GNDA VIN stage 1 INCM stage 2 Reference circuit stage n VINB IPOL VREFM DFSB SRC Sequencer-phase shifting OEB CLK Timing Digital data correction DR DO Buffers TO D11 OR GND 2 Pin connections Figure 2. Pin connections (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 3/18 Pin descriptions RHF1201 3 Pin descriptions Table 1. Pin descriptions Pin Name Description 1 GNDBI Digital buffer ground 2 GNDBE 3 VCCBE Observation Pin Name Description Observation 0V 25 SRC Slew rate control input 2.5 V/3.3 V CMOS input Digital buffer ground 0V 26 OEB Output Enable input 2.5 V/3.3 V CMOS input Digital buffer power supply 2.5 V/3.3 V 27 DFSB Data Format Select input 2.5 V/3.3 V CMOS input 4 NC Non connected 28 AVCC Analog power supply 2.5 V 5 NC Non connected 29 AVCC Analog power supply 2.5 V Out Of Range output CMOS output (2.5 V/3.3 V) 30 AGND Analog ground 0V Most Significant Bit output CMOS output (2.5 V/3.3 V) 31 IPOL Analog bias current input 6 OR 7 D11(MSB) 8 D10 Digital output CMOS output (2.5 V/3.3 V) 32 VREFP Top voltage reference 1V 9 D9 Digital output CMOS output (2.5 V/3.3 V) 33 VREFM Bottom voltage reference 0V 10 D8 Digital output CMOS output (2.5 V/3.3 V) 34 AGND Analog ground 0V 11 D7 Digital output CMOS output (2.5 V/3.3 V) 35 VIN Analog input 1 Vpp 12 D6 Digital output CMOS output (2.5 V/3.3 V) 36 AGND Analog ground 0V 13 D5 Digital output CMOS output (2.5 V/3.3 V) 37 VINB Inverted analog input 1 Vpp 14 D4 Digital output CMOS output (2.5 V/3.3 V) 38 AGND Analog ground 0V 15 D3 Digital output CMOS output (2.5 V/3.3 V) 39 INCM Input common mode 0.5 V 16 D2 Digital output CMOS output (2.5 V/3.3 V) 40 AGND Analog ground 0V 17 D1 Digital output CMOS output (2.5 V/3.3 V) 41 AVCC Analog power supply 2.5 V 18 D0(LSB) Least Significant Bit output CMOS output (2.5 V/3.3 V) 42 AVCC Analog power supply 2.5 V 19 DR Data Ready output CMOS output (2.5 V/3.3 V) 43 DVCC Digital power supply 2.5 V 20 NC Non connected 44 DVCC Digital power supply 2.5 V 21 NC Non connected 45 DGND Digital ground 0V 22 VCCBE Digital Buffer power supply 2.5 V/3.3 V 46 CLK Clock input 2.5 V compatible CMOS input 23 GNDBE Digital Buffer ground 0V 47 DGND Digital ground 0V 24 VCCBI Digital Buffer power supply 2.5 V 48 DGND Digital ground 0V 4/18 RHF1201 4 Timing characteristics Timing characteristics Table 2. Timing table Symbol Parameter Test conditions Min Typ Max Unit FS Sampling frequency 0.5 50 MHz Tck Sampling clock cycle 20 2000 ns DC Clock duty cycle 65 % TC1 Clock pulse width (high) 10 1800 ns TC2 Clock pulse width (low) 8 1800 ns Tod Data output delay (fall of clock to data valid) Tpd Data pipeline delay Tdr Data ready delay after data change Ton Falling edge of OEB to digital output valid data 1 3 ns Toff Rising edge of OEB to digital output tri-state 1 3 ns FS = 45 Msps 45 10 pF load capacitance 50 4 5 6 ns 5.5 5.5 5.5 cycles 0.5 cycles SRC = 0 5 pF load capacitance 2.8 ns SRC = 1 5pF load capacitance 5.7 ns SRC = 0 5pF load capacitance 2 ns SRC = 1 5pF load capacitance 4.3 ns Data rising time TrD Data falling time TfD Figure 3. Timing diagram N+2 N+3 N+1 N+4 N N-3 N-2 N+5 N-1 N+6 CLK Tpd + Tod Tdr OEB DATA OUT Ton Toff Tod N-9 N-8 N-7 N-6 N-5 N-4 N-1 N-3 N DR HZ state 5/18 Absolute maximum ratings and operating conditions 5 RHF1201 Absolute maximum ratings and operating conditions Table 3. Absolute maximum ratings Symbol AVCC DVCC Parameter Analog supply voltage(1) Digital supply voltage (1) Values Unit 0 to 3.3 V 0 to 3.3 V VCCBI (1) Digital buffer supply voltage 0 to 3.3 V VCCBE Digital buffer supply voltage(1) 0 to 3.6 V IDout Digital output current -100 to 100 mA Tstg Storage temperature -65 to +150 °C Rthjc Junction - case thermal resistance 22 °C/W ESD Electrostatic discharge - HBM 2 kV 1. All voltage values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must never exceed -0.3 V or VCC +0.3 V. Table 4. Symbol 6/18 Operating conditions Parameter Test conditions Min Typ Max Unit AVCC Analog supply voltage 2.3 2.5 2.7 V DVCC Digital supply voltage 2.3 2.5 2.7 V VCCBI Digital internal buffer supply 2.3 2.5 2.7 V VCCBE Digital output buffer supply 2.3 2.5 3.4 V VREFP Forced top voltage reference 0.5 1 AVCC V VREFM Bottom internal reference voltage 0 0 0.5 V RHF1201 6 Electrical characteristics (unchanged after 300kRad) Electrical characteristics (unchanged after 300kRad) Test conditions, unless otherwise specified are: AVCC = DVCC = VCCB = 2.5 V, FS = 50 Msps, Fin = 2 MHz, VIN @ -1 dBSF, VREFP = Internal, VREFM = 0 V, Tamb = 25° C Table 5. Analog inputs Symbol Parameter VIN-VINB Test conditions Min Typ Max Unit Full scale reference voltage 2.0 Vpp Cin Input capacitance 7.0 pF Rin Input resistance 95 MHz Effective resolution bandwidth(1) ERB 1. See Section 8: Definitions of specified parameters on page 14 for more information. Table 6. Reference voltage Symbol Parameter Test conditions Min Typ Max Unit VREFP Top internal reference voltage AVCC from 2.3V to 2.7V Tmin = -55° C to Tmax = 125° C(1) 0.82 0.95 1.16 V Input common mode voltage AVCC=2.3 V to AVCC=2.7 V Tmin = -55° C to Tmax = 125° C(1) 0.43 052 0.67 V VINCM TempCo Temperature coefficients VREFP Tmin = -55° C to Tmax = 125° C(1) 0.12 mV/°C VINCM Tmin = -55° C to Tmax = 125° C(1) 0.12 mV/°C 1. Not fully tested over the temperature range. Guaranteed by sampling. Table 7. Digital inputs and outputs Symbol Parameter Test conditions Min Typ Max Unit 0 0.8 V Clock input VIL Logic "0" voltage VIH Logic "1" voltage 2.0 2.5 V Digital inputs VIL Logic "0" voltage VIH Logic "1" voltage 0 0.75 VCCBE VCCBE 0.25 VCCBE V V 7/18 Electrical characteristics (unchanged after 300kRad) Table 7. RHF1201 Digital inputs and outputs (continued) Symbol Parameter Test conditions Min Typ Max Unit 0 0.2 V Digital outputs VOL Logic "0" voltage IOL = -1mA VOH Logic "1" voltage IOH = 1mA IOZ High impedance leakage current OEB set to VIH CL Output load capacitance Table 8. VCCBE - 0.2 V -15 15 µA 15 pF Max Unit Accuracy Symbol Parameter Test conditions Min Typ OE Offset error Fin = 2 MHz, VIN @ +1 dBFS ±0.3 % DNL Differential non linearity(1) Fin = 2 MHz, VIN @ +1 dBFS ±0.5 LSB INL Integral non linearity(1) Fin = 2 MHz, VIN @ +1 dBFS ±1.7 LSB - Monotonicity and no missing codes Guaranteed 1. See Section 8: Definitions of specified parameters on page 14 for more information. Table 9. Symbol SFDR Dynamic characteristics Parameter(1) Spurious free dynamic range Test conditions(2) Typ Max Unit Fin = 15 MHz -75 -63 dBc Fin = 95 MHz -70 Fin = 145 MHz -57 dBc 63 dB Fin = 95 MHz 60 dB Fin = 145 MHz 59 Fin = 15 MHz -76 Fin = 95 MHz -72 Fin = 145 MHz -58 Fin = 15 MHz SNR THD Signal to noise ratio Total harmonics distortion Fin = 15 MHz SINAD Signal to noise and distortion ratio Effective number of bits 59 59 8/18 dB dB dB 60 Fin = 145 MHz 56.5 dB 10.3 bits Fin = 95 MHz 9.5 bits Fin = 145 MHz 9.1 9.7 1. See Section 8: Definitions of specified parameters on page 14 for more information. 2. VREFP = 1 V with external supply. 63 -64 Fin = 95 MHz Fin = 15 MHz ENOB Min RHF1201 7 Application information Application information The RHF1201 is a high speed analog to digital converter based on a pipeline architecture and a 0.25 µm CMOS process to achieve the best performance in terms of linearity and power consumption. The pipeline structure consists of 11 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. Signal input is sampled on the rising edge of the clock. The first 10 stages of the conversion include at each stage, an analog to digital converter, a digital to analog converter, a Sample and Hold, and an amplifier with a gain of 2. A 1.5 bit conversion resolution is also performed at each stage. The final stage is simply a comparator. Each resulting LSB-MSB couple is then time shifted to recover from the delay caused by the conversion. Digital data correction completes the processing by recovering from the redundancy of the (LSB-MSB) couple at each stage. The corrected data is output through the digital buffers. The advantages of such a converter reside in the combination of pipeline architecture and the most advanced technologies. The highest dynamic performances are achieved while consumption remains at the lowest level. 7.1 RHF1201 operating modes Extra functionalities are provided to simplify the application board as much as possible. The operation modes offered by the RHF1201 are described in the following table. Table 10. RHF1201 operating modes Inputs Analog input differential level Outputs DFSB OEB SRC OR DR Most significant bit (MSB) (VIN-VINB) > RANGE H L X H CLK D11 -RANGE > (VIN-VINB) H L X H CLK D11 RANGE> (VIN-VINB) >-RANGE H L X L CLK D11 (VIN-VINB) > RANGE L L X H CLK D11 Complemented -RANGE > (VIN-VINB) L L X H CLK D11 Complemented RANGE> (VIN-VINB) >-RANGE L L X L CLK D11 Complemented X X H X HZ HZ HZ X X X H X CLK Low slew rate X X X L X CLK High slew rate Data format select (DFSB) When set to low level (VIL), the digital input DFSB provides a two’s complement digital output MSB. This can be of interest when performing some further signal processing. When set to high level (VIH), DFSB provides a standard binary output coding. 9/18 Application information RHF1201 Output enable (OEB) When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital output buffers are in high impedance state while the converter goes on sampling. When OEB is set to a low level again, the data arrives on the output with a very short Ton delay. This mechanism allows the chip select of the device. Figure 3: Timing diagram on page 5 summarizes this functionality. Slew rate control (SRC) When set to high level (VIH), all digital output currents are limited to a clamp value so that digital noise power is reduced to the minimum. When set to low level (VIL), the output edges are twice as fast. Out of range (OR) This function is implemented on the output stage in order to set an “Out of Range” flag whenever the digital data is over the full scale range. Typically, there is a detection of all the data at ’0’ or all the data at ’1’. It sets an output signal OR which is in low level state (VOL) when the data stays within the range, or in high level state (VOH) when the data is out of range. Data ready (DR) The Data Ready output is an image of the clock being synchronized on the output data (D0 to D11). This is a very helpful signal that simplifies the synchronization of the measurement equipment or of the controlling DSP. As all other digital outputs, DR goes into high impedance state when OEB is set to high level as shown in Figure 3: Timing diagram on page 5. 7.2 Driving the analog input 7.2.1 Differential inputs The RHF1201is designed to obtain optimum performance when driven on differential inputs. An RF transformer is an efficient way of achieving this high performance. Figure 4: Differential input configuration describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. The common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set close to 0.5V. The INCM is de-coupled to maintain a low noise level on this node. Our evaluation board is mounted with a 1:1 ADT1-1 transformer from Minicircuits. You might also use a higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal source. Each analog input can drive a 1 Vpp amplitude input signal, so the resulting differential amplitude is 2 Vpp. 10/18 RHF1201 Application information Figure 4. Differential input configuration Analog source ADT1-1 1:1 VIN 50Ω RHF1201 10-100pF VINB 330pF 7.2.2 10nF INCM 470nF Single-ended input configuration Some applications may require a single-ended input which is easily achieved with the configuration shown in Figure 5: Single-ended input configuration. The lack of accurate differential driving with its common-mode noise and even harmonics cancellation advantages can degrade the rated RHF1201 performance. It is then recommended to use a well de-coupled DC reference to bias the RHF1201 inputs. In this case, one can use an AC-coupled analog input and set the DC analog level with high value (10 kΩ to 100 kΩ) resistor connected to a proper DC source. The internal references INCM (0.52 V) or REFP (1 V) can be used as proper DC sources. Using 1 V DC with a single signal of 2 Vpp input amplitude gives better SNR performance. Figure 5. Single-ended input configuration Signal source 10nF VIN 50Ω 10-100kΩ RHF1201 VINB 330pF 7.2.3 10nF 470nF DC source or REFP IF-sampling The RHF1201 is specifically designed to meet sampling requirements for intermediate frequency input signals. In particular, the Track-and-Hold in the first stage of the pipeline is designed to minimize the linearity limitations as analog frequency increases.This is achieved by making the input impedance independent from the input frequency. As a result, the RHF1201 can maintain high performance up to an analog frequency of 150 MHz. 11/18 Application information RHF1201 7.3 Reference connection 7.3.1 Internal reference In the standard configuration, the ADC is biased with the internal reference voltage. The VREFM pin is connected to Analog Ground while VREFP is internally set to a voltage close to 1.0 V. It is recommended to de-couple the VREFP in order to minimize low and high frequency noise. Refer to Figure 6: Internal reference setting for the schematics. Figure 6. Internal reference setting ~1V VIN 330pF 10nF 470nF VREFP RHF1201 VINB VREFM 7.3.2 External reference It is possible to use an external reference voltage instead of the internal one for specific applications requiring even better linearity or enhanced temperature behavior. In this case, the amplitude of the external voltage must be at least equal to the internal one (1.0 V). You can use an external voltage reference with the configuration shown in Figure 7: External reference setting to obtain optimum performance. Figure 7. External reference setting 1kΩ 330pF VCCA VREFP VIN RHF1201 10nF 470nF external reference VINB VREFM This can be very helpful in multichannel applications for example to maintain a good matching along the sampling frequency range. 12/18 RHF1201 7.4 Application information Clock input The quality of your converter is very dependent on your clock input accuracy, in terms of aperture jitter; the use of a low jitter crystal controlled oscillator is recommended. Further points to consider in your implementation are: 7.5 ● The input signal must be square-shaped with sharp edges of less than 1 ns. ● At 45 Msps, the duty cycle must be between 45% and 65%; in any case, the high level duration of Clock must be longer than 10 ns. ● The clock power supplies must be independent from the ADC output supplies to avoid digital noise modulation on the output. ● When powered-on, the circuit needs several clock periods to reach its normal operating conditions. Power consumption optimization The internal architecture of the RHF1201 makes it possible to optimize power consumption according to the sampling frequency of the application. For this purpose, an External Rpol resistor is placed between the IPOL pin and the analog Ground. Therefore, the total dissipation can be adjusted across all the sampling range 0.5 Msps to 50 Msps to fulfil the requirements of applications where power saving is a must. For low sampling frequency, this value of resistor may be adjusted in order to decrease the analog current without any degradation of dynamic performance. Table 11 sums up the relevant data. Table 11. 7.6 Total power consumption optimization depending on Rpol value FS (Msps) 0.85 1.7 13.6 45 50 Rpol (kΩ) 100 70 35 24 18 Optimized power (mW) 44 47 60 93 100 Layout precautions ● Use of dedicated ground planes (analog, digital, internal and external buffer ones) on the PCB is recommended for high speed circuit applications to provide low inductance and low resistance common return. ● The separation of the analog signal from the digital output part is mandatory to prevent noise from coupling onto the input signal. ● Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. ● All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. ● Keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. ● Choose component sizes as small as possible (SMD). 13/18 Definitions of specified parameters 8 RHF1201 Definitions of specified parameters Static parameters Static measurements are performed using the histograms method on a 2 MHz input signal, sampled at 50 Msps, which is high enough to fully characterize the test frequency response. The input level is +1 dBFS to saturate the signal. Differential non linearity (DNL) The average deviation of any output code width from the ideal code width of 1 LSB. Integral non linearity (INL) An ideal converter exhibits a transfer function which is a straight line from the starting code to the ending code. The INL is the deviation from this ideal line for each transition. Dynamic parameters Dynamic measurements are performed by spectral analysis, applied to an input sine wave of various frequencies and sampled at 50 Msps. Spurious free dynamic range (SFDR) The ratio between the power of the worst spurious signal (not always an harmonic) and the amplitude of fundamental tone (signal power) over the full Nyquist band. It is expressed in dBc. Total harmonic distortion (THD) The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB. Signal to noise ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (fs/ 2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB. Signal to noise and distortion ratio (SINAD) Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. The effective number of bits (ENOB) is easily deduced from the SINAD, using the formula: SINAD = 6.02 × ENOB + 1.76 dB. When the applied signal is not full scale (FS), but has an amplitude A0, the SINAD expression becomes: SINAD = 6.02 × ENOB + 1.76 dB + 20 log (2A0/FS) The ENOB is expressed in bits. 14/18 RHF1201 Definitions of specified parameters Effective resolution bandwidth For a given sampling rate and clock jitter, the analog input frequency at which the SINAD is reduced of 3 dB. Pipeline delay Delay between the initial sample of the analog input and the availability of the corresponding digital data output on the output bus. Also called data latency. It is expressed as a number of clock cycles. 15/18 Package information 9 RHF1201 Package information Figure 8. SO-48 package Dimensions Ref. Millimeters Min. Typ. Max. Min. Typ. Max. A 2.18 2.47 2.72 0.086 0.097 0.107 b 0.20 0.254 0.30 0.008 0.010 0.012 c 0.12 0.15 0.18 0.005 0.006 0.007 D 15.57 15.75 15.92 0.613 0.620 0.627 E 9.52 9.65 9.78 0.375 0.380 0.385 E1 16/18 Inches 10.90 0.429 E2 6.22 6.35 6.48 0.245 0.250 0.255 E3 1.52 1.65 1.78 0.060 0.065 0.070 e 0.635 0.025 f 0.20 0.008 L 12.28 12.58 12.88 0.483 0.495 0.507 P 1.30 1.45 1.60 0.051 0.057 0.063 Q 0.66 0.79 0.92 0.026 0.031 0.036 S1 0.25 0.43 0.61 0.010 0.017 0.024 RHF1201 10 Ordering information Ordering information Part number 11 Temperature range Package Marking RHF1201KSO1 -55 °C to 125 °C SO-48 RHF1201KSO1 RHF1201KSO2 -55 °C to 125 °C SO-48 RHF1201KSO2 RHF1201KSO-01V -55 °C to 125 °C SO-48 F0521701VXC Revision history Date Revision 01-Sep-2006 1 Changes Initial release in new format. Updated failure immune and latchup immune value to 120 MeV- cm2/mg. 29-Jun-2007 2 Updated package mechanical data. Removed reference to non rad-hard components from Section 7.3.2: External reference on page 12. 17/18 RHF1201 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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