ST7162 UNIVERSAL PROGRAMMABLE DUAL PLL PRODUCT PREVIEW TWO INDEPENDENT PLL WITH 16 BITS PROGRAMMABLE DIVIDERS FROM 13 TO 65535 FOR TRANSMIT AND RECEIVE LOOPS ON CHIP REFERENCE OSCILLATOR COMMON FOR THE TWO LOOPS UP TO 16MHz WITH EXTERNAL CRYSTAL TWO INDEPENDENT PROGRAMMABLE REFERENCE COUNTERS: - 12 bits programmable counter from 13 to 4095 followed by selectable dividers by 1, 4 and 25 - 14 bits auxiliary programmable counter from 13 to 16383 A MCU CLOCK DERIVED FROM REFERENCE OSCILLATOR WITH A SELECTABLE DIVISION FACTOR OF 3 OR 4 TWO INDEPENDENT PFD (PHASE FREQUENCY DISCRIMINATOR) WITH 3 STATE OUTPUTS LOCK DETECT SIGNAL OUTPUT FOR THE TRANSMIT LOOP 3 & 4 WIRES SELECTABLE MCU SERIAL INTERFACE, FOR SIMULTANEOUS PROGRAMMING OF 2 COUNTERS STAND-BY MODE DIP16 ORDERING NUMBER: ST7162N SO16 ORDERING NUMBER: ST7162D PIN CONNECTION (Top view) MAIN CHARACTERISTICS High input sensitivity: 200mVpkpk @ 60MHz Low consumption: 3.5mA @ 3V for the two loops Power supply voltage: 3V to 5V Operating temperature range: –25°C to +70°C DESCRIPTION The ST7162 is a dual frequency synthesizer in High Speed CMOS technology for radio applications with a frequency up to 60MHz. The low power consumption and high flexibility make it well suitable for cordless CT0 applications in various countries. July 1993 1/17 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. ST7162 BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VDD - VSS VIN VOUT Value Unit – 0.5 to +6 V Input Voltage VSS –0.5 to VDD +0.5 V Output Voltage VSS –0.5 to VDD +0.5 V – 10 to 10 mA – 30 to 30 mA – 55 to +125 °C IIN, IOUT DC Current per pin IDD, ISS DC Current for pin VDD or VSS Tstg 2/17 Parameter Supply Voltage Storage Temperature ST7162 PIN FUNCTIONS N. Name Function 1 CLOCK 2 AUX DATA IN MCU Interface MCU Interface 3 DATA IN MCU Interface 4 ENABLE MCU Interface 5 MCU CLOCK 6 VSS 7 OSC OUT 8 OSC IN Oscillator Input Scaled down reference frequency for clocking the MCU Negative Power Supply Oscillator Output 9 FIN RX Input to the 16 bits Receive Counter 10 PD RX Phase detector output of the Receive loop 11 Out RX Power saving output bit for the RX loop and FIN RX divided by N1 for testing the RX input sensitivity. 12 VDD 13 OUT TX Power saving output bit for the TX loop and FIN TX divided by N2 for testing the TX input sensitivity. 14 FIN TX Input to the 16 bits Transmit counter. 15 PD TX Phase detector output of the transmit loop 16 LD Positive power supply Lock detect output of the transmit loop. ELECTRICAL CHARACTERISTICS (Tamb = 25°C, voltage reference = VSS) Symbol Parameter Test Condition VDD Min. Typ. Max. Unit SUPPLY VDD Supply Voltage IDD up Supply Current 200mVpkpk sinus at input; FIN RX = 36MHz, FIN TX =49MHz; loop in lock condition; fosc = 10.24MHz; no output load 3V 3 5.5 V 3.7 mA 5V 7.7 mA IDDRX Supply Current 200mVpkpk sinus at input; FIN RX = 36MHz; TX Loop in Power down; fosc = 10.24MHz; no output load 3V 2.5 mA 5V 5.3 mA IDD down Supply Current Stand-by mode for all counters; OSCIN pin Grounded; MCU interface disabled 3V 150 µA 5V 300 µA 3V 5V TX and RX INPUTS C IN Input Capacitance IIN up Input Current 0 < VIN < VDD Fmax Input Frequency Input = sinus 200mVpkpk AC coupled – 60 – 100 3-5V 8 pF 60 100 µA µA 60 MHz OSCILLATOR C IN Input Capacitance 8 pF COUT Output Capacitance 8 pF IIN up Input Current 60 100 µA µA Fmax Input Frequency 16 MHz 0 < VIN < VDD DC measured 3V 5V 3-5V – 60 – 100 3/17 ST7162 ELECTRICAL CHARACTERISTICS (Tamb = 25°C, voltage reference = VSS) Symbol Parameter Test Condition VDD Min. Typ. Max. Unit 8 pF PHASE FREQUENCY DISCRIMINATOR COUT Output Capacitance IOUT HI Output Current IOUT LO ILEAK Output Current Leakage Current Source VOUT = 2.7V VOUT = 4.5V 3V 5V – 200 – 500 µA µA Sink VOUT = 0.3V VOUT = 0.5V 3V 5V 200 500 µA µA 5V – 50 50 nA 8 pF 3-5V – 10 10 µA 3V 2.3 V 5V 3.8 V Three state output VPDTX, VPDRX = 0 or 5V MCU INTERFACE INPUTS C IN Input Capacitance IIN Input Current DC measured VIN = VDD or VSS VIH Input Voltage High level ”1” VIL Fmax TW TSU THOLD TREC Input Voltage Low level ”0” Input Frequency Maximum frequency at clock input Pulse width Clock and Enable inputs Set-up Time Hold Time Recovery Time 3V 0.7 V 5V 1.2 V 3-5V 500 KHz 3V 80 ns 5V 60 ns Data to clock 3-5V 100 ns Enable to clock 3-5V 200 ns 3V 80 ns 5V 40 ns 3V 80 ns 5V 40 ns Clock to data Enable to Clock DIGITAL OUTPUTS: OUTTX, OUTRX, MCUCLOCK, LD CLOAD Output Load Capacitance VOUT IH Output Voltage VOUT LO IOUTHI IOUTLO 4/17 Output Voltage Output Current Output Current 25 IOUT = 0, High level ”1” IOUT = 0, Low level ”0” pF 3V 2.95 V 5V 4.95 V 3V 0.05 V 5V 0.05 V Source VOUT = 2.7V VOUT = 4.5V 3V 5V – 200 – 500 µA µA Sink VOUT = 0.3V VOUT = 0.5V 3V 5V 200 500 µA µA 3V 200 ns 5V 100 ns 3V 200 ns 5V 100 ns THI Output rise Time CLOAD = 25pF TLO Output Fall Time CLOAD = 25pF ST7162 Figure 1: Control Unit Block Diagram Sumary of Internal Registers Adress Register Number of Data Bits Function A2 A1 A0 R0 0 0 0 13 CIRCUIT CONTROL R1 0 0 1 16 BINARY VALUE OF N1 = RX RATIO R2 0 1 0 16 BINARY VALUE OF N2 = TX RATIO R3 0 1 1 12 BINARY VALUE OF N3 = REF RATIO R4 1 0 0 14 BINARY VALUE OF N4 = AUX REF RATIO 5/17 ST7162 Description of Control Register Bit Name Function D12 TEST 1 D11 TEST 2 D10 TEST 3 D9 AUXILIARY DATA SELECT D8 REFOUT/3 D7 TXCE TX Counter Enable bit: if set to 0, TX amplifier, counter and PFD will be in power down mode and OUTTX pin will be set to 1. D6 RXCE RX Counter Enable bit: if set to 0, RX amplifier, counter and PFD will be in power down mode and OUTRX pin will be set to 1. D5 RCE Reference Counter Enable bit: if set to 0, ref counter will be in power down mode. D4 ARCE D3 MUX SELECT 1 D2 MUX SELECT 2 D1 MUX SELECT 3 D0 MUX SELECT 4 Test Mode: See Table 1. Set to 0 to select 3 wires serial data bus mode at the next pattern Set to 1 to select 4 wires serial data bus mode at the next pattern Set to 0, MCUCLOCK frequency = OSC.OUT frequency / 4 Set to 1, MCUCLOCK frequency = OSC.OUT frequency / 3 Auxiliary Reference Counter Enable bit: if set to 0, AUX Ref counter will be in power down mode Used to connect internally PFD inputs REFTX and REFRX to the chosen Ref frequency output: see Table 2. Table 1. TEST1 TEST2 TEST3 Status of output pin OUTTX Status of output pin OUTRX Status of TX and RX PFD 0 0 0 CONTROL BIT TXCE CONTROL BIT RXCE NORMAL OPERATION 0 0 1 INTERNAL POINT REFTX INTERNAL POINT REFRX TEST MODE NORMAL IUP 0 1 0 INTERNAL POINT FINTX/N2 INTERNAL POINT FINRX/N1 TEST MODE NORMAL IDOWN 0 1 1 INTERNAL POINT FINTX/N2 INTERNAL POINT FINRX/N1 TEST MODE I LEAKAGE 1 0 0 CONTROL BIT TXCE CONTROL BIT RXCE OPERATION WITH INCREASED IUP AND IDOWN 1 0 1 INTERNAL POINT REFTX INTERNAL POINT REFRX TEST MODE INCREASED IUP 1 1 0 INTERNAL POINT FINTX/N2 INTERNAL POINT FINRX/N1 TEST MODE INCREASED IDOWN 1 1 1 INTERNAL POINT FINTX/N2 INTERNAL POINT FINRX/N1 TEST MODE I LEAKAGE 6/17 ST7162 Figure 2: Reference Frequency Diagram. Table 2. INPUT OF RX PFD INPUT OF TX PFD REFTX CONNECTED REFRX CONNECTED TO INTERNAL POINT TO INTERNAL POINT (see Note 2) (see Note 1) MUX SELECT 1 MUX SELECT 2 MUX SELECT 3 MUX SELECT 4 0 0 0 0 FREF 0 0 0 1 FREF FREF/4 0 0 1 0 FREF FREF/25 0 0 1 1 FREF AUXFREF 0 1 0 0 FREF/4 FREF 0 1 0 1 FREF/4 FREF/4 0 1 1 0 FREF/4 FREF/25 0 1 1 1 FREF/4 AUXFREF 1 0 0 0 FREF/25 FREF 1 0 0 1 FREF/25 FREF/4 1 0 1 0 FREF/25 FREF/25 1 0 1 1 FREF/25 AUXFREF 1 1 0 0 AUXFREF FREF 1 1 0 1 AUXFREF FREF/4 1 1 1 0 AUXFREF FREF/25 1 1 1 1 AUXFREF AUXFREF FREF Note (1): If the 12 bits REF. counter is disabled (RCE control bit = 0) then the inputs of RX and TX PFD (REF TX and REF RX) are connected to internal point AUX REF. Note (2): If the 14 bits auxiliary reference counter is disabled (ARCE control bit = 0) then the internal point AUXFREF is replaced by FREF/ 25. 7/17 ST7162 PROGRAMMING THE REGISTER (Figs 3 to 8) When a Low level is present on the ENABLE input, information on the DATA and AUX DATA inputs are used to program the internal registers. Data are shifted at the rising edge of the clock input. First the 3 address bits of a register are sent, followed by 12 to 16 data bits, depending on the lenght of the register. The address is latched at the 3rd clock impulse following a falling edge at ENABLE input. This configuration allows to send various lenght patterns. Moreover, fixed patterns of 24 or 32 bits can be sent if dummy bits are inserted between the address bits and the first data bit. After the last data bit, a rising edge of the ENABLE input latches the information. When the VDD supply is switched on, an internal circuit pro- vides a reset of the control register bits. When the serial bus is not used, a Low level at clock input and a HIGH level at ENABLE inputs are applied. PROGRAMMING THE 3/4 WIRES MODE When the Auxiliary Data select bit of the control register is set to 1, the serial bus is switched in 4 wires mode at the next pattern. Then one or other of the 5 registers may be serially loaded by one or other of the DATA or AUX DATA inputs. When loading simultaneously 2 registers with different lenght, dummy bits are inserted between the address bits and the data bits of the shorter register (see fig. 8). Figure 3: 3 Wires Serial Data Transmission Timing X = DON’T CARE DATA ADDRESS A2 0 8/17 A1 0 A0 0 D12 TEST 1 D11 TEST 2 D10 TEST 3 D9 AUX. DATA SELECT D8 REF OUT/3 D7 TX COUNTER ENABLE D6 RX COUNTER ENABLE D5 REF. COUNTER ENABLE D4 AUX. REF. COUNTER ENABLE D3 MUX SELECT 1 D2 MUX SELECT 2 D1 MUX SELECT 3 D0 MUX SELECT 4 ST7162 Figure 4: 3 Wires Serial Data Transmission Timing X = DON’T CARE ADDRESS DATA A2 A1 A0 REGISTER 0 0 1 R1 : RX COUNTER 0 1 0 R2 : TX COUNTER D15 : : : D0 MSB = 32768 LSB = 1 Figure 5: 3 Wires Serial Data Transmission Timing X = DON’T CARE ADDRESS DATA A2 A1 A0 REGISTER 0 1 1 R3 : REF. COUNTER D11 : : : D0 MSB = 2048 LSB = 1 9/17 ST7162 Figure 6: 3 Wires Serial Data Transmission Timing X = DON’T CARE DATA ADDRESS A2 A1 A0 REGISTER 1 0 0 R4 : AUX REF. COUNTER D13 : : : D0 MSB = 8192 LSB = 1 Figure 7: 4 Wires Serial Data Transmission Timing ADDRESS DATA A2 AUX A2 A1 AUX A1 A0 AUX A0 REGISTER 0 0 1 R1 : RX COUNTER 0 1 0 R2 : TX COUNTER 10/17 D15, AUX D15 : : : D0, AUX D0 MSB = 32768 LSB = 1 ST7162 Figure 8: 4 Wires Serial Data Transmission Timing X = DON’T CARE ADDRESS A2 AUX A2 A1 AUX A1 A0 AUX A0 REGISTER 0 1 1 R3 : REF COUNTER 1 0 0 R4 : AUX REF. COUNTER DATA D11 : : : D0 MSB = 2048 LSB = 1 AUX DATA AUX D13 : : : AUX D0 MSB = 8192 LSB = 1 11/17 ST7162 PFD DESCRIPTION (pin 10 & 15) Outputs PDTX or PDRX produce an output pulse current, sourcing or sinking, whose width depends on the delay between falling edges of reference frequency and RF frequency divided. Sim- plified schematic of both PFD is described in figure 10. When the current output is off, PFD is in high impedance state. The voltage at PFD outputs pins depends on the loop filter and VCO characteristics (Fig. 9) Figure 9: PD Output Current vs. FIN / REF. Frequencies. REF RX (REF TX) FIN RX / N1 (FIN TX / N2) OUTPUT CURRENT TRI-STATE D93TL012 Figure 10: Simplified schematic of PFD outputs. VDD I up PDTX, PDRX I down OUTPUT CURRENT VSS to VCO LOOP FILTER D93TL013 When the loop is locked, to prevent a dead area in the PFD gain due to switching delays, a very short phase offset is introduced in the loop, so the PFD output current show the following waveform Fig. 11. Figure 11: PD output current in locked condition. T = 1/REF OUTPUT CURRENT TRI-STATE t1 = 1/OSC IN Freq. 12/17 D93TL014 ST7162 Figure 12: Switching diagrams. TW CLOCK ENABLE 50% 50% TLO THI 90% 90% OUTTX, OUTRX MCU CLOCK, LD 10% 10% D93TL015 ENABLE 50% 50% TREC CLOCK TSU 50% TSU DATA IN, AUX DATA IN 50% FIRST CLOCK 50% LAST CLOCK THOLD 50% D93TL016 13/17 ST7162 Figure 13: Test Circuit. 14/17 ST7162 DIP16 PACKAGE MECHANICAL DATA mm DIM. MIN. a1 0.51 B 0.77 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 15/17 ST7162 SO16 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. A a1 inch MAX. TYP. 2.65 0.1 MAX. 0.104 0.2 a2 0.004 0.008 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45° (typ.) D 10.1 10.5 0.397 0.413 E 10.0 10.65 0.393 0.419 e 1.27 0.050 e3 8.89 0.350 F 7.4 7.6 0.291 0.300 L 0.5 1.27 0.020 0.050 M S 16/17 MIN. 0.75 0.029 8° (max.) ST7162 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 17/17