ST7540
FSK power line transceiver
General features
■
Half-duplex frequency shift keying (FSK)
transceiver
■
Integrated power line driver with programmable
voltage and current control
■
Programmable mains access:
– Synchronous
– Asynchronous
HTSSOP28 Exposed Pad
■
Single supply voltage (from 7.5V up to 13.5V)
■
Very low power consumption (Iq = 5mA)
■
Integrates 5V voltage regulator (up to 50mA)
with short circuit protection
■
Integrated 3.3V voltage regulator (up to 50mA)
with short circuit protection
■
3.3V or 5V digital supply
■
8 Programmable transmission frequencies
■
Programmable baud rate up to 4800BPS
■
Receiving sensitivity up to 250µVRMS
■
Suitable for applications in accordance with EN
50065 Cenelec specification
■
Carrier or preamble detection
■
Band in use detection
■
Programmable control register
■
Watchdog timer
■
8 or 16 Bit header recognition
■
ST7537 and ST7538 compatible
■
UART/SPI host interface
Description
The ST7540 is a Half Duplex
synchronous/asynchronous FSK Modem
designed for power line communication network
applications. It operates from a single supply
voltage and integrates a line driver and two linear
regulators for 5V and 3.3V. The device operation
is controlled by means of an internal register,
programmable through the synchronous serial
interface. Additional functions as watchdog, clock
output, output voltage and current control,
preamble detection, time-out and band in use are
included. Realized in Multipower BCD5
technology that allows to integrate DMOS, Bipolar
and CMOS structures in the same chip.
Order codes
Part number
Package
Packaging
ST7540
HTSSOP28 (Exposed Pad)
Tube
ST7540TR
HTSSOP28 (Exposed Pad)
Tape and reel
September 2006
Rev 2
1/44
www.st.com
44
Contents
ST7540
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
2.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Crystal resonator and external clock . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/44
6.1
Carrier frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2
Baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3
Mark and space frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4
ST7540 Mains access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.5
Host processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.5.1
Communication between Host and ST7540 . . . . . . . . . . . . . . . . . . . . . 20
6.5.2
Control register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6
Receiving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.7
Transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.8
Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ST7540
7
Contents
Auxiliary analog and digital functions . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1
Band in use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2
Time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.3
Reset & watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.4
Output clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.5
Output voltage level freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.6
Extended control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.7
Under voltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.8
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.9
5V Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.10
3.3V Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.11
Power-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8
Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3/44
Block diagram
ST7540
1
Block diagram
Figure 1.
Block diagram
CARRIER
DETECTION
CD/PD
RxD
UART/SPI
TEST
BU
FSK
DEMOD
IF
FILTER
FILTER
AMPL
RX_IN
SERIAL
INTERFACE
REG/DATA
BU/THERM
AGC
DIGITAL
FILTER
PLL
CLR/T
TEST1 TEST2
FILTER
CONTROL
REGISTER
RxTx
FSK
MODULATOR
TxD
TX
FILTER
DAC
ALC
CURRENT
CONTROL
CL
VOLTAGE
CONTROL
Vsense
TX_OUT
TIME BASE
OSC
VREG
VREG
+
-
PA
VCC
PA_OUT
VSS
X1
X2
WD
RSTO
MCLK
GND VDD
SVSS Vdc
PA_IN+
PA_IND03IN1407A
4/44
ST7540
Pin settings
2
Pin settings
2.1
Pin connection
Figure 2.
2.2
Pin connection (top view)
CD_PD
1
28
TEST2
REG_DATA
2
27
TEST1
GND
3
26
VDC
RxD
4
25
RX_IN
RxTx
5
24
CL
TxD
6
23
Vsense
BU/THERM
7
22
X2
CLR/T
8
21
X1_OSCIN
VDD
9
20
SVSS
MCLK
10
19
TX_OUT
RSTO
11
18
PA_IN+
UART/SPI
12
17
VCC
WD
13
16
VSS
PA_IN-
14
15
PA_OUT
Pin description
Table 1. Pin description
N°
Name
Type
1
CD_PD
2
REG_DATA
3
GND
Supply
Digital ground
4
RxD
Digital/Output
RX data output.
5
RxTx
Digital/Input
with internal pull-up
Rx or Tx mode selection input.
"1" - RX Session
"0" - TX Session
6
TxD
Digital/Input
TX data input.
with internal pull-down
Digital/Output
Description
Carrier, preamble or frame header detect output.
"1" No carrier, preamble or frame header detected
"0" Carrier, preamble or frame header detected
Mains or control register access selector
Digital/Input
"1" - Control register access
with internal pull-down
"0" - Mains access
5/44
Pin settings
ST7540
Table 1. Pin description (continued)
N°
7
Name
Type
BU/THERM Digital/Output
Band in use/Thermal Shutdown event detection output.
In Rx mode:
"1" Signal within the programmed band
"0" No signal within the programmed band
In Tx mode:
"1" - Thermal Shutdown event occurred
"0" - No Thermal Shutdown event occurred
(signal not latched)
8
CLR/T
Digital/Output
Synchronous mains access clock or
control register access clock
9
VDD
Supply/Power
Digital supply voltage or 3.3V voltage regulator output
10
MCLK
Digital/Output
Master clock output
11
RSTO
Digital/Output
Power ON or watchdog reset output
12
UART/SPI
13
WD
14
Interface type:
Digital/Input
“0” - Serial peripheral interface
with internal pull-down
“1” - UART interface
Digital/Input
with internal pull-up
Watchdog input. The internal watchdog counter is
cleared on the falling edges.
PA_IN-
Analog/Input
Power line amplifier inverting input
15
PA_OUT
Power/Output
Power line amplifier output
16
VSS
Supply
Power analog ground
17
VCC
Supply
Power supply voltage
18
PA_IN+
Analog/Input
Power line amplifier not inverting input
19
TX_OUT
Analog/Output
Small signal analog transmit output
20
SVSS
Supply
Analog signal ground
21
X1
Analog/Output
Crystal oscillator output
22
X2
Analog/Input
Crystal oscillator input - or external clock input
23
VSENSE (1)
Analog/Input
Output voltage sensing input for the voltage control loop
24
CL(2)
Analog/Input
Current limiting feedback.
A resistor between CL and SVSS sets the PLI current
limiting value. An integrated 80pF filtering input
capacitance is present on this pin.
25
RX_IN
Analog/Input
Receiving analog input
26
VDC
Power
5V voltage regulator output
27
TEST1
Digital/Input
Test input. Must be connected to GND.
with internal pull-down
28
TEST2
Analog/Input
1. Cannot be left floating
2. Cannot be left floating
6/44
Description
Test input. Must be connected SVSS
ST7540
Electrical data
3
Electrical data
3.1
Maximum ratings
Table 2. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
Power supply voltage
-0.3 to + 14
V
VDD
Digital supply voltage
-0.3 to +5.5
V
Voltage between SVSS and GND
-0.3 to +0.3
V
Digital input voltage
GND - 0.3 to VDD +0.3
V
VO
Digital output voltage
GND - 0.3 to VDD +0.3
V
IO
Digital output current
-2 to +2
mA
SVSS - 0.3 to 5.6
V
-5.6 to 5.6
V
SVSS - 0.3 to 5.6
V
VSS - 0.3 to +VCC +0.3
V
650
mArms
Operating ambient temperature
-40 to +85
°C
Storage temperature
-50 to 150
°C
±1750
V
±2000
V
HTSSOP28
Exposed Pad
Unit
SVSS/GND
VI
Vsense,
X2,PA_IN,PA_IN+, CL
RX_IN
Voltage range at Vsense, X2, PA_IN-, PA_IN+, CL
Inputs
Voltage range at RX_IN input
TX_OUT, X1
PA_OUT
I(PA_OUT)
TA
TSTG
RxD,
PA_OUT Pin
Other pins
Voltage range at TX_OUT, X1 outputs
Voltage range at powered PA_OUT Output
Power line driver output current (1)
Maximum withstanding voltage range
Test condition: CDF-AEC-Q100-002- “Human
Body Model”
Acceptance criteria: “Normal Performance”
1. This current is intended as not repetitive pulse current
3.2
Thermal data
Table 3. Thermal data
Symbol
1.
Parameter
RthJA1
Maximum thermal resistance junction-ambient steady
state (1)
35
° C/W
RthJA2
Maximum thermal resistance junction-ambient Steady
State (2)
70
° C/W
Mounted on Multilayer PCB with a dissipating surface on the bottom side of the PCB
2. It is the same condition of the point above, without any heatsinking surface on the board.
7/44
Electrical data
3.3
ST7540
Recommended operating conditions
Table 4. Recommended operating conditions
Symbol
Parameter
Value
Unit
100
V/ms
VCC
Max allowed slope during
Power-up
I(VCC)
Powered analog supply
Current with digital supply
provided externally
Maximum total current
650
mArms
Maximum voltage
Difference between VCC
VCC - VDD
and VDD during power-up
sequence
VDD < 4.75V with 5V
Digital supply provided
externally
1.2
V
VCC-4.5
VPP
500
mArms
VPA_OUT
Output voltage swing for
PA_OUT pin
Maximum output
transmitting current in
I(PA_OUT)
programmable current
limiting
8/44
Test Condition
Rcl = 1.4kΩ; RLOAD =1Ω
(as in Figure 17)
ST7540
4
Electrical characteristics
Electrical characteristics
Table 5. Electrical characteristics
( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40°C ≤TA ≤85°C, TJ < 125°C,
unless otherwise specified)
Symbol
Parameter
VDD
Digital supply voltages
VCC
Power supply voltage
I(VDD)
Digital input supply
current
I(VCC)
Power supply current
current with digital
supply provided
externally
UVLO
Under voltage lock out
Threshold on VCC
UVLOHYS
Test condition
Min.
Typ.
Max.
Unit
4.75
5
5.25
V
13.5
V
Transmission &
receiving mode
(MCLK = 4MHz),no load
3.5
mA
Transmission &
Receiving mode
(MCLK = OFF), no load
1.5
mA
TX mode, no load
60
mArms
RX mode
5
mArms
4.1
V
5V Digital supply
provided externally
7.5
3.7
UVLO Hysteresis on
VCC
3.9
340
mV
Digital I/O
Rdown
Rup
Internal pull down
resistor
-30%
100
+30%
kΩ
Internal pull up resistor
-30%
100
+30%
kΩ
Digital I/O - 5V digital supply
VIH
High logic level input
voltage
VIL
Low logic level input
voltage
VOH
High logic level output
voltage
IOH= -2mA
VOL
Low logic level output
voltage
IOL= 2mA
2
V
1.2
VDD 0.45
V
V
GND
+ 0.3
V
Digital I/O - 3.3V digital supply
VIH
High logic level input
voltage
VIL
Low logic level input
voltage
1.4
V
0.8
V
9/44
Electrical characteristics
ST7540
Table 5. Electrical characteristics (continued)
( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40°C ≤TA ≤85°C, TJ < 125°C,
unless otherwise specified)
Symbol
Parameter
Test condition
VOH
High logic level output
voltage
IOH= -2mA
VOL
Low logic level output
voltage
IOL= 2mA
Min.
Typ.
Max.
VDD 0.75
Unit
V
GND
+ 0.4
V
Oscillator
External Clock X2 voltage swing
External clock. Figure 4
5
Vpp
External Clock X2 DC voltage level
External clock. Figure 4
2.5
V
DC
XTAL Clock duty cycle
External clock.
Xtal
Crystal oscillator
frequency
fundamental
XtalESR
XtalCL
40
60
16
External oscillator esr
resistance
External oscillator
stabilization
capacitance
Figure 6
%
MHz
40
Ω
16
pF
1
mArms
Transmitter
ITX_OUT
Output transmitting
current on TX_OUT
VTX_OUT
Max carrier output AC
voltage
VTX_OUTDC
Output DC voltage on
TX_OUT
HD2TX_OUT
Second harmonic
distortion on TX_OUT
HD3TX_OUT
1.75
2.3
3.5
VPP
1.7
2.1
2.5
V
VTX_OUT = 2VPP;
Fc = 86KHz, no load
-42
dBc
Third harmonic
distortion on TX_OUT
VTX_OUT = 2VPP;
Fc = 86KHz, no load
-49
dBc
G accuracy
Accuracy on voltage
control loop active
RCL = 0Ω
+1
GST
GST
ALC gain step control
loop gain step
1.4
dB
DRNG
ALC dynamic range
30
dB
CCL
Input capacitance on
CL pin
80
pF
VsenseTH
VsenseHYST
10/44
RCL = 1.4kΩ
Vsense = 0V
0.6
Voltage control loop
reference threshold on Figure 17
Vsense pin
Hysteresis on voltage
loop reference
threshold
-1
Figure 17
160
1
180
±18
200
mVPK
mV
ST7540
Electrical characteristics
Table 5. Electrical characteristics (continued)
( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40°C ≤TA ≤85°C, TJ < 125°C,
unless otherwise specified)
Symbol
VSENSE
Parameter
Test condition
Min.
VSENSE Input
impedance
Typ.
Max.
36
Unit
kΩ
Current control loop
reference threshold on Figure 17
CL pin
1.80
1.90
2.00
V
Hysteresis on current
loop reference
threshold
210
250
290
mV
Figure 21 - 600
Baud Xtal = 16MHz
1.6
ms
Figure 21- 1200 Baud
Xtal = 16MHz
800
µs
Figure 21- 2400 Baud
Xtal = 16MHz
400
µs
Figure 21- 4800 Baud
Xtal = 16MHz
200
µs
TALC
Carrier stabilization
time
Figure 21
from STEP 16 to zero
Xtal = 16MHz
or from step 16 to step
31,
3.2
ms
TST
Tstep
Figure 21
Xtal = 16MHz
200
µs
CLTH
CLHYST
TRxTx
Figure 17
Carrier activation time
Power amplifier
PAIN(Offset)
Input terminals
OFFSET
GBWP
Gain bandwidth
product
RIN
CIN
CMRR
Input resistance at
PA_IN+ and PA_INpins
Input capacitance at
PA_IN+ and PA_INpins
Common mode
rejection ratio
±18
mV
100
MHz
PA_IN+ vs. Vss (1)
1
MΩ
PA_IN- vs. Vss (1)
1
MΩ
PA_IN+ vs. Vss (1)
5
pF
PA_IN- vs. Vss (1)
5
pF
40
dB
11/44
Electrical characteristics
ST7540
Table 5. Electrical characteristics (continued)
( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40°C ≤TA ≤85°C, TJ < 125°C,
unless otherwise specified)
Symbol
HD2PA_OUT
HD3PA_OUT
Parameter
Test condition
Min.
Typ.
Max.
Unit
Second harmonic
distortion on PA_OUT
VPA_OUT = 5.6VPP ,
VCC = 12V
RLOAD = 30Ω
Carrier frequency:
86KHz
Figure 3
-63
dBc
Third harmonic
distortion on PA_OUT
pin
VPA_OUT = 5.6VPP ,
VCC = 12V
RLOAD = 30Ω
Carrier frequency:
86KHz
Figure 3
- 63
dBc
2
mVrms
Receiver
VIN
0.5
Input sensitivity
(High Sens.)
250
µVrms
Input sensitivity (TxD
line forced to “1”)
VBU
dB/
µVrms
VIN
Maximum input signal
RIN
Input impedance
VCD
VBU
12/44
Input sensitivity
(Normal Mode)
2
Vrms
100
140
kΩ
Carrier detection
sensitivity
(Normal Mode)
0.5
2
mVrms
Carrier detection
sensitivity
(High Sensitivity Mode)
250
µVrms
Carrier detection
sensitivity
(TxD forced to “1”)
VBU
dB/
µVrms
Band in Use Detection
Level
83.5
80
86
dB/
µVrms
ST7540
Electrical characteristics
Table 5. Electrical characteristics (continued)
( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40°C ≤TA ≤85°C, TJ < 125°C,
unless otherwise specified)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Linear regulator output 0 < Io < 50mA
7.5V < VCC < 13.5V
voltage
-5%
5.05
+5%
V
-5%
3.3
+5%
V
5V Voltage regulator
VDC
3.3V Voltage regulator
VDD
Linear regulator output 0 < Io < 50mA
7.5V < VCC < 13.5V
voltage
Other functions
See Figure 23;
Xtal = 16MHz
50
ms
TWD
Watch-dog pulse width See Figure 23
125
ns
250
ns
TWM
Watch-dog pulse
period
TRSTO
Reset time
Minimum value.
See Figure 23
Maximum value.
See Figure 23
TWO
Watch-dog time out
See Figure 23
TOUT
TX time out
Control register bit 7
and bit 8
TOFF
Time Out OFF time
Figure 22
TOFFD
RxTx 0->1 vs. time out
Figure 22
delay
1490
ms
1.5
s
1
3
s
125
ms
20
µs
µs
ms
ms
ms
TCD
Carrier detection time
selectable by register
Control register
bit 9 and bit10
Figure 14
500
1
3
5
TDCD
CD_PD Propagation
delay
Figure 14
300
MCLK
Master clock output
selectable by register
Control register
bit 15 and bit 16
See Table 12
fclock
fclock/2
fclock/4
off
MHz
Baud rate
Control register
bit 3 and bit 4
See Table 12
600
1200
2400
4800
Baud
BAUD
500
µs
13/44
Electrical characteristics
ST7540
Table 5. Electrical characteristics (continued)
( VDD = +5V, VCC =+9 V, VSS = SVSS = GND = 0V,-40°C ≤TA ≤85°C, TJ < 125°C,
unless otherwise specified)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Serial Interface
1667
833
417
208
TB
Baud rate Bit Time
(1/BAUD)
Control register bit 3
and bit 4
(See Figure 13)
Ts
Setup time
see Figures 8, 9, 10, 11
& 12
5
ns
TH
Hold time
see Figures 8, 9, 10, 11
& 12
2
ns
TCR
CLR/T vs. REG_DATA
or RxTx
see Figures 8, 9, 10, 11
& 12
TB/4
TCC
CLR/T vs. CLR/T
see Figures 8, 9, 10, 11
& 12
TB
2*TB
TDS
Setup time
see Figures 8, 9, 10, 11
& 12
TB/4
TB/2
TDH
Hold time
see Figures 8, 9, 10, 11
& 12
TB/4
TB/2
TH
TB/2
TCRP
µs
1. Not tested, guaranteed by design
Figure 3.
PLI configuration for PA_OUT distortions measurement
150 pF
100 pF
2.7 kΩ
5 kΩ
Vcc
PA_IN PA_OUT
PA
10 kΩ
VAC= 2Vpp
VDC= 1.9 V
1uF
PA_IN +
30 Ω
Vss
D03IN1426
Measurement point
14/44
ST7540
Crystal resonator and external clock
External clock waveform
X2
SVss
Figure 5.
External ClockOFFSET
Figure 4.
External ClockSWING
5
Crystal resonator and external clock
Crystal Resonator
X1
32 pF
X2
32 pF
D03IN1425A
15/44
Functional description
ST7540
6
Functional description
6.1
Carrier frequencies
ST7540 is a multi frequency device: eight programmable Carrier Frequencies are available
(see Table 6).
Only one Carrier can be used a time. The communication channel could be varied during
the normal working Mode to realize a multi frequency communication.
Selecting the desired frequency in the Control Register the Transmission and Reception
filters are accordingly tuned.
Table 6. Channels List
FCarrier
F (KHz)
F0
60
F1
66
F2
72
F3
76
F4
82.05
F5
86
F6
110
F7 (1)
132.5
1. Default value
6.2
Baud rates
ST7540 is a multi Baud rate device: four Baud Rate are available (See Table 8).
Table 7. ST7540 mark and space tones frequency distance Vs. baud rate and deviation
Baud Rate [Baud]
∆F (1)(Hz)
Deviation (2)
600
600
1 (3)
1200
600
1200
0.5
1
2400 (4)
1200 (4)
2400
0.5
1
4800
2400
4800
0.5
1
1. Frequency deviation
2. Deviation = ∆F / (Baud Rate)
3. Deviation 0.5 not allowed
4. Default value
16/44
ST7540
6.3
Functional description
Mark and space frequencies
Mark and Space Communication Frequencies are defined by the following formula:
F ("0") = FCarrier + [∆F]/2
F ("1") = FCarrier - [∆F]/2
∆F is the Frequency Deviation.
With Deviation = “0.5” the difference in terms of frequency between the mark and space
tones is half the Baudrate value (∆F=0.5*BAudrate). When the Deviation = “1” the difference
is the Baudrate itself (∆F= Baudrate). The minimal Frequency Deviation is 600Hz.
Table 8. ST7540 synthesized frequencies
Carrier
frequency
(KHz)
Baud
rate
Deviation
Exact frequency
[Hz]
(Clock=16MHz)
“1”
Carrier
frequency
(KHz)
Baud
rate
Deviation
“0”
Exact frequency
[Hz]
(Clock=16MHz)
“1”
“0”
1
81706
82357
0.5
81706
82357
1
81380
82682
0.5
81380
82682
1
80892
83171
0.5
80892
83171
1
79590
84473
1
85775
86263
0.5
85775
86263
1
85449
86589
0.5
85449
86589
1
84798
87240
0.5
84798
87240
1
83659
88379
1
109701
110352
0.5
109701
110352
1
109375
110677
0.5
109375
110677
1
108724
111165
0.5
108724
111165
1
107585
112467
--
-600
600
1
59733
60221
0.5
59733
60221
1200
1200
1
59408
60547
82.05
60
0.5
59408
60547
2400
2400
1
58757
61198
0.5
58757
61198
4800
4800
1
57617
62337
--
-600
600
1
65755
66243
0.5
65755
66243
1200
1200
1
65430
66569
86
66
0.5
65430
66569
2400
2400
1
64779
67220
0.5
64779
67220
4800
4800
1
63639
68359
--
--
600
600
1
71777
72266
0.5
71777
72266
1200
1200
1
71452
72591
72
110
0.5
71452
72591
2400
2400
1
70801
73242
0.5
70801
73242
4800
4800
1
69661
74382
17/44
Functional description
ST7540
Table 8. ST7540 synthesized frequencies
--
-600
600
1
75684
76335
0.5
75684
76335
1200
132161
132813
0.5
132161
132813
1
131836
133138
0.5
131836
133138
1
131348
133626
0.5
131348
133626
1
130046
134928
1200
1
75358
76660
132.5
76
0.5
75358
76660
2400
2400
1
74870
77148
0.5
74870
77148
4800
4800
1
6.4
1
73568
78451
ST7540 Mains access
ST7540 can access the Mains in two different ways:
●
Synchronous access
●
Asynchronous access
The choice between the two types of access can be performed by means of Control
Register bit 14(see Table 12) and affects the ST7540 data flow in Transmission Mode as in
Reception Mode (for how to set the communication Mode, see Section 6.5).
In data transmission mode:
●
Synchronous Mains access: on clock signal provided by ST7540 (CLR/T line) rising
edge, data transmission line (TxD line) value is read and sent to the FSK Modulator.
ST7540 manages the Transmission timing according to the BaudRate Selected.
●
Asynchronous Mains access: data transmission line (TxD line) value enters directly to
the FSK Modulator. The Host Controller manages the Transmission timing (CLR/T line
should be neglected).
In data reception mode:
18/44
●
Synchronous Mains access: on clock signal recovered by a PLL from ST7540 (CLR/T
line) rising edge, value on FSK Demodulator is read and put to the data reception line
(RxD line). ST7540 recovers the bit timing timing according to the BaudRate Selected.
●
Asynchronous Mains access: Value on FSK Demodulator is sent directly to the data
reception line (RxD line). The Host Controller recovers the communication timing
(CLR/T line should be neglected).
ST7540
6.5
Functional description
Host processor interface
ST7540 exchanges data with the host processor through a serial interface.
The data transfer is managed by REG_DATA and RxTx Lines, while data are exchanged
using RxD, TxD and CLR/T lines.
Four are the ST7540 working modes:
●
Data Reception
●
Data Transmission
●
Control Register Read
●
Control Register Write
REG_DATA and RxTx lines are level sensitive inputs.
Table 9. Data and Control register access bits configuration
REG_DATA
RxTx
Data Transmission
0
0
Data Reception
0
1
Control Register Read
1
1
Control Register Write
1
0
ST7540 features two type of Host Communication Interfaces:
●
SPI
●
UART
The selection can be done through the UART/SPI pin. If UART/SPI pin is forced to “0” SPI
interface is selected while if UART/SPI pin is forced to “1” UART interface is selected. The
type of interface affects the Data Reception by setting the idle state of RxD line. When
ST7540 is in Receiving mode (REG_DATA=”0” and RxTx =“1”) and no data are available on
mains (or RxD is forced to an idle state, i.e. with a conditioned Detection Method), the RxD
line is forced to “0” when UART/SPI pin is forced to ”0” or it is forced to “1” when UART/SPI
pin is forced to ”1”.
The UART interface allows to connect an UART compatible device while SPI interface
allows to connect an SPI compatible device. The allowed combinations of Host
Interface/ST7540 Mains Access are:
Table 10. Host interface / ST7540 mains access combinations
Host device
interface type
UART/SPI pin
Communication
mode
Mains access
Asynchronous
Synchronous
UART
“1”
Transmission
X
UART
“1”
Reception
X
SPI
“0”
Transmission
X
SPI
“0”
Reception
X
19/44
Functional description
Figure 6.
ST7540
Synchronous and Asynchronous ST7540/Host Controller interfaces
UART/Asynchronous
Data Interface
Host Controller
SPI/Synchronous
Data Interface
RxD
RxD
TxD
TxD
RxTx
RxTx
CLR/T
CLR/T
REG_DATA
REG_DATA
ST7540
Host Controller
ST7540
D03IN1415
ST7540 allows to interface the Host Controller using a five line interface (RxD,TxD,RxTx,
CLR/T, & REG_DATA) in case of Synchronous mains access or using a 3 line interface
(RxD,TxD & RxTx) in Asynchronous mains access. Since Control Register is not accessible
in Asynchronous mode, in this case REG_DATA pin must be tied to GND.
6.5.1
Communication between Host and ST7540
The Host can achieve the Mains access by selecting REG_DATA=”0” and the choice
between Data Transmission or Data Reception is performed by selecting RxTx line (if RxTx
=“1” ST7540 receives data from mains, if RxTx=”0” ST7540 transmits data over the mains).
Communication between Host and ST7540 is different in Asynchronous and Synchronous
mode:
●
Asynchronous mode:
In Asynchronous Mode, data are exchanged without any data Clock reference. The
host controller has to recover the clock reference in receiving Mode and control the Bit
time in transmission mode.
If RxTx line is set to “1” & REG_DATA=”0” (Data Reception), ST7540 enters in an Idle
State. After Tcc time the modem starts providing received data on RxD line.
If RxTx line is set to “0” & REG_DATA=”0” (Data Transmission), ST7540 enters in an
Idle State and transmission circuitry is switched on. After Tcc time the modem starts
transmitting data present on TxD line.
20/44
ST7540
Functional description
●
Synchronous mode:
In Synchronous Mode ST7540 is always the master of the communication and provides
the clock reference on CLR/T line. When ST7540 is in receiving mode an internal PLL
recovers the clock reference. Data on RxD line are stable on CLR/T rising Edge.
When ST7540 is in transmitting mode the clock reference is internally generated and
TxD line is sampled on CLR/T rising Edge.
If RxTx line is set to “1” & REG_DATA=”0” (Data Reception), ST7540 enters in an Idle
State and CLR/T line is forced Low. After Tcc time the modem starts providing received
data on RxD line.
If RxTx line is set to “0” & REG_DATA=”0” (Data Transmission), ST7540 enters in an
Idle State and transmission circuitry is switched on. After Tcc time the modem starts
transmitting data present on TxD line (Figure 8) .
Figure 7.
Receiving and transmitting data/recovered clock timing
Receiving Bit Synchronization
Transmitting Bit Synchronization
CLR/T
CLR/T
RxD
TxD
D03IN1416
TS TH
Figure 8.
Data reception -> data transmission -> data reception
TCC
TCC
CLR_T
TDS
TB
TDH
RxD
REG_DATA
TCR
TCR
RxTx
TSTH
TxD
D03IN1402
21/44
Functional description
6.5.2
ST7540
Control register access
The communication with ST7540 Control Register is always synchronous. The access is
achieved using the same lines of the Mains interface (RxD, TxD, RxTx and CLR/T) plus
REG_DATA Line.
With REG_DATA = 1 and RxTx = 0, the data present on TxD are loaded into the Control
Register MSB first. The ST7540 samples the TxD line on CLR/T rising edges. The control
Register content is updated at the end of the register access section (REG_DATA falling
edge).
In Normal Control Register mode (Control Register bit 21 = ”0”, see Table 12) if more than
24 bits are transferred to ST7540 only latest 24 bits are stored inside the Control Register. If
less than 24 bits are transferred to ST7540 the Control Register writing is aborted.
In order to avoid undesired Control Register writings caused by REG_DATA line fluctuations
(for example because of surge or burst on mains), in Extended Control Register mode
(Control Register bit 21 = ”1” see Table 12) exactly 24 or 48 bits must be transferred to
ST7540 in order to properly write the Control Register, otherwise writing is aborted. If 24 bits
are transferred, only the first 24 Control Register bits (from 23 to 0) are written.
With REG_DATA = 1 and RxTx = 1, the content of the Control Register is sent on RxD port.
The Data on RxD are stable on CLR/T rising edges MSB First. In Normal Control Register
mode 24 bits are transferred from ST7540 to the Host. In Extended Control Register mode
24 or 48 bits are transferred from ST7540 to the Host depending on content of Control
Register bit 18 (with bit 18 = ”0” the first 24 bits are transferred, otherwise all 48 bits are
transferred, see Table 12).
Figure 9.
Data reception ➨ control register read ➨ data reception timing diagram
TCC
TCC
CLR_T
TDS
TDH
TDS
RxD
TDH
BIT23
TB
BIT22
TCR
REG_DATA
TCR
RxTx
D03IN1404
Figure 10. data reception ➨ control register write ➨ data reception timing diagram
TCC
TCC
CLR_T
TDS
TB
TDH
RxD
TCR
TCR
REG_DATA
TCR
TCR
RxTx
TSTH
TxD
BIT23
BIT22
D03IN1403
22/44
ST7540
Functional description
Figure 11. Data transmission ➨ control register read ➨ data reception timing diagram
TCC
TCC
CLR_T
TB
TDS
RxD
BIT23
TDH
TDH
BIT22
TCR
REG_DATA
TDS
TCR
TCR
RxTx
TSTH
TxD
D03IN1405
Figure 12. Data transmission ➨ control register write ➨ data reception timing diagram
TCC
TCC
CLR_T
TB
TSTH
TxD
BIT23
BIT22
TCR
TSTH
REG_DATA
TCR
TCR
RxTx
TDS
TDH
RxD
D03IN1401
6.6
Receiving mode
The receive section is active when RxTx Pin =”1” and REG_DATA=0.
The input signal is read on RX_IN Pin using SVSS as ground reference and then pre-filtered
by a Band pass Filter (62kHz max bandwidth at -3dB). The Pre-Filter can be inserted setting
one bit in the Control Register. The Input Stage features a wide dynamic range to receive
Signal with a Very Low Signal to Noise Ratio. The Amplitude of the applied waveform is
automatically adapted by an Automatic Gain Control block (AGC) and then filtered by a
Narrow Band Band-Pass Filter centered around the Selected Channel Frequency (14kHz
max at -3dB). The resulting signal is down-converted by a mixer using a sinewave generated
by the FSK Modulator. Finally an Intermediate Frequency Band Pass-Filter (IF Filter)
improves the Signal to Noise ration before sending the signal to the FSK demodulator. The
FSK demodulator then send the signal to the RX Logic for final digital filtering. Digital
filtering Removes Noise spikes far from the BAUD rate frequency and Reduces the Signal
Jitter. RxD Line is forced to “0” or “1” (according the UART/SPI pin level) when neither mark
or space frequencies are detected on RX_IN Pin.
Mark and Space Frequency in Receiving Mode must be distant at least BaudRate/2 to have
a correct demodulation.
While ST7540 is in Receiving Mode (RxTx pin =”1”), the transmit circuitry, Power Line
Interface included, is turned off. This allows the device to achieve a very low current
consumption (5mA typ).
23/44
Functional description
ST7540
●
Receiving Sensitivity Level Selection
It is possible to select the ST7540 Receiving Sensitivity Level by Control Register (see
Table 12) or setting to ‘1’ the TxD pin during reception phase (this condition overcomes
the control register setting the sensitivity equal to BU threshold). Increasing the device
sensitivity allows to improve the communication reliability when the ST7540 sensitivity
is the limiting factor.
●
Synchronization Recovery System (PLL)
ST7540 embeds a Clock Recovery System to feature a Synchronous data exchange
with the Host Controller. The clock recovery system is realized by means of a second
order PLL. In Synchronous mode, data on the data line (RxD) are stable on CLR/T line
rising edge (CLR/T Falling edge synchronized to RxD line transitions ± LOCK-IN
Range). The PLL Lock-in and Lock-out Range is ±π/2. When the PLL is in the unlock
condition RxD line is forced to “0” or “1” according to the UART/SPI pin level and CLR/T
is forced to “0” only if the Detection Method “Preamble Detection With Conditioning” is
selected.When PLL is in unlock condition it is sensitive to RxD Rising and Falling
Edges. The maximum number of transition required to reach the lock-in condition is 5.
When in lock-in condition the PLL is sensitive only to RxD rising Edges to reduce the
CLR/T Jitter. ST7540 PLL is forced in the un-lock condition, when more than 32 equal
symbols are received.Due to the fact that the PLL, in lock-in condition, is sensitive only
to RxD rising edge, sequences equal or longer than 15 equal symbols can put the PLL
into the un-lock condition.
Figure 13. ST7540 PLL lock-in range
CLR/T
RxD
D03IN1417
LOCK-IN RANGE
●
24/44
Carrier/Preamble Detection
The Carrier/Preamble Block is a digital Frequency detector Circuit.
It can be used to manage the MAINS access and to detect an incoming signal.
Two are the possible setting:
–
Carrier Detection
–
Preamble Detection
ST7540
Functional description
●
Carrier Detection
The Carrier/Preamble detection Block notifies to the host controller the presence of a
Carrier when it detects on the RX_IN Input a signal with an harmonic component close
to the programmed Carrier Frequency. The CD_PD signal sensitivity is identical to the
data reception sensitivity (0.5mVrms Typ. in Normal Sensitivity Mode). When the
device sensitivity is set by the TxD line (Sensitivity level equal to BU threshold) the
CD_PD signal is conditioned to the BU signal.
The CD_PD line is forced to a logic level low when a Carrier is detected.
●
Preamble Detection
The Carrier/Preamble detection Block notifies to the host controller the presence of a
Carrier modulated at the Programmed Baud Rate for at least 4 Consecutive Symbols
(“1010” or “0101” are the symbols sequences detected).
CD_PD line is forced low till a Carrier signal is detected and PLL is in the lock-in range.
To reinforce the effectiveness of the information given by CD_PD Block, a digital
filtering is applied on Carrier or Preamble notification signal (see Section 6.8: Control
register). The Detection Time Bits in the Control Register define the filter performance.
Increasing the Detection Time reduced the false notifications caused by noise on main
line. The Digital filter adds a delay to CD_PD notification equal to the programmed
Detection Time. When the carrier frequency disappears, CD_PD line is held low for a
period equal to the detection time and then forced high. During this time, some
spurious data caused by noise can be demodulated and sent over RxD line.
●
Header Recognition
In Control Register Extended Mode (Control Register bit 21=”1”, see Table 12) the
CD_PD line can be used to recognize if an header has been sent during the
transmission. With Header Recognition function enable (Control Register bit 18=”1”,
see Table 12), CD_PD line is forced low when a Frame Header is detected. If Frame
Length Count function is enabled, CD_PD is held low and a number of 16 bit word
equal to the Frame Length selected is sent to the host controller. In this case, CLR/T is
forced to “0” and RxD is forced to “0” or “1” (according the UART/SPI pin level) when
Header has not been detected or after the Frame Length has been reached.
If Frame Length Count function is disabled, an header recognition is signaled by forcing
CD_PD low for one period of CLR/T line. In this case, CLR/T and RxD signal are
always present, even if no header has been recognized.
25/44
Functional description
ST7540
Figure 14. CD_PD Timing during RX
TDCD
TCD
TDCD
TCD
CD_PD
RX_IN
demodulation active on RxD pin
noise demodulated
RxD (UART/SPI="1")
noise demodulated
RxD (UART/SPI="0")
D03IN1418
Figure 15. Receiving path block diagram
Bits 3-4
RxD
MIXER
4
CLR/T
PLL
Bits 18-21 &
24-47
CD_PD
1
Low Pass
DIGITAL
FILTER
Bits 9-10
HEADER
RECOGN.
Low Pass
BU/THERM
25
AGC
Bits 3-4 &14
8
Bit 23
Bits 0-2
Bits 3-4 & 22
Band Pass
FSK
DEMODULATOR
Bits 12-13 & 22
CARRIER/
PREAMBLE
DETECTION
IF FILTER
LOCAL
OSC
CHANNEL
FILTER
RX_IN
Band Pass
Band Pass
PRE-FILTER
GAIN
CONTROL
Bits 0 -2
Carrier Detection
7
BAND
IN
USE
D03IN1419
6.7
Transmission mode
The transmission mode is set when RxTx Pin =”0” and REG_DATA Pin =”0”. In transmitting
mode the FSK Modulator and the Power Line Interface are turned ON. The transmit Data
(TxD) enter synchronously or asynchronously to the FSK modulator.
●
Synchronous Mains access: on CLR/T rising edge, TxD Line Value is read and sent to
the FSK Modulator. ST7540 manages the Transmission timing according to the
BaudRate Selected
●
Asynchronous Mains access: TxD data enter directly to the FSK Modulator.The Host
Controller manages the Transmission timing
In both conditions no Protocol Bits are added by ST7540.
The FSK frequencies are synthesized in the FSK modulator from a 16 MHz crystal oscillator
by direct digital synthesis technique. The frequencies Table in different Configuration is
reported in Table 8. The frequencies precision is same as external crystal one’s.
26/44
ST7540
Functional description
In the analog domain, the signal is filtered in order to reduce the output signal spectrum and
to reduce the harmonic distortion. The transition between a symbol and the following is done
at the end of the on-going half FSK sinewave cycle.
Figure 16. Transmitting path block diagram
Bits 7-8
BU/THERM
7
THERMAL
SENSOR
Bit 14
TxD
Bits 17 & 21
VOLTAGE
LOOP
23
CURRENT
LOOP
24
Vsense
TIMER
Bits 0-2
Bits 0-5
+
6
DAC
ALC
-
PA
15
CL
PA_OUT
Band Pass
D-TYPE
FLIP
FLOP
CLR/T
FSK
MODULATOR
TRANSMISSION
FILTER
14
18
8
19
PA_INPA_IN+
TX_OUT
CLR/T GENERATOR
D03IN1420
●
Automatic Level Control (ALC)
The Automatic Level Control Block (ALC) is a variable gain amplifier (with 32 non linear
discrete steps) controlled by two analog feed backs acting at the same time. The ALC
gain range is 0dB to 30 dB and the gain change is clocked at 5KHz. Each step
increases or reduces the voltage of 1dB (Typ).
Two are the control loops acting to define the ALC gain:
–
A Voltage Control loop
–
A Current Control Loop
The Voltage control loop acts to keep the Peak-to-Peak Voltage constant on Vsense.
The gain adjustment is related to the result of a peak detection between the Voltage
waveform on Vsense and two internal Voltage references. It is possible to protect the
Voltage Control Loop against noise by freezing the output level (see Section 7.5:
Output voltage level freeze).
–
If Vsense < VsenseTH - VsenseHYST
–
If VsenseTH - VsenseHYST < Vsense < VsenseTH + VsenseHYST No Gain Change
–
If Vsense > VsenseTH + VsenseHYST
The next gain level is increased by 1 step
The next gain level is decreased by 1 step
27/44
Functional description
ST7540
The Current control loop acts to limit the maximum Peak Output current inside
PA_OUT.
The current control loop acts through the voltage control loop decreasing the Output
Peak-to-Peak Amplitude to reduce the Current inside the Power Line Interface.
The current sensing is done by mirroring the current in the High side MOS of the Power
Amplifier (not dissipating current Sensing). The Output Current Limit (up to 500mrms),
is set by means of an external resistor (RCL) connected between CL and VSS. The
resistor converts the current sensed into a voltage signal. The Peak current sensing
block works as the Output Voltage sensing Block:
–
If V(CL) < CLTH - CLHYSTVoltage Control Loop Acting
–
If CLTH - CLHYST < V(CL) < CLTH + CLHYSTNo Gain Change
–
If V(CL) > CLTH + CLHYSTThe next gain level is decreased by 1 step
Figure 17 shows the typical connection of Current anVoltage control loops.
Figure 17. Voltage and current feedback external interconnection example
PA_OUT/TX_OUT
ALC
Vout
VoutPK
R1
VOLTAGE
LOOP
Vsense
10nF
R2
VsenseHYST
VsenseTH
CURRENT
LOOP
80pF typ.
RCL
AVss
D03IN1421
Voltage Control Loop Formula
R1 + R2
V OUTPK ≅ -------------------- ⋅ ( Vsense TH ± Vsense HYST )
R2
28/44
1.865V (Typ)
CL
VCLHYST
VCLTH
ST7540
Functional description
Table 11. VOUT Vs. R1 & R2 resistors value
Note:
Vout (Vrms)
Vout (dBµV)
(R1+R2)/R2
R2 (KΩ)
R1 (KΩ)
0.150
103.5
1.1
7.5
1.0
0.250
108.0
1.9
5.1
3.9
0.350
110.9
2.7
3.6
5.6
0.500
114.0
3.7
3.3
8.2
0.625
115.9
4.7
3.3
11.0
0.750
117.5
5.8
2.7
12.0
0.875
118.8
6.6
2.0
11.0
1.000
120.0
7.6
1.6
10.0
1.250
121.9
9.5
1.6
13.0
1.500
123.5
10.8
1.6
15.0
Notes: The rate of R2 takes in account the input resistance on the VSENSE pin (36KΩ). 10nF
capacitor effect has been neglected.
Figure 18. Typical output current vs RCL
Irms
(mA)
D01IN1311
1220
1120
1020
920
820
720
620
520
420
320
220
120
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1
●
Rcl(kΩ)
Integrated Power Line Interface (PLI)
The Power Amplifier (PA) is a CMOS AB Class Power Amplifier. The PA requires, to
ensure a proper
operation, a regulated and well filtered Supply Voltage. Vcc Voltage and PA_OUT
Voltage must fulfil
the following formulas to work without clipping phenomena:
( AC )- + VPOUT ( DC ) + 3V
V CC ≥ VPAOUT
--------------------------------------2
VPAOUT ( AC )
VPOUT ( DC ) – ---------------------------------------- ≥ 1.5V
2
29/44
Functional description
ST7540
Figure 19. PA_OUT and VCC relationship
V
Vcc
≤ 3V
VPA_OUT(AC)
≤ 1.5V
VPA_OUT(DC)
Vss
t
D03IN1425
Inputs and outputs of PA are available on pins PA_IN-,PA_IN+ and PA_OUT. User can easily
select an appropriate active filtering topology to filter the signal present on TX_OUT pin.
TX_OUT output has a current capability much lower than PA_OUT.
30/44
ST7540
Functional description
Figure 20. Power line interface topology
Vcc
Z2
PA_IN-
-
Z1
PA_OUT
+
PA_IN+
AC LINE
R3
TX_OUT
ALC
R4
Vss
R1
VOLTAGE
LOOP
Vsense
CURRENT
LOOP
CL
R2
RCL
80pF typ.
D03IN1422
Figure 21. Power line interface startup timing diagram
RxTx
TALC
TRXTX
TST
2.1V
TX_OUT
0V
STEP NUMBER 16
17
18
31
D03IN1408
31/44
Functional description
6.8
ST7540
Control register
The ST7540 is a multi-channel and multifunction transceiver. An internal 24 or 48 Bits (in
Extended mode) Control Register allows to manage all the programmable parameters
(Table 12).
The programmable functions are:
●
Channel Frequency
●
Baud Rate
●
Deviation
●
Watchdog
●
Transmission Timeout
●
Frequency Detection Time
●
Detection Method
●
Mains Interfacing Mode
●
Output Clock
●
Sensitivity Mode
●
Input Pre-Filter
In addition to these functions the Extended mode provides 24 additional bits and others
functions:
32/44
●
Output Level Freeze
●
Frame Header Recognizes (one 16 bits header of or two 8 bits headers) with support to
Frame Length Bit count
ST7540
Functional description
Table 12. Control register functions
Function
0 to 2
3 to 4
Frequencies
Baud rate
Value
60 KHz
66 KHz
72 KHz
76 KHz
82.05 KHz
86 KHz
110 KHz
132.5 KHz
600
1,200
2,400
4,800
Selection
Note
Bit2
Bit1
Bit0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bit 4
Bit 3
0
0
1
1
0
1
0
1
Default
132.5 kHz
2400
Bit 5
5
Deviation
0.5
1
0
1
0.5
Bit 6
6
7 to 8
9 to 10
11
Watchdog
Transmission
time out
Frequency
detection time
Reserved
Disabled
Enabled (1.5 s)
Disabled
1s
3s
Not Used
500 µs
1 ms
3 ms
5 ms
0
1
Enabled
Bit 8
Bit 7
0
0
1
1
0
1
0
1
Bit 10
Bit 9
0
0
1
1
0
1
0
1
1 sec
1 ms
Do not force a different value
0
33/44
Functional description
ST7540
Table 12. Control register functions
Function
Value
Selection
Bit 13
Preamble detection
without conditioning
Preamble detection
with conditioning
12 to 13
Carrier detection
with conditioning
Default
Bit 12
0
0
0
Preamble detection
notification on CD_PD Line
CLR/T and RxD signal always
present In UART Mode
(UART/SPI pin set to 1) this
configuration is not allowed.
1
Preamble Detection
notification on CD_PD Line.
CLR/T and RxD line are
forced to "0" when Preamble
has not been detected or PLL
is in Unlock condition. In
UART Mode (UART/SPI pin
set to 1) this configuration is
not allowed.
Detection
method
Carrier detection
without conditioning
Note
1
1
0
Carrier detection notification
on CD_PD Line
CLR/T and RxD signal always
present
1
Carrier detection notification
on CD_PD Line
CLR/T Line is forced to “0”
and RxD Line is forced to “0”
or “1” (according the
UART/SPI pin level) when
carrier is not detected
Carrier
detection
without
conditioning
Bit 14
14
15 to 16
Mains
Interfacing
Mode
Output Clock
Synchronous
Asynchronous
16 MHz
8 MHz
4 MHz
Clock OFF
0
1
Asynchronous
Bit 16
Bit 15
0
0
1
1
0
1
0
1
4 MHz
Bit 17
17
Output
Voltage Level
Freeze
Enabled
Disabled
0
1
Active only if extended control
register is enable (Bit 21=”1”)
Disabled
Bit 18
18
Header
Recognition
Disabled
Enabled
0
1
Bit 19
19
34/44
Frame Length
Count
Disabled
Enabled
0
1
Active only if extended control
register is enable (Bit 21=”1”)
Active only if header
recognition function (Bit
18=”1”) and extended control
register (Bit 21=”1”)
are enable
Disabled
Disabled
ST7540
Functional description
Table 12. Control register functions
Function
Value
Selection
Note
Default
Active only if Extended
Control Register is enable (Bit
21=”1”)
16 bits
Extended Register enables
Functions on Bit 17, 18,19 and
20
Disabled
(24 bits)
Bit 20
20
Header
Length
8 bits
16 bits
0
1
Bit 21
21
Extended
Register
Disable (24 bits)
Enabled (48 bits)
0
1
Bit 22
22
Sensitivity
Mode
Normal Sensitivity
High Sensitivity
0
1
Normal
Bit 23
23
Input Filter
Disabled
Enabled
24 to 39
Frame
Header
from 0000h to
FFFFh
40 to 47 Frame Length
from 01h to FFh
0
1
Disabled
One 16 bits Header or two 8
bits Headers (MSB first)
depending on Bit 20
Number of 16 bits words
expected
9B58h
08h
35/44
Auxiliary analog and digital functions
ST7540
7
Auxiliary analog and digital functions
7.1
Band in use
The Band in Use Block has a Carrier Detection like function but with a different Input
Sensitivity (83.5 dBµV Typ.) and with a different BandPass filter Selectivity (40dB/Dec).
BU/THERM line is forced High when a signal in band is detected.
To prevent BU/THERM line false transition, Band in Use signal is conditioned to Carrier
Detection Internal Signal. This function is enabled only in Receiving mode (in Transmission
mode the BU/THERM pin is used for Thermal shutdown signaling, see Section 7.8: Thermal
shutdown).
7.2
Time out
Time Out Function is a protection against a too long data transmission. When Time Out
function is enabled after 1 or 3 second of continuos transmission the transceiver is forced in
receiving mode. This function allows ST7540 to automatically manage the CENELEC
Medium Access specification. When a time-out event occur, the transmission section is
disabled for at least 125 ms. To Unlock the Time Out condition RxTx should be forced High.
During the time out period only register access or reception mode are enabled.
During Reset sequence if RxTx line =”0” & REG_DATA line =”0”, Time Out protection is
suddenly enabled and ST7540 must be configured in data reception after the reset event
before starting a new data transmission.
Time Out time is programmable using Control Register bits 7 and 8 (Table 12).
Figure 22. Time-out timing and unlock sequence
RxTx
TOUT
TOFF TOFFD
Time Out function
D03IN1409
36/44
ST7540
7.3
Auxiliary analog and digital functions
Reset & watchdog
RSTO Output is a reset generator for the application circuitry. During the ST7540 startup
sequence is forced low. RSTO becomes high after a TRSTO delay from the end of oscillator
startup sequence.
Inside ST7540 is also embedded a watchdog function. The watchdog function is used to
detect the occurrence of a software fault of the Host Controller. The watchdog circuitry
generates an internal and external reset (RSTO low for TRSTO time) on expiry of the internal
watchdog timer. The watchdog timer reset can be achieved applying a negative pulse on
WD pin (see Figure 23).
Figure 23. Reset and Watchdog Timing
TRSTO
TWO
RSTO
TRSTO
TWM
TWD
WD
D03IN1410
7.4
Output clock
MCLK is the master clock output. The clock frequency sourced can be programmed through
the Control Register to be a ratio of the crystal oscillator frequency (Fosc, Fosc/2 Fosc/4).
The transition between one frequency and another is done only at the end of the ongoing
cycle. The oscillator can be disabled using Control Register bits 15 and 16 (Table 12).
7.5
Output voltage level freeze
The Output Level Freeze function, when enabled, turns off the Voltage Control Loop once
the ALC stays in a stable condition for about 3 periods of control loop, and maintains a
constant gain until the end of transmission. Output Level Freeze can be enabled using
Control Register bit 17 (Table 12). This function is available only using the Extended Control
Register (Control Register bit 21=”1”).
7.6
Extended control register
When Extended Control Register function is enabled, all the 48 bits of Control Register are
programmable. Otherwise, only the first 24 bits of Control Register are programmable. The
functions Header Recognition, Frame Bit Count and Output Voltage Freeze are available
only if Extended Control Register function is enabled. Extended Control Register can be
enabled using Control Register bit 21(Table 12).
37/44
Auxiliary analog and digital functions
7.7
ST7540
Under voltage lock out
The UVLO function turns off the device if the VCC voltage falls under 4V. Hysteresis is
340mV typically.
7.8
Thermal shutdown
The ST7540 is provided of a thermal protection which turn off the PLI when the junction
temperature exceeds 170°C ±10% . Hysteresis is around 30°C.
When shutdown threshold is overcome, PLI interface is switched OFF.
Thermal Shutdown event is notified to the HOST controller using BU/THERM line. When
BU/THERM line is High, ST7540 junction temperature exceed the shutdown threshold (Not
Latched). This function is enabled only in Transmission mode (in Receiving mode the
BU/THERM pin is used for Band in Use signaling, see Band in Use function Section 7.1:
Band in use).
7.9
5V Voltage regulator
ST7540 has an embedded 5V linear regulator externally available (on pin VDC) to supply
the application circuitry. The 5V linear regulator has a very low quiescent current (50µA) and
a current capability of 50mA. The regulator is protected against short circuitry events.
7.10
3.3V Voltage regulator
The VDD pin can act either as 3.3V Voltage Output or as Input Digital Supply. When the VDD
pin is externally forced to 5V all the Digital I/Os operate at 5V, otherwise all the Digital I/Os
are internally supplied at 3.3V. The VDD pin can also source 3.3V voltage to supply external
components. The 3.3V linear regulator has a very low quiescent current (50µA) and a
current capability of 50mA. The regulator is protected against short circuitry events.
7.11
Power-up procedure
To ensure ST7540 proper power-Up sequence, VCC and VDD Supply has to fulfil the
following rules:
1.
VCC rising slope must not exceed 100V/ms.
2.
When VDD is below 5V/3.3V: VCC-VDD < 1.2V.
When VDD supply is connected to VDC (5V Digital Supply) the above mentioned relation
can be ignored if VDC load < 50mA and if the filtering capacitor on VDC < 100uF.
If VDD is not forced to 5V, the Digital I/Os are internally supplied at 3.3 V and if VDD load <
50mA and the filtering capacitor on VDD < 100uF the second relation can be ignored .
38/44
ST7540
Auxiliary analog and digital functions
Figure 24. Power-up sequence
Voltage
5V/3.3V
VCC
VDD
VCC-VDD
D03IN1424
Time
39/44
40/44
HOST
CONTROLLER
5V Supply
for Host Controller
Clock & Reset for
Host Controller
RSTO
MCLK
5 Lines
Serial Interface
REG/DATA
CLR/T
RxTx
TxD
RxD
CD/PD
BU/THERM
WD
TEST1
TEST2
VDD
VDC
11
10
2
8
5
6
4
1
7
13
27
28
9
26
GND
3
ST7540
UART/SPI
12
SVss
20
21
22
24
23
16
19
25
18
15
14
17
X1_OSCIN
X2
RCL
CL
Vsense
VSS
TX_OUT
RX_IN
PA_IN+
PA_OUT
PA_IN-
VCC
R4
R3
Voltage
Regulation
&
Current
Protection
D03IN1412A
Z1
Z2
C1
AC/DC
Converter
R2
R1
AC LINE
No External Components
for POWER LINE DRIVER
SINGLE SUPPY
Auxiliary analog and digital functions
ST7540
Figure 25. Application schematic example with coupling transformer.
ST7540
8
Mechanical data
Mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
41/44
Mechanical data
ST7540
Table 13. HTSSOP28 Mechanical data
mm.
inch
Dim.
Min.
Typ.
Min.
Typ.
Max.
A
1.2
0.047
A1
0.15
0.006
A2
0.8
1.05
0.031
b
0.19
0.3
0.007
0.012
c
0.09
0.2
0.003
0.008
D (*)
9.6
9.8
0.377
D1
3.3
E
6.2
6.4
6.6
E1 (*)
4.3
4.4
4.5
E2
1.5
e
L
L1
1.0
9.7
aaa
0.041
0.382
0.385
0.244
0.252
0.260
0.169
0.173
0.177
0.65
0.45
0.039
0.130
0.6
0.026
0.75
0.018
1.0
k
0.024
0.039
0° (min), 8° (max)
0.1
Figure 26. Package dimensions
42/44
Max.
0.004
0.029
ST7540
9
Revision history
Revision history
Table 14. Revision history
Date
Revision
Changes
15-Mar-2006
1
Initial release.
25-Sep-2006
2
Updated Electrical Characteristics and Power Amplifier description
43/44
ST7540
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44/44