ST7LNB0 DiSEqC™ 2.1 Slave Microcontroller for LNBs and Switchers The ST7LNB0 is an 8-bit microcontroller dedicated to DiSEqC™ slave operation in LNBs and switchers, it is compliant with the DiSEqC™ 2.1 level, also it supports backwards compatible (13/ 18 V, 22 kHz tone) and toneburst signalling. ■ Clock, Reset and Supply Management – Reduced power consumption. – Safe power on/off management by low voltage detector (LVD). – Internal 8 MHz oscillator ■ Communication interface – One DiSEqC™ 2.1 communication interface ■ Analog interface SO16 150” ■ I/O ports – 8 output ports for control of committed and uncommitted switches – 1 output port for standby control – 13/18 V voltage detector – 22 KHz tone detector Figure 1. ST7LNB0 Block Diagram Internal CLOCK 8 MHz. RC OSC VDD VSS RESET POWER SUPPLY CONTROL 8-BIT CORE ALU ADDRESS AND DATA BUS LVD DiSEqC™ 2.1 22KHz tone Detector DTX DRX 13/18 V Detector OP[8:1] SWITCH PORTS SBY Table 1. Device Summary Features Packages Peripherals ST7LNB0Y0M6 SO16 150” DiSEqC™ 2.1 communication interface, 22KHz tone detector, 13/18V detector Operating Voltage 4.5 V t0 5.5 V Temperature range -40°C to +85°C Rev. 3.0 December 2004 1/22 1 ST7LNB0 1 ST7LNB0 PIN DESCRIPTION Figure 2 ST7LNB0 Pinout VSS 1 16 NC VDD RESET 2 15 3 14 NC DTX DRX OP5 4 13 SBY 5 12 OP1 OP6 6 11 OP2 OP7 7 10 OP3 OP8 8 9 OP4 The following table gives the pin functions Table 2. ST7LNB0 Pin Functions Pin Number 1 2 3 4 5 6 7 8 9 10 1) 11 12 13 14 15,16 Function Name Vss VDD RESET DRX OP5 OP6 OP7 OP8 OP4 OP3 OP2 OP1 SBY DTX - Function Description Ground Power Supply (+5 volts) Reset (active low) input Receive input output 5 (uncommitted port) output 6 (uncommitted port) output 7 (uncommitted port) output 8 (uncommitted port) output 4 (SO B/A) output 3 (SB/SA) output 2 (H/V) output 1 (Hi/Lo) STANDBY DiSEqC™ data transmit output Not used pins 2) Notes: 1. During normal operation this pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up 2. Unused pins 15 and 16 must be tied to ground. 2/22 1 ST7LNB0 2 ST7LNB0 IMPLEMENTATION The following figure shows a typical application circuit for the ST7LNB0: Figure 3 ST7LNB0 typical application circuit OPTIONAL 4.7K (4) F-CONNECTOR 2N2222 ST7LNB0 2.2 nF 10n 330K 100K LNB / SWITCHER CONTROL (Uncommitted SW) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SBY LNB / SWITCHER CONTROL (Committed SW) Notes: 1.The divider chain connected to the DRX pin must have the following resistance values: 330KΩ and 100KΩ. 2.The reset circuitry linked to the RESET pin is optional, in fact the ST7LNB0 has an internal voltage level detector LVD which generates a static reset when the VDD supply is below a threshold voltage of 4.1 V. 3.The DiSEqC signalling must have a tone frequency of 22KHz(+/- 20%) and an amplitude exceeding 150 mV peak to peak. 4. When the LVD is enabled (default state), it is mandatory not to connect a pull-up resistor. A 10nF pulldown capacitor is recommended to filter noise on the reset line. 3/22 1 ST7LNB0 3 ST7LNB0 FUNCTIONAL DESCRIPTION 3.1 ST7LNB0 Configuration Unlike the original slave microcontroller described in the “Eutelsat DiSEqC slave microcontroller version 1.0” the ST7LNB0 does not scan the control pins in order to determine the slave configuration, instead all configuration parameters must be programmed for each specific application, an Option List (Section 8) must be filled-in in order to program the necessary options at the manufacturing stage. The slave configuration parameters are the following: – The DiSEqC™ slave address e.g.: 11h for an LNB, 15h for a switcher. – The Local oscillator frequency table entry numbers. – The DiSEqC™ configuration byte (refer to DiSEqC slave microcontroller document page 15) – The output mode (see next paragraph) – 22 kHz tone use in backwards compatible mode (SB/SA or Hi/Lo switching) – Standby pin use. 3.2 ST7LNB0 Switching Output Modes The ST7LNB0 has 8 pins (OP1 to OP 8) available to provide ‘TTL’ logic levels to operate switches to select various signal conditions and sources (e.g. horizontal polarization, satellite position). As listed in Table 2 the committed output port is composed of OP1 to OP4 and the uncommitted output port is composed of OP5 to OP8. Depending on the application hardware, the switching control pins OP1 to OP8 may be operat- 4/22 ed differently. Three possible output modes can be configured: Single polarity output mode. In this mode each pin can be controlled individually as described in the following table: Table 3. Single polarity output mode Pin Number Function Name 9 10 11 12 5 6 7 8 OP4 OP3 OP2 OP1 OP5 OP6 OP7 OP8 Function Description SO B/A SB/SA Hor/Ver Hi/Lo SW5 SW6 SW7 SW8 Decoded output mode. This mode offers the possibility to demultiplex three adjacent committed or uncommitted control lines (e.g Hi/Lo, SB/SA and SOB/A) in order to have a 1 of 8 demux on the output port OP1 to OP8. (for more details refer to DiSEqC™ slave microcontroller specification document page 10). It is also possible to have a 1 of 4 demux by decoding only 2 control lines e.g. SB/SA and SO B/A for controlling a 1 of 4 switcher for example. Complementary output mode. In this mode the state of the uncommitted switching outport pins is the complementary of the state of the committed output ports pins (for more details refer to DiSEqC™ slave microcontroller document page 14). ST7LNB0 4 SUPPORTED DiSEqC™ COMMANDS Table 4. ST7LNB0 DiSEqC™ supported commands Command number (Hex byte) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 10h 11h 14h 15h 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 38h 39h 51h 52h 53h Command name RESET clr RESET STANDBY Power on Set Cont Contend Clr Cont Address Move C Move STATUS Config Group 0 Group 1 Set Lo Set VR Set Pos A Set SO A Set Hi Set HL Set Pos B Set SO B Set S1 A Set S2 A Set S3 A Set S4 A Set S1 B Set S2 B Set S3 B Set S4B Write N0 Write N1 LO LO Lo LO Hi Command Function Reset DiSEqC™ microcontroller Clear the “RESET” flag Switch peripheral power off Switch peripheral power supply off Set contention flag Return address only if contention flag is set Clear contention flag Return address unless contention flag is set Change address only if contention flag is set Change address unless contention flag is set Read STATUS register Read Configuration register Read switching state (committed port) Read switching state (uncommitted port) Select the low Local oscillator frequency Select the vertical polarization Select satellite position A Select switch Option A Select the Hi local oscillator frequency Select the Horizontal polarization Select satellite position B Select the switch Option B Select switch S1 input A Select switch S2 input A Select switch S3 input A Select switch S4 input A Select switch S1 input B Select switch S2 input B Select switch S3 input B Select switch S4 input B Write to port group 0 (committed switches) Write to port group 1 (uncommitted switches) Read current L.O frequency table entry number Read Lo L.O frequency table entry number Read Hi L.O frequency table entry number Note: After a power-on, the ST7LNB0 responds to backwards compatible signalling (13/18 V, 22 kHz, tone burst) until a valid DiSEqC frame is detected. In order to return to backwards compatible mode, a RESET command must be sent. 5/22 ST7LNB0 5 ST7LNB0 CONFIGURATION To configure the ST7LNB0 to the required target application, a dedicated DiSEqC command is implemented. This configuration is stored in the ST7LNB0 embedded EEPROM location. 5.1 COMMAND 0Fh ST7LNB0 devices are shipped to customers with a default parameter value. These parameters can be updated using a dedicated 0Fh DiSEqC command. This command has the following format where “data” is the parameter value to be programmed at the “index” location as shown in Table 5. E0h DiSEqC Slave address 0Fh index data Note: The special command E0 xx 0F FF FF protects the EEPROM data from any subsequent write access (where xx is the corresponding DiSEqC Slave address). 5.2 COMMAND 0Dh For reading a parameter inside the EEPROM a dedicated 0Dh command has been added. This command has the following format where” index” is the address in the EPPROM of the byte to be read (see Table 5) E2h DiSEqC Slave address 0Dh index :The reply frame has the following format where “data” is the read byte from the EEPROM: E4h data Timings: the time required to update a byte parameter (write and read operation) is 130 ms the time required to update all the parameters is about 3.5 s 6/22 ST7LNB0 Table 5. ST7LNB0 EEPROM Parameters index 00 01 02 03 04 Parameter slave address L.O frequencies output configuration Description DiSEqC slave address (00 to FFh), see note 1 see note 2 see note 3 Serial / version number user can enter a value:0000h to FFFFh Default Value 14h 00h 0Ah 1Bh, see note 4 FFh Notes: 1.Besides the address defined in the EEPROM at index 00h, addresses 10h and 00h are recognized also as valid addresses. 2. L.O frequencies : Local oscillator table entry numbers. - High nibble: High L.O frequency - Low nibble: Low L.O frequency 3.Output configuration byte: Bit Number 0 [1:4] 5 6 7 Bit Description 22 KHz use Value - 0: High/Low switching - 1: SB/SA switching - 0: mode not selected - [ 1 to 8] : decoded mode number - 0: mode not selected Complementary Mode Selection - 1: mode selected - 0: mode not selected 2 Lines Decoded Mode Selection - 1: mode selected Decoded Mode Selection Not Used -0 If neither the decoded mode nor the complementary mode is set then the “Single polarity mode” is selected by default. 4. Software version 7/22 ST7LNB0 6 ELECTRICAL CHARACTERISTICS 6.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are referred to VSS. 6.1.1 Minimum and Maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25°C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA=25°C, VDD=5V for the 4.5V≤VDD≤5.5V voltage range. They are given only as design guidelines and are not tested. 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 4. Figure 4. Pin loading conditions ST7 PIN CL 8/22 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 5. Figure 5. Pin input voltage ST7 PIN VIN ST7LNB0 6.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi6.2.1 Voltage Characteristics Symbol VDD - VSS VIN tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Ratings Maximum value Supply voltage Unit 7.0 Input voltage on any pin 1) & 2) V VSS-0.3 to VDD+0.3 VESD(HBM) Electrostatic discharge voltage (Human Body Model) VESD(MM) Electrostatic discharge voltage (Machine Model) see section 6.5.3 on page 13 6.2.2 Current Characteristics Symbol IVDD IVSS IIO IINJ(PIN) 2) & 4) Ratings Total current into VDD power lines (source) 100 Total current out of VSS ground lines (sink) 3) 100 Output current sunk by any standard I/O and control pin 25 Output current sunk by any high sink I/O pin 50 Output current source by any I/Os and control pin - 25 Injected current on RESET pin ±5 Injected current on any other pin ΣIINJ(PIN) 2) Maximum value 3) 5) & 6) Total injected current (sum of all I/O and control pins) 5) Unit mA ±5 ± 20 6.2.3 Thermal Characteristics Symbol TSTG TJ Ratings Storage temperature range Value Unit -65 to +150 °C Maximum junction temperature (see Section 7.2 THERMAL CHARACTERISTICS) Notes: 1. Directly connecting the I/O pins to VDD or VSS could damage the device if an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration. 2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. 3. All power (VDD) and ground (VSS) lines must always be connected to the external supply. 4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken: - Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage is lower than the specified limits) - Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as far as possible from the analog input pins. 5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device. 6. True open drain I/O port pins do not accept positive injection. 9/22 ST7LNB0 6.3 OPERATING CONDITIONS 6.3.1 General Operating Conditions: Symbol VDD TA Parameter Conditions Min Max Unit Supply voltage 4.5 5.5 V Ambient temperature -40 +85 °C Unit 6.3.2 Operating Conditions with Low Voltage Detector (LVD) Symbol Parameter Conditions Min Typ Max VIT+(LVD) Reset release threshold (VDD rise) 4.00 4.25 4.50 VIT-(LVD) Reset generation threshold (VDD fall) 3.80 4.10 4.30 Vhys LVD voltage threshold hysteresis VtPOR VDD rise time rate 1) tg(VDD) Filtered glitch delay on VDD IDD(LVD) LVD/AVD current consumption V VIT+(LVD)-VIT-(LVD) 200 20 mV 20000 Not detected by the LVD 150 200 µs/V ns µA Notes: 1. Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on and LVD reset. When the VDD slope is outside these values, the LVD may not ensure a proper reset of the MCU. 6.3.3 Operating Conditions with the DiSEqC™ Signalling Min Typ Max Unit fDiSEqC Symbol DiSEqC™ tone frequency Parameter Conditions 17.6 22 26.4 KHz VDiSEqC DiSEqC™ tone voltage 150 650 mVpp VBackward 13/18 volt backward compatibility voltage threshold 1) 15 V Notes: 1. In backwards compatible mode, bus DC voltage is compared with 15 V, if it exceeds this voltage then it is considered as 13 V else it is considered as 18 V. 10/22 ST7LNB0 6.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock 6.4.1 Supply Current TA = -40 to +125°C unless otherwise specified Symbol Parameter source current consumption. To get the total device consumption, the two current values must be added. Conditions Supply current in RUN mode 1) IDD VDD=5.5V, fCPU=8MHz Supply current for LNB or switcher applications 2) Typ Max 4.50 7 20 Unit mA Notes: 1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled. 2. Data based on typical ST7LNB0 LNB or switcher application software running. Figure 6. Typical IDD in RUN vs. fCPU 8MHz 5.0 4MHz Idd (mA) 4.0 1MHz 3.0 2.0 1.0 0.0 2.4 2.7 3.7 4.5 5 5.5 Vdd (V) 11/22 ST7LNB0 6.5 EMC CHARACTERISTICS Susceptibility tests are performed on a sample basis during product characterization. 6.5.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ■ ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. ■ FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-44 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. 6.5.1.1 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical applicaSymbol tion environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the management of runaway conditions such as: – Corrupted program counter – Unexpected reset – Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Parameter Level/ Class Conditions VFESD Voltage limits to be applied on any I/O pin to induce a VDD=5V, TA=+25°C, fOSC=8MHz functional disturbance conforms to IEC 1000-4-2 2B VFFTB Fast transient voltage burst limits to be applied V =5V, TA=+25°C, fOSC=8MHz through 100pF on VDD and VDD pins to induce a func- DD conforms to IEC 1000-4-4 tional disturbance 3B 6.5.2 Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/ 3 which specifies the board and the loading of each pin. Symbol SEMI Parameter Peak level Conditions Monitored Frequency Band 0.1MHz to 30MHz VDD=5V, TA=+25°C, 30MHz to 130MHz SO16 package, conforming to SAE J 1752/3 130MHz to 1GHz SAE EMI Level Notes: 1. Data based on characterization results, not tested in production. 12/22 Max vs. [fOSC/fCPU] 1/4MHz 1/8MHz 8 14 27 32 26 28 3.5 4 Unit dBµV - ST7LNB0 EMC CHARACTERISTICS (Cont’d) 6.5.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. 6.5.3.1 Electro-Static Discharge (ESD) Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22A114A/A115A standard. Absolute Maximum Ratings Symbol VESD(HBM) Ratings Electro-static discharge voltage (Human Body Model) Conditions TA=+25°C Maximum value 1) Unit 4000 V Notes: 1. Data based on characterization results, not tested in production. 6.5.3.2 Static and Dynamic Latch-Up ■ LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. ■ DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181. Electrical Sensitivities Symbol LU DLU Parameter Conditions Class 1) Static latch-up class TA=+25°C A Dynamic latch-up class VDD=5.5V, fOSC=4MHz, TA=+25°C A Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 13/22 ST7LNB0 6.6 I/O PORT PIN CHARACTERISTICS 6.6.1 General Characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Symbol Parameter Conditions Min Typ Max VIL Input low level voltage 0.3xVDD VIH Input high level voltage Vhys Schmitt trigger voltage hysteresis 1) IL Input leakage current VSS≤VIN≤VDD ±1 IS Static current consumption 2) Floating input mode 200 RPU Weak pull-up equivalent resistor3) VIN=VSS, VDD=5V CIO I/O pin capacitance 0.7xVDD 400 50 120 5 tf(IO)out Output high to low level fall time 1) tr(IO)out Output low to high level rise time 1) Unit V mV 250 µA kΩ pF 25 CL=50pF Between 10% and 90% ns 25 Notes: 1. Data based on characterization results, not tested in production. 2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see Figure 7). Data based on design simulation and/or technology characteristics, not tested in production. 3. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in Figure 8). Figure 7. Two typical Applications with unused I/O Pin VDD ST7XXX 10kΩ 10kΩ UNUSED I/O PORT UNUSED I/O PORT ST7XXX Note: only external pull-up allowed on ICCCLK pin Figure 8. Typical IPU vs. VDD with VIN=VSS l 90 Ta=140°C 80 Ta=95°C 70 Ta=25°C Ta=-45 °C Ipu(uA ) 60 50 TO BE CHARACTERIZED 40 30 20 10 0 2 14/22 2.5 3 3.5 4 4.5 Vdd(V) 5 5.5 6 ST7LNB0 I/O PORT PIN CHARACTERISTICS (Cont’d) 6.6.2 Output Driving Current Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Symbol VOH 2) Conditions Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 9) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 10) VDD=5V VOL 1) Parameter Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 11) Min Max IIO=+5mA 1.0 IIO=+2mA 0.4 IIO=+20mA 1.3 IIO=+8mA 0.75 IIO=-5mA VDD-1.5 IIO=-2mA VDD-0.8 Unit V Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Section 6.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 6.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH. 3. Not tested in production, based on characterization results. Figure 9. Typical VOL at VDD=5V (standard) Figure 10. Typical VOL at VDD=5V (high-sink) 2.50 0.80 2.00 -45°C 0°C 25°C 90°C 130°C 0.50 0.40 0.30 0.20 0.10 0.00 0.01 1 2 3 4 Vol (V) at VDD=5V (HS) 0.60 -45 0°C 25°C 90°C 130°C 1.50 1.00 0.50 5 0.00 lio (mA) 6 7 8 9 10 15 20 25 30 35 40 lio (mA) Figure 11. Typical VDD-VOH at VDD=5V 2.00 1.80 VDD-VOH at VDD=5V VOL at VDD=5V 0.70 1.60 1.40 1.20 1.00 TO BE CHARACTERIZED 0.80 0.60 -45°C 0°C 25°C 90°C 130°C 0.40 0.20 0.00 -0.01 -1 -2 -3 -4 -5 lio (mA) 15/22 ST7LNB0 6.7 CONTROL PIN CHARACTERISTICS 6.7.1 Asynchronous RESET Pin Symbol Parameter Conditions VIL Input low level voltage VIH Input high level voltage Vhys Schmitt trigger voltage hysteresis 1) VOL Output low level voltage 2) VDD=5V RON Pull-up equivalent resistor 3) 1) VDD=5V tw(RSTL)out Generated reset pulse duration th(RSTL)in External reset pulse hold time 4) tg(RSTL)in Filtered glitch duration 5) Min Typ Max 0.3xVDD 0.7xVDD 1 0.5 1.0 IIO=+2mA 0.2 0.4 40 80 Internal reset sources 30 V V IIO=+5mA 20 Unit V kΩ µs µs 20 200 ns Notes: 1. Data based on characterization results, not tested in production. 2. The IIO current sunk must always respect the absolute maximum rating specified in Section 6.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltage on RESET pin between VILmax and VDD 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. 5. The reset network protects the device against parasitic resets. 6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). 7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the VIL max. level specified in section 6.7.1 on page 16. Otherwise the reset will not be taken into account internally. 8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value specified for IINJ(RESET) in section 6.2.2 on page 9. 16/22 ST7LNB0 7 PACKAGE CHARACTERISTICS 7.1 PACKAGE MECHANICAL DATA Figure 12. 16-Pin Plastic Small Outline Package, 150-mil Width L Dim. 45× A A1 e B a A1 C H D mm Min 9 E Min Typ Max 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 9.80 10.00 0.386 0.394 E 3.80 4.00 0.150 0.157 1.27 H 5.80 α 0° L 0.40 8 1 Max A e 16 inches Typ 0.050 6.20 0.228 8° 0.244 0° 1.27 0.016 8° 0.050 Number of Pins N 16 0016020 7.2 THERMAL CHARACTERISTICS Symbol RthJA PD TJmax Ratings Package thermal resistance (junction to ambient) Power dissipation 1) Maximum junction temperature 2) Value Unit TBD °C/W 500 mW 150 °C Notes: 1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD) and PPORT is the port power dissipation determined by the user. 2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA. 17/22 ST7LNB0 7.3 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only as design guidelines. Figure 13. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb) 250 150 SOLDERING PHASE 80°C Temp. [°C] 100 50 COOLING PHASE (ROOM TEMPERATURE) 5 sec 200 PREHEATING PHASE Time [sec] 0 20 40 60 80 100 120 140 160 Figure 14. Recommended Reflow Soldering Oven Profile (MID JEDEC) 250 Tmax=220+/-5°C for 25 sec 200 150 90 sec at 125°C 150 sec above 183°C Temp. [°C] 100 50 ramp down natural 2°C/sec max ramp up 2°C/sec for 50sec Time [sec] 0 100 Recommended glue for SMD plastic packages: ■ Heraeus: PD945, PD955 Loctite: 3615, 3298 18/22 200 300 400 ST7LNB0 8 DEVICE CONFIGURATION 8.1 DATA EEPROM OPTION BYTES Byte Name FAM LOFREQ PARAM Description Device Family Address (11h:LNB ; 15h: switcher) Local Oscillator Frequency Table Entry Numbers Output Mode and 22 kHz Tone Use (Hi/Lo or SB/SA) Address 1002h 1003h 1004h FAM OPTION BYTE Device Family Address. 11h: Normal LNB 15h: Normal Switcher PARAM OPTION BYTE Output Mode and 22 kHz Tone Use (Hi/Lo or SB/ SA) Bit 7:8 = Not used. LOFREQ OPTION BYTE Local Oscillator Frequency Table Entry Number This byte indicates the value of a LNB local oscillator: Lowest Nibble = Lo Local Oscillator Frequency Table Entry Number Highest Nibble = Hi Local Oscillator Frequency Table Entry Number Note: see table 2 on page 8 of the “Eutelsat DisEqC slave microcontroller version 1.0”. Bit 6 = Decoded Mode With Only Two Lines (the lowest line of a selection group is kept low) 0: Decoded mode with only two lines not selected 1: Decoded mode with only two lines selected Bit 5 = Complementary Mode Selection 0: Complementary Mode not selected 1: Complementary Mode selected Bit 4:1 = Decoded Mode Number 0: Decoded Mode not selected 1 to 8 : Decoded Mode Number (refer to table 5a on page 11 of the “Eutelsat DisEqC slave microcontroller version 1.0”). Bit 0 = 22 kHz Tone Use 0: 22 kHz tone use for Hi/Lo switching in backwards compatible mode 1: 22 kHz tone use for SB/SA switching in backwards compatible mode Note: if neither a decoded mode nor a complementary output mode is selected, the output mode is the single polarity output mode (refer to Table 3, “Single polarity output mode,” on page 4). 19/22 ST7LNB0 ST7LNB0 DiSEqC™ “slave” MICROCONTROLLER OPTION LIST (Last update: December 2004) Customer Address Contact Phone No ................................................................. ................................................................. ................................................................. ................................................................. ................................................................. - Family address (tick one box) Normal LNB (11h) Normal Switcher (15h) - Backwards Compatible 22 kHz tone usage (tick one box) Hi/Lo switching SB/SA switching - Local oscillator frequencies table entry number Hi L.O table entry number Lo L.O table entry number - Switching output type: (tick or fill one box) Single polarity output Decoded mode output (indicate the mode number) Complementary output Comments: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ................................................................. ................................................................. Notes ................................................................. ................................................................. ................................................................. Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Date ................................................................. Please download the latest version of this option list from: http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list 20/22 ST7LNB0 9 REVISION HISTORY Date September-04 December-04 Revision Main changes 2.0 First release on st.com 3.0 Changed note 4 and added “optional” in Figure 3 “ST7LNB0 typical application circuit” on page 3 Added default values in Table 5, “ST7LNB0 EEPROM Parameters,” on page 7 21/22 ST7LNB0 Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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