STA333ML Sound Terminal™ 2-channel microless high-efficiency digital audio system Features ! Wide supply voltage range (4.5 - 18 V) ! 2 x 20 W into 8 Ω at Vcc = 18 V ! 3 power output configurations; 2 channels of ternary PWM PowerSSO-36 slug down ! PowerSSO-36 exposed pad package ! 2 channels of 24-Bit DDX® ! 100-dB SNR and dynamic range ! 32 kHz to 48 kHz input sample rates ! Soft volume update ! Automatic zero-detect mute ! Automatic invalid input detect mute ! 2-channel I2S input data interface ! Selectable clock input ratio (256 or 364 x fs) ! Max power correction for lower full power ! 96 kHz internal processing sample rate, 24-bit precision ! Thermal overload and short-circuit protection embedded Applications ! LCD ! DVD ! Cradle ! Digital speaker ! Wireless speaker cradle Description STA333ML is a single die embedding digital audio processing and high efficiency DDX® power amplification, capable of operating without the aid of an external micro controller. The STA333ML is part of the Sound Terminal™ family that provides full digital audio streaming to the speaker offering cost effectiveness, low energy dissipation and sound enrichment. The STA333ML combines a unique 24-bit DDX® digital class-D ternary modulator together with an extremely low RDSON stereo power DMOS stage. It is capable of a total output power of 2 x 20 W with outstanding performance in terms of efficiency (>90 %), THD, SNR and EMI. The microless feature allows the use in low-cost applications (cradle, digital speakers, audio terminals) where no micro controller is needed. The serial audio data interface accepts the universally used I2S format. Basic features (like oversampling clock, gain and I2S format) can be set using a minimal number of selection pins. The STA333ML is self-protected against thermal overload, overcurrent, short circuit and overvoltage conditions. The fault condition is also exported to an external pin (INT_LINE) for specific requirements. Table 1. Device summary Order code Package Packaging STA333ML PowerSSO-36 (slug down) Tube STA333ML13TR PowerSSO-36 (slug down) Tape and reel May 2008 Rev 2 1/14 www.st.com 14 Block diagram 1 STA333ML Block diagram Figure 1. Block diagram Protection current/thermal 2 I S interface Volume control Channel 1A Power control Logic Channel 1B DDX Channel 2A Regulators Channel 2B PLL Bias 2/14 STA333ML 2 Pin description Pin description Figure 2. Table 2. Pin connection (top view) GND_SUB 1 36 VDD_DIG FMT 2 35 GND_DIG TEST_MODE 3 34 GAIN VSS_REG 4 33 ONSEL VCC_REG 5 32 INT_LINE OUT2B 6 31 RESET GND2 7 30 SDI VCC2 8 29 LRCKI OUT2A 9 28 BICKI OUT1B 10 27 XTI VCC1 11 26 PLL_GND GND1 12 25 FILTER_PLL OUT1A 13 24 VDD_PLL GND_REG 14 23 PWRDN VDD_REG 15 22 GND_DIG CONFIG 16 21 VDD_DIG N.C. 17 20 N.C. N.C. 18 19 N.C. Pin description Pin Type Name Description 1 Gnd GND_SUB 2 I FMT 3 I TEST_MODE 4 I/O VSS 5 I/O VSS_REG Internal Vcc reference 6 O OUT2B Output half bridge 2B 7 Gnd GND2 Power negative supply 8 Power VCC2 Power positive supply 9 O OUT2A Output half bridge 2A 10 O OUT1B Output half bridge 1B 11 Power VCC1 Power positive supply 12 Gnd GND1 Power negative supply Substrate ground 0: I2S format 1: left justified This pin must be connected to ground Internal reference at Vcc-3.3 V 3/14 Pin description STA333ML Table 2. 4/14 Pin description (continued) Pin Type Name Description 13 I/O OUT1A 14 GND GND_REG Internal ground reference 15 Power VDD_REG Internal 3.3 V reference voltage 16 I CONFIG Output half bridge 1A Paralleled mode command 17 N.C. Not connected 18 N.C. Not connected 19 N.C. Not connected 20 N.C. Not connected 21 Power VDD_DIG Positive supply digital 22 GND GND_DIG Digital ground 23 I PWDN 24 Power VDD_PLL Positive supply for PLL 25 I FILTER_PLL Connection to PLL filter 26 GND GND_PLL Negative supply for PLL 27 I XTI 28 I BICKI I2S serial clock 29 I LRCKI I2S left/right clock 30 I SDI 31 I RESET 32 O INT_LINE 33 I ONSEL 34 I GAIN Gain selector: 0: 0 dBFS 1: 24 dBFS 35 GND GND_DIG Digital ground 36 Power VDD_DIG Digital supply Power down: 0: low-power mode 1: normal operation PLL input clock, 256 x fs or 384 x fs I2S serial data channel Reset Fault interrupt Oversampling selector: 0: 256 fs 1: 384 fs STA333ML Electrical specifications 3 Electrical specifications 3.1 Thermal data Table 3. Thermal data Symbol Typ. Max. Unit Thermal resistance junction to case (thermal pad) 1.5 2 °C/W Tsd Thermal shut-down junction temperature 150 °C Tw Thermal warning temperature 130 °C Thsd Thermal shut-down hysteresis 20 °C RTh(j-case) Parameter 3.2 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol VCC Parameter Min. Typ. Max. Unit 20 V 4 V 4 V 0 150 °C -40 150 °C Max. Unit 18.0 V Power supply voltage (VCC1, VCC2) VL Logic input interface VDD_DIG Positive supply digital -0.3 Top Operating junction temperature Tstg Storage temperature 3.3 Recommended operating condition Table 5. Recommended operating condition Symbol VCC Min. Parameter Min. Typ. Power supply voltage (VCC1, VCC2) 4.5 VL Logic Input Interface 2.7 3.3 3.6 V VDD_DIG Positive supply digital 2.7 3.3 3.6 V Tamb Ambient temperature 0 70 °C 5/14 Electrical specifications 3.4 STA333ML Electrical characteristics The specifications given here are with the operating conditions VCC = 18 V, VDD_DIG =3.3 V, fsw = 384 kHz, Tamb = 25° C and RL = 8 Ω, unless otherwise specified. Table 6. Electrical characteristics Symbol Po Parameter Conditions Min. Typ. THD = 1% 16 THD = 10% 20 180 Max. Output power BTL Unit W RdsON Power Pchannel/Nchannel MOSFET (total bridge) ld = 1 A ldss Power Pchannel/Nchannel leakage Vcc = 18 V gP Power Pchannel RdsON matching ld = 1 A 95 % gN Power Nchannel RdsON matching ld = 1 A 95 % ILDT Low current dead time (static) Resistive load, see Figure 3 5 10 ns IHDT High current dead time (dynamic) lload = 1.5 A, see Figure 3 10 20 ns tr Rise time Resistive load, seeFigure 3 8 10 ns tf Fall time Resistive load, see Figure 3 8 10 ns 18 V VCC Supply voltage (VCC1, VCC2) 4.5 250 mΩ 10 µA Supply current from VCC in power down mode PWRDN = 0 0.1 mA Supply current from VCC in operation PCM input signal = -60 dBFS. Switching frequency = 384 kHz No LC filters 30 mA Supply current DDX processing (reference only) Internal clock = 49.152 MHz 80 mA Ilim Overcurrent limit Nonlinear output 2.2 3.5 4.3 A Isc Short circuit protection Hi-Z output 2.7 3.8 5.0 A 3.5 4.3 V 30 60 ns Icc UVL Under voltage protection threshold tmin Output minimum pulse width DR Dynamic range SNR Signal to noise ratio No load A-weighted 20 100 dB 94 dB THD+N Total harmonic distortion and noise Po = 1 W, f = 1 kHz PSRR Power supply rejection ratio DDX stereo, < 5 kHz Vripple = 1 V RMS Audio input = dither only 80 dB XTALK Crosstalk DDX stereo, < 5 kHz One channel driven at 1 W other channel measured 80 dB Peak efficiency, DDX mode Po = 2 x 20 W, 8 Ω 90 % η 6/14 0.05 0.2 % STA333ML 3.5 Electrical specifications Testing Figure 3. Test circuits OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% DTf M58 OUTxY INxY R 8Ω M57 + - V67 = vdc = Vcc/2 gnd D03AU1458 High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) M58 DTin(A) Q1 Q2 INA L67 22µ Q3 C69 470nF M64 DTin(B) OUTB INB L68 22µ Iout=4A Lout = 1.5 A M57 DTout(B) Rload=8Ω OUTA Iout=4A Lout = 1.5 A C71 470nF C70 470nF Q4 Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure M63 D03AU1517 7/14 Functional description STA333ML 4 Functional description 4.1 Serial audio interface protocols Figure 4. I2S Lrclki Bicki Sdi Figure 5. n-1 n 11 2 33 1 2 3 n-1 n Left justified Lrclki/ Lrclko Biclki/ Biclko Sdatai/ Sdatao 4.2 1 2 3 n-1 n 1 2 3 n-1 n Fault detect recovery bypass The on-chip STA333ML power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either over-current or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tristate output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for 1 ms and then toggles it back to 1. This sequence is repeated for as long as the fault exists. 4.3 Zero-detect mute enable If this function is enabled, the zero-detect circuit examines each processing channel to see if 2048 consecutive zero value samples (regardless of fs) are received. If so the channel is muted. 8/14 STA333ML 5 Package thermal characteristics Package thermal characteristics The amount of power dissipated within the device depends primarily on the supply voltage, load impedance and output modulation level. For the STA333ML the maximum dissipated power is approximately 3 W. Thus, at an ambient temperature of 70 °C (the generally recommended maximum for consumer applications) the device can tolerate a further temperature rise of around 80° C before thermal shutdown is invoked (at Tj = 150° C). A suitable heatsink must, therefore, be found. Now, a thermal resistance of 25° C/W can be achieved using a ground copper area of 3 x 3 cm2, and 16 vias, on the PCB as shown in Figure 6. This gives a tiny margin of safety near to the upper recomended operating limits. Figure 6. Using the PCB as heatsink 9/14 Package information 6 STA333ML Package information Figure 7 shows the 36-pin PowerSSO package drawing and Table 7 gives the dimensions. PowerSSO-36 slug down outline drawing h x 45° Figure 7. 10/14 STA333ML Package information Table 7. PowerSSO-36 slug down dimensions mm inch Symbol Min Typ Max Min Typ Max A 2.15 - 2.47 0.085 - 0.097 A2 2.15 - 2.40 0.085 - 0.094 a1 0 - 0.10 0 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 e3 - 8.5 - - 0.335 F - 2.3 - - 0.091 G - - 0.10 - - H 10.10 - 10.50 0.398 h - - 0.40 0.016 k 0 - 8 degrees 8 degrees L 0.60 - 1.00 M - 4.30 - N - - 10 degrees O - 1.20 - 0.047 Q - 0.80 - 0.031 S - 2.90 - 0.114 T - 3.65 - 0.144 U - 1.00 - 0.039 X 4.10 4.70 0.161 0.185 Y 6.50 7.10 0.256 0.280 0.004 0.413 0.024 0.039 0.169 10 degrees In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 11/14 Trademarks and other acknowledgements 7 Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. Sound Terminal is a trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. 12/14 STA333ML STA333ML 8 Revision history Revision history Table 8. Document revision history Date Revision Changes 2-May-2008 2 Package information update 1-Feb-2007 1 Initial release. 13/14 STA333ML Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 14/14