STMICROELECTRONICS STDVE001A

STDVE001A
Adaptive single 3.4 Gbps TMDS/HDMI signal equalizer
Preliminary Data
Features
■
Compatible with the high-definition multimedia
interface (HDMI) v1.3 digital interface
■
Conforms to the transition minimized
differential signaling (TMDS) voltage standard
on input and output channels
■
340 MHz maximum clock speed operation
supports all video formats with deep color at
maximum refresh rates
■
3.4 Gbps data rate per channel
■
Fully automatic adaptive equalizer for cables
lengths up to 25 m
■
Single supply VCC: 3.135 to 3.465 V
■
ESD: ±8 KV contact for all I/Os
■
Integrated open-drain I2C buffer for display
data channel (DDC)
■
5.3 V tolerant DDC and HPD I/Os
■
Lock-up free operation of I2C bus
■
0 to 400 kHz clock frequency for I2C bus
■
Low capacitance of all the channels
■
Equalizer regenerates the incoming attenuated TMDS signal
■
Buffer drives the TMDS outputs over long PCB
track lengths
■
Low output skew and jitter
■
Tight input thresholds reduce bit error rates
■
On-chip selectable 50 Ω input termination
■
Low ground bounce
■
Data and control inputs provide undershoot
clamp diode
TQFP48
QFN48
Description
The STDVE001A integrates a 4-channel 3.4 Gbps
TMDS equalizer. High-speed data paths and flowthrough pinout minimize the internal device jitter
and simplify the board layout.
The equalizer overcomes the intersymbol
interference (ISI) jitter effects from lossy cables.
The buffer/driver on the output can drive the
TMDS output signals over long distances. In
addition to this, STDVE001A integrates the 50 Ω
termination resistor on all the input channels to
improve performance and reduce board space.
The device can be placed in a low-power mode by
disabling the output current drivers. The
STDVE001A is ideal for advanced TV and STB
applications supporting HDMI/DVI standard. The
differential signal from the HDMI/DVI ports can be
routed through the STDVE001A to guarantee
good signal quality at the HDMI receiver.
Designed for very low skew, jitter and low I/O
capacitance, the switch preserves the signal
integrity to pass the stringent HDMI compliance
requirements.
■
Evaluation kit is available
Table 1.
Device summary
Order code
Operating temperature
Package
Packaging
STDVE001ABTR
-40°C to 85°C
TQFP48
Tape and reel
STDVE001AQTR
-40°C to 85°C
QFN48
Tape and reel
July 2008
Rev 2
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/49
www.st.com
49
Contents
STDVE001A
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
5
3.1
Adaptive equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3
HPD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4
DDC channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5
I2C DDC line repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6
Power-down condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7
Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8
Timing between HPD and DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9
CEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3
DC electrical characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . . . . . . 26
4.4
DC electrical characteristics (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.5
Dynamic switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.6
Dynamic switching characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . 30
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.1
Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.2
Power supply requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3
Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3.1
I2C lines application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2/49
STDVE001A
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Adaptive equalizer gain with frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
OE_N operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bias parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC specifications for TMDS differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC specifications for TMDS differential ouputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC specifications for OE_N, EQ_BOOST, EQ_BOOST2, PRE, DDC_EN inputs . . . . . . . 23
Input termination resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
External reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DDC I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Status pins (HPD_INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Status pins (HPD_EXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Input/output SDA, SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC electrical characteristics (CEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Clock and data rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Differential output timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DDC I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Status pins (HPD_INT, HPD_EXT, OE_N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
I2C repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TQFP48 (7 x 7 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
QFN48 (7 x 7 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3/49
List of figures
STDVE001A
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
4/49
STDVE001A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Equalizer functional diagram (one signal pair) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DDC I2C bus repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STDVE001A in a digital TV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin configuration (TQFP48 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin configuration (QFN48 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
STDVE001A gain vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Test circuit for electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TMDS output driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Test circuit for HDMI receiver and driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Test circuit for turn off and turn off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Test circuit for short circuit output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TSK(O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TSK(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TSK(D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
AC waveform 1 (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Test circuit for AC measurements (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
I2C bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Typical application of I2C bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
TQFP48 (7 x 7 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TQFP48 (7 x 7 mm) footprint recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
TQFP48 (7 x 7 mm) tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
QFN48 (7 x 7 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
STDVE001A
1
Block diagram
Block diagram
Figure 1.
STDVE001A block diagram
4-$3
DIFFERENTIAL
INPUTS
)NPUT
TERMINATION
SELECTABLE
)NPUTSTAGE
RECEIVER
%QUALIZER
/UTPUT
$RIVER
4RANSMITTER
4-$3
DIFFERENTIAL
OUTPUTS
3$!?%84
3#,?%84
) #
REPEATER
3$!?).4
3#,?).4
$$#?%.
(0$?%84
(0$
DRIVER
(0$?).4
#%#?)/
#%#?)/?).4
!-6
5/49
Block diagram
STDVE001A
Figure 2.
Equalizer functional diagram (one signal pair)
EQ_BOOST 1, 2
OE_N
PRE
Data+
50 Ω
Termination
Selectable
Pre-Amp
Equalizer
OE_N
Quantizer
Output
I
Driver
Data-
Output current
control
REXT
AM00720V2
Figure 3.
DDC I2C bus repeater
)#BUSREPEATER
$$#?%.
3$!?%84
9?$$#?3$!
$$#?%.
3#,?%84
9?$$#?3#,
!-6
6/49
STDVE001A
Application diagrams
Figure 4.
STDVE001A in a digital TV
$6$2
34"
"ACKPANEL
460#"BOARD
($-)?"
($-)?#
PORT($-)RECEIVER
,ONG0#"4RACK
1.1
Block diagram
34$6%!
($-)?!
&RONTPANELOFAHIGH END46
'AME
CONSOLE
!-6
7/49
Pin configuration
Pin configuration
(0$?).4
3$!?).4
3#,?).4
/%?.
'.$
$$#?%.
6$$?).4
6##
%1?"//34
'.$
%1?"//34
'.$
Pin configuration (TQFP48 package)
'.$
'.$
).?$
/54 ?$
).?$
/54 ?$
6##
6##
).?$
/54 ?$
).?$
/54 ?$
'.$
'.$
).?$
/54 ?$
).?$
/54 ?$
6##
6##
).?$
/54 ?$
).?$
/54 ?$
(0$?%84
3$!?%84
3#,?%84
'.$
2%84
'.$
#%#?)/?).4
6$$?%84
#%#?)/
6##
02%
41&0
Figure 5.
'.$
2
STDVE001A
!-6
8/49
STDVE001A
Pin configuration
OE_N
SDA_INT
29
25
HPD_INT
30
VDD_INT
GND
31
26
DDC_EN
32
GND
VCC
33
27
EQ_BOOST1
34
SCL_INT
EQ_BOOST2
35
28
GND
Pin configuration (QFN48 package)
36
Figure 6.
24
GND
GND
37
23
38
OUT_D1-
IN_D1-
22
OUT_D1+
IN_D1+
39
VCC
VCC
40
21
IN_D2-
20
OUT_D2-
41
19
OUT_D2+
IN_D2+
42
18
GND
GND
43
17
OUT_D3-
IN_D3-
44
16
OUT_D3+
IN_D3+
45
15
VCC
VCC
46
14
OUT_D4-
IN_D4-
47
13
OUT_D4+
IN_D4+
48
1
2
3
4
5
6
7
8
9
10
11
12
GND
VCC
CEC_IO
CEC_IO_INT
GND
REXT
HPD_EXT
SDA_EXT
SCL_EXT
PRE
VDD_EXT
GND
QFN-48
!-6
9/49
Pin configuration
STDVE001A
Table 2.
Pin description
Pin number
Pin name
Type
Function
1
GND
Power
Ground
2
VCC
Power
3.3 V±5% DC supply
3
CEC_IO
I/O
CEC signal to/from the connector end
4
CEC_IO_INT
I/O
CEC signal to/from TV end
5
GND
Power
Ground
6
REXT
Analog
Connect to GND through a 4.7 KΩ ± 1% precision
reference resistor. Sets the output current to generate
the output voltage compliant with TMDS
7
HPD_EXT
Output
0 to 5.0 V (nominal) output signal. Hot plug detector
output. Open drain output. Connect an external resistor
according to the HDMI specification.
8
SDA_EXT
I/O
DDC data I/O. Pulled-up by external termination to VDD.
9
SCL_EXT
I/O
DDC clock I/O. Pulled-up by external termination to VDD.
TMDS output de-emphasis adjustment
10
PRE
PRE
Output de-emphasis
0V
0 dB
Input
3.3 V
10/49
3 dB
11
VDD_EXT
Power
DC supply for DDC, HPD and CEC (can be 5V or 3.3V or
unconnected)
12
GND
Power
Ground
13
OUT_D4+
Output
HDMI 1.3 compliant TMDS output. OUT_D4+ makes a
differential output signal with OUT_D4-.
14
OUT_D4-
Output
HDMI 1.3 compliant TMDS output. OUT_D4- makes a
differential output signal with OUT_D4+.
15
VCC
Power
3.3V±10% DC supply
16
OUT_D3+
Output
HDMI 1.3 compliant TMDS output. OUT_D3+ makes a
differential output signal with OUT_D3-.
17
OUT_D3-
Output
HDMI 1.3 compliant TMDS output. OUT_D3- makes a
differential output signal with OUT_D3+.
18
GND
Power
Ground
19
OUT_D2+
Output
HDMI 1.3 compliant TMDS output. OUT_D2+ makes a
differential output signal with OUT_D2-.
20
OUT_D2-
Output
HDMI 1.3 compliant TMDS output. OUT_D2- makes a
differential output signal with OUT_D2+.
21
VCC
Power
3.3V±10% DC supply
STDVE001A
Pin configuration
Table 2.
Pin description (continued)
Pin number
Pin name
Type
Function
22
OUT_D1+
Output
HDMI 1.3 compliant TMDS output. OUT_D1+ makes a
differential output signal with OUT_D1-.
23
OUT_D1-
Output
HDMI 1.3 compliant TMDS output. OUT_D1- makes a
differential output signal with OUT_D1+.
24
GND
Power
Ground
Active low enable signal
OE_N
25
OE_N
N_D
termination
IOUT_D outputs
Input
1
High-Z
0
50 Ω
High-Z
Active
26
VDD_INT
Power
DC supply for DDC, HPD and CEC (can be 5V or 3.3V or
unconnected)
27
GND
Power
Ground
28
SCL_INT
I/O
DDC Clock I/O. Pulled-up by external termination to
VCC.
29
SDA_INT
I/O
DDC Data I/O. Pulled-up by external termination to VCC.
Sink side, Low-frequency, 0V to 5V (nominal) hot plug
detector input signal.
30
HPD_INT
Input
Voltage high indicates “plugged” state; voltage low
indicates “unplugged” state.
High : 5V power signal asserted from source to sink and
EDID is ready
Low : No 5V power signal is asserted from source to sink
or EDID is not ready
31
GND
Power
32
DDC_EN
Input
Ground
I2C repeater enable signal
DDC_EN
33
VCC
Power
I2C repeater
0V
Disabled, high-Z
3.3 V
Enabled, active
3.3 V±10% DC supply
11/49
Pin configuration
Table 2.
Pin number
STDVE001A
Pin description (continued)
Pin name
Type
Function
TMDS input equalization selector (control pin).
EQ_BOOST EQ_BOOST
2
1
34-35
EQ_BOOST1,
EQ_BOOST2
Input
0
0
11 dB
0
1
9 dB
0
4 dB
1
16 dB
1
1
12/49
Setting at 825 MHz
36
GND
Power
Ground
37
GND
Power
Ground
38
IN_D1-
Input
HDMI 1.3 compliant TMDS input. IN_D1- makes a
differential pair with IN_D1+.
39
IN_D1+
Input
HDMI 1.3 compliant TMDS input. IN_D1+ makes a
differential pair with IN_D1-.
40
VCC
Power
3.3V±10% DC supply
41
IN_D2-
Input
HDMI 1.3 compliant TMDS input. IN_D2- makes a
differential pair with IN_D2+.
42
IN_D2+
Input
HDMI 1.3 compliant TMDS input. IN_D2+ makes a
differential pair with IN_D2-.
43
GND
Power
Ground
44
IN_D3-
Input
HDMI 1.3 compliant TMDS input. IN_D3- makes a
differential pair with IN_D3+.
45
IN_D3+
Input
HDMI 1.3 compliant TMDS input. IN_D3+ makes a
differential pair with IN_D3-.
46
VCC
Power
3.3V±10% DC supply
47
IN_D4-
Input
HDMI 1.3 compliant TMDS input. IN_D4- makes a
differential pair with IN_D4+.
48
IN_D4+
Input
HDMI 1.3 compliant TMDS input. IN_D4+ makes a
differential pair with IN_D4-.
STDVE001A
3
Functional description
Functional description
The STDVE001A routes physical layer signals for high bandwidth digital video and is
compatible with low voltage differential signaling standard like TMDS. The device passes the
differential inputs from a video source to a common display when it is in the active mode of
operation. The device conforms to the TMDS standard on both inputs and outputs.
The low on-resistance and low I/O capacitance of the switch in STDVE001A result in a very
small propagation delay. Additionally, it supports the DDC, HPD and CEC signaling.
The I2C interface of the enabled input port is linked to the I2C interface of the output port,
and the hot plug detector (HPD) of the enabled input port is output to HPD_EXT.
3.1
Adaptive equalizer
The equalizer dramatically reduces the intersymbol interference (ISI) jitter and attenuation
from long or lossy transmission media. The inputs present high impedance when the device
is not active or when VCC is absent or 0 V. In all other cases, the 50 Ω termination resistors
on input channels are present.
This circuit helps to improve the signal eye pattern significantly. Shaping is performed by the
gain stage of the equalizer to compensate the signal degradation and then the signals are
driven on to the output ports.
The equalizer is fully adaptive and automatic in function providing smaller gain at low
frequencies and higher gain at high frequencies. The default setting of EQ = 00 is
recommended on EQ pins for optimized operation.
Table 3.
Adaptive equalizer gain with frequency
Freq (MHz)
Gain in dB
(EQ=00)
Gain in dB
(EQ=01)
Gain in dB
(EQ=10)
Gain in dB
(EQ=11)
225
3
2
0
6.5
325
5
3
1
8.5
410
6.5
4.5
1.5
11
825
11
9
4
16
1650
16
14
8.5
21.5
13/49
Functional description
Figure 7.
STDVE001A
STDVE001A gain vs. frequency
Gain v/s Freq (STDVE001A)
25
Gain (dB)
20
Gain (EQ=00)
15
Gain (EQ=01)
10
Gain (EQ=10)
Gain (EQ=11)
5
0
225
325
410
825
1650
Freq (MHz)
The equalizer of STDVE001A is fully adaptive and automatic in function. The default setting
of EQ = 00 is recommended for optimal operation. The equalizer performance is optimized
for all frequencies over the cable lengths from 1m to 25 m at EQ = 00. If cable lengths
greater than 25 m are desired in application, then EQ = 11 setting is recommended. The
other two EQ settings of 01 and 10 are provided simply for fine-tuning purposes and can be
used for very short external cables or PCB traces only if deemed necessary.
Input termination
The STDVE001A integrates precise 50 Ω ± 5% termination resistors, pulled up to VCC, on all
its differential input channels. External terminations are not required. This gives better
performance and also minimizes the PCB board space. These on-chip termination resistors
should match the differential characteristic impedance of the transmission line. Since the
output driver consists of current steering devices, an output voltage is not generated without
a termination resistor. Output voltage levels are dependent on the value of the total
termination resistance. The STDVE001A produces TMDS output levels for point-to-point
links that are doubly terminated (100 Ω at each end). With the typical 10 mA output current,
the STDVE001A produces an output voltage of 3.3 – 0.5 V = 2.8 V when driving a
termination line terminated at each end. The input terminations are selectable thus saving
power for the unselected ports.
Output buffers
Each differential output of the STDVE001A drives external 50 Ω load (pull-up resistor) and
conforms to the TMDS voltage standard. The output drivers consist of 10 mA differential
current-steering devices.
The driver outputs are short-circuit current limited and are high-impedance to ground when
OE_N = H or the device is not powered. The current steering architecture requires a
resistive load to terminate the signal to complete the transmission loop from VCC to GND
through the termination resistor. Because the device switches the direction of the current
flow and not voltage levels, the output voltage swing is determined by VCC minus the voltage
drop across the termination resistor. The output current drivers are controlled by the OE_N
pin and are turned off when OE_N is a high. A stable 10 mA current is derived by accurate
internal current mirrors of a stable reference current which is generated by band-gap voltage
across the REXT. The differential output driver provides a typical 10 mA current sink
capability, which provides a typical 500 mV voltage drop across a 50 Ω termination resistor.
14/49
STDVE001A
Functional description
TMDS voltage levels
The TMDS interface standard is a signaling method intended for point-to-point
communication over a tightly controlled impedance medium. The TMDS standard uses a
lower voltage swing than other common communication standards, achieving higher data
rates with reduced power consumption while reducing EMI emissions and system
susceptibility to noise. The device is capable of detecting differential signals as low as
100 mV within the entire common mode voltage range.
3.2
Operating modes
Table 4.
OE_N operating modes
Input
Output
Function
OE_N
IN+
IN-
OUT+
OUT-
L
H
L
H
L
Active mode
L
L
H
L
H
Active mode
H
X
X
Hi-Z
Hi-Z
Low power mode
The OE_N input activates a hardware power down mode. When the power down mode is
active (OE_N = H), all input and output buffers and internal bias circuitry are powered-off
and disabled.
Outputs are tri-stated in power-down mode. When exiting power-down mode, there is a
delay associated with turning on band-references and input/output buffer circuits.
Note that the OE_N pin is only used to disable the TMDS paths in the chip to same
maximum amount of current. It does not affect the HPD, DDC and CEC portions. The DDC
is controlled only by the DDC_EN pin whereas the HPD and CEC are always active as long
as the supply to the chip is present.
15/49
Functional description
3.3
STDVE001A
HPD pins
The input pin HPD_INT is 5 V tolerant, allowing direct connection tp 5 V signals. The output
HPD pin has open-drain structure so that the disabled HPD output is driven to GND
whereas the enabled HPD port has the same polarity as the HPD_INT. Note that the HPD
output should have an external pull-up resistor connected to +5 V from the HDMI source.
3.4
DDC channels
The DDC channels are designed together with a bi-directional buffer so as to ensure the
voltage levels on the I2C lines are met even after long capacitive cables. This feature
eliminates the errors during EDID and HDCP reading.
16/49
STDVE001A
3.5
Functional description
I2C DDC line repeater
The device contains two identical bi-directional open-drain, non-inverting buffer circuits that
enable I2C DDC bus lines to be extended without degradation in system performance. The
STDVE001A buffers both the serial data (DDC SDA) and serial clock (DDC SCL) on the I2C
bus, while retaining all the operating modes and features of the I2C system. This enables
two buses of 400 pF bus capacitance to be connected in an I2C application. These buffers
are operational from a supply V of 3.0 V to 3.6 V.
The I2C bus capacitance limit of 400 pF restricts the number of devices and bus length. The
STDVE001A enables the system designer to isolate the two halves of a bus,
accommodating more I2C devices or longer trace lengths. It can also be used to run two
buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz
bus is isolated when 400 kHz operation of the other bus is required. The STDVE001A can
be used to run the I2C bus at both 5 V and 3.3 V interface levels.
The DDC_EN acts as the enable for the DDC buffer. The DDC_EN line should not change
state during an I2C operation, because disabling during bus operation hangs the bus and
enabling port may through a bus cycle could confuse the I2C ports being enabled. The
DDC_EN input should change state only when the global bus and repeater port are in idle
state, to prevent system failures.
The output low levels for each internal buffer are approximately 0.5 V, but the input voltage
of each internal buffer must be 70 mV or more below the output low level, when the output
internally is driven low. This prevents a lock-up condition from occurring when the input low
condition is released.
As with the standard I2C system, pull up resistors are required to provide the logic high
levels on the buffered bus. The STDVE001A has standard open collector configuration of
the I2C bus. The size of the pull up resistors depends on the system, but each side of the
repeater must have a pull up resistor.
This part is designed to work with standard mode and fast mode I2C devices. Standard
mode I2C devices only specify 3 mA output drive, this limits the termination current to 3 mA
in a generic I2C system where standard mode devices and multiple masters are possible.
Under certain conditions, higher termination currents can be used.
3.6
Power-down condition
The OE_N pin can be used to disable the device. Also there is no ESD protection dode to
supply on any of the IOs. This prevents a reverse current flow condition when the main box
is switched off while the TV is switched on.
The OE_N is used to disable most of the internal circuitry of STDVE001A that puts the
device in a low power mode of operation.
17/49
Functional description
3.7
STDVE001A
Bias
The bandgap reference voltage over the external REXT reference resistor sets the internal
bias reference current. This current and its factors (achieved by employing highly accurate
and well matched current mirror circuit topologies) are generated on-chip and used by
several internal modules. The 10 mA current used by the transmitter block is also generated
using this reference current. It is important to ensure that the REXT value is within the ±1%
tolerance range of its typical value.
Table 5.
Bias parameter
Parameter
Min
Bandgap voltage
Typ
Max
1.2
Unit
V
The output voltage swing depends on 3 components: supply voltage (Vsupply), termination
resistor (RT) and current drive (Idrive). The supply voltage can vary from 3.3 V ±5%,
termination resistor can vary from 50 Ω ±10%.
The voltage on the output is given by:
Vsupply −Idrive x RT.
The variation on Idrive must be controlled to ensure that the voltage on HDMI output is within
the HDMI specification under all conditions.
This is achieved when:
400 mV ≤Idrive x RT ≤600 mV with typical value centered at 500 mV.
3.8
Timing between HPD and DDC
It is important to ensure that the I2C DDC interface is ready by the time the HPD detection is
complete.
As soon as the discovery is finished by the HPD detection, the configuration data is
exchanged between a source and sink through the I2C DDC interface. The STDVE003 Afs
DDC interface is ready for communication as soon as the power supply to the chip is
present and stable. When the desired port is enabled and the chip is out of shutdown mode,
the I2C DDC lines can be used for communication.
Thus, as soon as the HPD detection sequence is complete, the DDC interface can be
readily used. There is no delay between the HPD detection and I2C DDC interface to be
ready.
18/49
STDVE001A
3.9
Functional description
CEC
The CEC channel is a dedicated single pin bus and electrically translates to a bi-directional
buffer used to ensure that the electrical specs of the CEC are met even with high
capacitance on the single CEC line. The pull-up resistor of 26K? is integrated on either sides
of the buffer. The CEC is used for AV control of the electronic devices connected in a HDMI
cluster. The drive of the buffer is set to meet the requirements of the CEC. This is optionally
used for higher-level user functions such as automatic set-up tasks or tasks typically
associated with infrared remote control usage.
The CEC line is continuously monitored during the power-on state and is not monitored
during powered-off state. In powered off state, the CEC line should not be pulled low and it
should not affect the CEC communication between other devices. The maximum
capacitance on the CEC lines can be 7.2nF.
19/49
Maximum rating
4
STDVE001A
Maximum rating
Stressing the device above the rating listed in the “absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 6.
Absolute maximum ratings
Symbol
Parameter
VCC
VI
IO
TSTG
TL
VESD
Table 7.
20/49
Value
Unit
Supply voltage to ground
-0.5 to +4.0
V
DC input voltage (TMDS ports)
1.7 to +4.0
V
OE_N, DDC_EN, PRE, EX_BOOST1, EX_BOOST2
-0.5 to +4.0
V
SDA_INT, SCL_INT, SDA_EXT, SCL_EXT, HPD_INT,
HPD_EXT
-0.5 to +6.0
V
120
mA
-65 to +150
°C
Lead temperature (10 sec)
300
°C
Contact discharge
Electrostatic discharge voltage on all IOs as per IEC610004-2 standard
±8
kV
DC output current
Storage temperature
Thermal data
Symbol
Parameter
ΘJA
Thermal coefficient (junction-ambient)
TQFP48
QFN48
48
Unit
°C/W
STDVE001A
Maximum rating
4.1
Recommended operating conditions
4.2
DC electrical characteristics
TA = -40 to +85 °C, VCC = 3.3 V ± 5% (a)
Table 8.
Power supply characteristics
Value
Symbol
VCC
ICC
Parameter
Test condition
Supply voltage
Supply current
Unit
Min
Typ
Max
3.135
3.3
3.465
All inputs/outputs
are enabled.
Inputs are
terminated with
130
50 Ω to VCC.
V
mA
VCC = 3.465 V
Data rate =
3.4 Gbps
Table 9.
DC specifications for TMDS differential inputs
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
0
150
VTH
Differential input high
threshold
(peak-to-peak)
VCC = 3.465 V
over the entire
VCMR
VTL
Differential input low
threshold
VCC = 3.465 V
over the entire
VCMR
-150
VID
Differential input
voltage
(peak-to-peak)(1)
VCC = 3.465 V
150
1560
mV
VCC - 0.3
VCC - 0.04
V
VCMR
CIN
Common mode
voltage range
Input capacitance
IN+ or IN- to
GND
F = 1 MHz
0
3.5
mV
mV
pF
1. Differential output voltage is defined as | (OUT+ - OUT-) |.
Differential input voltage is defined as | (IN+ - IN-) |.
a. Typical parameters are measured at VCC = 3.3 V, TA = +25 °C.
21/49
Maximum rating
Table 10.
STDVE001A
DC specifications for TMDS differential ouputs
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
VOH
Single-ended high level
output voltage
VCC-10
VCC+10
mV
VOL
Single-ended low level
output voltage
VCC-600
VCC-400
mV
Single ended output
swing voltage
VCC = 3.3 V
RTERM = 50 Ω
400
500
600
mV
VOD
Differential output
voltage
(peak-to-peak)(1)
VCC = 3.3 V
RTERM = 50 Ω
800
1000
1200
mV
IOH
Differential output high
level current
0
50
µA
IOL
Differential output low
level current
8
12
mA
|ISC|
Output driver shortcircuit current
(continuous)
OUT± = GND
through a 50 Ω
resistor.
See Figure 12
12
mA
Output capacitance
OUT+ or OUTto GND when tristate
F = 1 MHz
Vswing
COUT
10
5.5
1. Differential output voltage is defined as | (OUT+ - OUT-) |. Differential input voltage is defined as | (IN+ - IN-) |
22/49
pF
STDVE001A
Table 11.
Maximum rating
DC specifications for OE_N, EQ_BOOST, EQ_BOOST2, PRE, DDC_EN inputs
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
VIH
HIGH level input voltage
High level
guaranteed
2.0
VIL
LOW level input voltage
Low level
guaranteed
-0.5
VIK
Clamp diode voltage
VCC = 3.465 V
IIN = -18 mA
-1.2
IIH
Input high current
VCC = 3.465 V
VIN = VCC
-5
+5
µA
IIL
Input low current
VCC = 3.465 V
VIN = GND
-5
+5
µA
CIN
Input capacitance
Pin to GND
F = 1 MHz
Table 12.
Symbol
RTERM
Table 13.
V
0.8
-0.8
V
V
3.5
pF
Value
Unit
Input termination resistor
Parameter
Differential input
termination resistor on
IN± channels relative to
VCC
Test condition
IIN = -10 mA
45
50
55
Ω
External reference resistor
Value
Symbol
Parameter
Test condition
Unit
Min
REXT
Table 14.
Resistor for TMDS
compliant voltage swing
range
Tolerance for
R = ±1%
Typ
Max
4.7
KΩ
DDC I/O pins
Value
Symbol
Parameter
Test condition
Unit
Min
VI(DDC)
Input voltage
GND
Typ
Max
5.3
V
23/49
Maximum rating
Table 14.
STDVE001A
DDC I/O pins
Value
Symbol
Parameter
Test condition
Unit
Min
II(leak)
CI/O
24/49
Typ
Max
VCC = 3.465 V
Input port= 5.3 V
Output port = 0.0 V
Switch is isolated
6
µA
VCC = 3.465 V
Input port = 3.3 V
Output port = 0.0 V
Switch is isolated
2
µA
Input leakage current
VI = 0 V
F = 1 MHz
Switch disabled
5
pF
VI = 0 V
F = 1 MHz
Switch enabled
9
pF
Input/output capacitance
STDVE001A
Table 15.
Maximum rating
Status pins (HPD_INT)
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
VIH
High level input voltage
VCC = 3.3 V
High level guaranteed
2.0
5.3
V
VIL
Low level input voltage
VCC = 3.3 V
Low level guaranteed
GND
0.8
V
VCC = 3.465 V
Output = 5.3 V
4
µA
VCC = 3.465 V
Output = 3.3 V
2
µA
II(leak)
Table 16.
Input leakage current
Status pins (HPD_EXT)(1)
Value
Symbol
Parameter
Test condition
Unit
Min
V
CI/O
VOL
Voltage
Typ
GND
Max
5.3
V
VI = 0 V
F = 1 MHz
Switch disabled
5
pF
VI = 0 V
F = 1 MHz
Switch enabled
9
pF
Input/output capacitance
Output low voltage
(open drain I/Os)
VCC = 3.3 V
IOL = 8 mA
0.4
V
1. Typical parameters are measured at VCC = 3.3 V, TA = +25 °C.
25/49
Maximum rating
STDVE001A
DC electrical characteristics (I2C repeater)
4.3
(TA = -40 to +85 °C, VCC = 3.3 V ± 5%, GND = 0 V; unless otherwise specified)
Table 17.
Supplies
Value
Symbol
VCC
Table 18.
Parameter
Test condition
DC supply voltage
Unit
Min
Typ
Max
3.135
3.3
3.465
V
Input/output SDA, SCL
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
VIH
High level input
voltage
0.7 VCC
5.3
V
VIL
Low level input
voltage(1)
-0.5
0.3 VCC
V
VILc
Low level input voltage
contention(1)
-0.5
0.4
V
VIK
Input clamp voltage
II = -18 mA
−
−
-1.2
V
IIL
Input current low
(SDA, SCL)
Input current low
(SDA, SCL)
−
−
1
μA
VI = 3.465 V
(SDA, SCL)
−
−
10
μA
IIH
Input current high
(SDA, SCL)
VI = 5.3 V
(SDA, SCL)
−
−
10
μA
IOL = 3 mA
0.4
V
IOL = 6 mA
0.65
V
VOL
IOH
CI
LOW-level output
voltage
Output high level
leakage current
Input capacitance
VO = 3.6 V;
driver disabled
−
−
10
μA
VO = 5.3 V;
driver disabled
−
−
10
μA
VI = 3 V or 0 V
−
6
7(2)
pF
1. VIL specification is for the first low level seen by the SDA/SCL lines. VILc is for the second and subsequent low levels seen
by the SDA/SCL lines.
2. The SCL/SDA CI is about 200 pF when VCC = 0 V. The STDVE001A should be used in applications where power is
secured to the repeater but an active bus remains on either set of the SDA/SCL pins.
26/49
STDVE001A
4.4
Maximum rating
DC electrical characteristics (CEC)
(TA = -40 to +85 °C, VCC = 3.3V ± 5%, GND=0V; unless otherwise specified)
Table 19.
DC electrical characteristics (CEC)
Value
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
3.135
3.3
3.465
V
VCC
DC supply voltage
VOL
Logic 0 output
0.0
0.6
V
VOH
Logic 1 output
2.5
3.63
V
VHL(th)
High to low input V
treshold for logic ‘0’
Vcec(‘0’)
≥ 0.8
V
VLH(th)
Low to high input V
treshold for logic ‘1’
Vcec(‘1’)
≥ 2.0
V
0.4
V
Vhys
Typical input
hysteresis(1)
Tr
Maximum rise time
(10% to 90%)
CL= 7.2 nF
250
μs
Tf
Maximum fall time
(90% to 10%)
CL= 7.2 nF
50
μs
28.6
KΩ
1.8
μA
RPU
Internal pull-up
resistor(2)
IOFF
CEC IO current in
upowered state
23.4
VCC = 0.0 V
26
1. Input hysteresis is normally supplied by the microprocessor input circuit. In this case, additional hysteresis
circuitry is not needed.
2. The internal device pull-up should be disconnected from the line when the device is powered-off.
27/49
Maximum rating
STDVE001A
Dynamic switching characteristics(b)
4.5
TA = -40 to +85 °C, VCC = 3.3 V ± 5%, RTERM = 50 Ω ± 5%, CL = 5 pF).
Typical values are at TA = +25 °C and VCC = 3.3 V.
Table 20.
Clock and data rate
Value
Symbol
Parameter
Test condition
Unit
Min
fCK
Drate
Table 21.
Clock frequency
(1/10th of the
differenttial data rate)
Typ
Max
25
Signaling rate
340
MHz
3.4
Gbps
Differential output timings
Value
Symbol
tr
tf
Parameter
Test condition
Differential data and
clock output rise/fall
times
tPLH
Differential low to high
propagation delay
tPHL
Differential high to low
propagation delay
Table 22.
Unit
Min
Typ
Max
20% to 80% of VOD
75
150
240
ps
80% to 20% of VOD
75
150
240
ps
Alternating 1 and 0 pattern
at slow and fast data rates
Measure at 50% VOD
between input to output
250
800
ps
250
800
ps
Skew times
Value
Symbol
Parameter
Test condition
Unit
Min
tSK(O)
Inter-pair channel-tochannel output skew
tSK(P)
Pulse skew
tSK(D)
Intra-pair differential
skew
tSK(CC)
b.
28/49
Output channel to
channel skew
| tPLH - tPHL |
Difference in
propagation
delay
(tPLH or tPHL)
among all output
channels
Typ
25
50
Max
100
ps
80
ps
44
ps
125
ps
The timing values in this section are tested during characterization and are guaranteed by
design and simulation. Not tested in production.
STDVE001A
Table 23.
Maximum rating
Turn-on and turn-off times
Value
Symbol
Parameter
Test condition
Unit
Min
tON
tOFF
Table 24.
Typ
Max
TMDS output enable
time
Time from
OE_N to OUT±
change from tristate to active
12
20
ns
TMDS output disable
time
Time from
OE_N to OUT±
change from
active to tristate
6
10
ns
DDC I/O pins
Value
Symbol
Parameter
Test condition
Unit
Min
Typ
Max
Refer to Section 4.6
Table 25.
Status pins (HPD_INT, HPD_EXT, OE_N)
Value
Symbol
Parameter
Test condition
Unit
Min
tPD(HPD)
Propagation delay
(from Y_HPD to the
active port of HPD)
TON/OFF
Switch time
(from port select to the
CL = 10 pF
latest valid status of
HPD)
Table 26.
CL = 10 pF,
RPU = 1 KΩ
Typ
Max
150
ns
50
ns
Jitter
Value
Symbol
Parameter
Test condition
Unit
Min
tJIT
Total jitter(1)
PRBS pattern
at 1.6 Gbps
(800 MHz)
Typ
35
Max
ps (p-p)
1. Total jitter is measured peak-to-peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been
subtracted. Input differential voltage = VID = 500 mV, PRBS random pattern at 1.65 Gbps, tr=tf=50 ps (20% to 80%). Jitter
parameter is not production-tested but guaranteed through characterization on a sample-to-sample basis.
29/49
Maximum rating
4.6
STDVE001A
Dynamic switching characteristics (I2C repeater)
TA = -40 to +85 °C, VCC = 3.3 V ± 5%.
Typical values are at TA = +25 °C and VCC = 3.3 V.
Table 27.
.
I2C repeater(1)
Value
Symbol
Parameter
Test condition
Unit
Min
fSCL
tLOW
tLOW
30/49
I2C clock frequency
Low duration on SCL pin
Typ
Max
Standard mode
100
kHz
Fast mode
400
kHz
100 KHz
See Figure 20
Voltage on line = 5V
Cmax=400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20 % time intervals
on both transitions.
4.7
μs
400 KHz
See Figure 20
Voltage on line = 5V
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20 % time intervals
on both transitions.
1.3
μs
100 KHz
See Figure 20
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20 % time intervals
on both transitions.
4.7
μs
400 KHz
See Figure 20
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20 % time intervals
on both transitions.
1.3
μs
Low duration on SCL pin
STDVE001A
Table 27.
Maximum rating
I2C repeater(1) (continued)
Value
Symbol
Parameter
Test condition
Unit
Min
tHIGH
tHIGH
tPHL
tPLH
tPHL
Typ
Max
100 KHz
See Figure 20
Voltage on line = 5 V
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20 % time intervals
on both transitions
4.0
μs
400 KHz
See Figure 20
Voltage on line = 5 V
Cmax = 400 pF, Rmax=2 K
Depends on input signal rise time.
Includes the 20 % time intervals
on both transitions
0.6
μs
100 KHz
Refer section 14.12,
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20 % time intervals
on both transitions
4.0
μs
400 KHz
See Figure 20
Voltage on line = 3.3 V,
Cmax=400 pF, Rmax = 2 K
Depends on input signal rise time.
Includes the 20 % time intervals
on both transitions
0.6
μs
High duration on SCL pin
High duration on SCL pin
Propagation delay
400 KHz
Waveform 1 (Figure 18)
Voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K
250
μs
Propagation delay
400 KHz
Waveform 1 (Figure 18)
Voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K
300
μs
Propagation delay
400 KHz
Waveform 1 (Figure 18)
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
250
ns
31/49
Maximum rating
Table 27.
STDVE001A
I2C repeater(1) (continued)
Value
Symbol
Parameter
Test condition
Unit
Min
tPLH
tPHL
tPLH
tPHL
tPLH
tf
tf
32/49
Typ
Max
Propagation delay
400 KHz
Waveform 1 (Figure 18)
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
450
ns
Propagation delay
100 KHz
Waveform 1 (Figure 18)
Voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K
250
ns
Propagation delay
100 KHz
Waveform 1 (Figure 18)
Voltage on line = 5 V,
Cmax = 400 pF, Rmax = 2 K
300
ns
Propagation delay
100 KHz
Waveform 1 (Figure 18)
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
250
ns
Propagation delay
100 KHz
Waveform 1 (Figure 18)
Voltage on line = 3.3 V,
Cmax = 400 pF, Rmax = 2 K
450
ns
400 KHz
Waveform 1 (Figure 18)(2)
Voltage on line = 5 V
Cmax = 400 pF, Rmax = 2 K
300
ns
400 KHz
Waveform 1(2)
Voltage on li ne = 3.3 V
Cmax = 400pF, Rmax = 2 K
300
ns
100 KHz
Waveform 1 (Figure 18) (2)
Voltage on line = 5 V
Cmax = 400 pF, Rmax = 2 K
300
ns
100 KHz
Waveform 1 (Figure 18)(2)
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
300
ns
Output fall time
Output fall time
STDVE001A
Table 27.
Maximum rating
I2C repeater(1) (continued)
Value
Symbol
Parameter
Test condition
Unit
Min
tr
tr
Typ
Max
400 KHz
Waveform 1 (Figure 18)(2)
Voltage on line = 5 V
Cmax = 400 pF, Rmax = 2 K
300
ns
400 KHz
Waveform 1 (Figure 18)(2)
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
300
ns
100 KHz
Waveform 1,(2)
Voltage on line = 5 V
Cmax = 400 pF, Rmax = 2 K
1000
ns
100 KHz
Waveform 1 (Figure 18)(2)
Voltage on line = 3.3 V
Cmax = 400 pF, Rmax = 2 K
1000
ns
Output rise time
Output rise time
1. All the timing values are tested during characterization and are guaranteed by design and simulation. Not tested in
production.
2. The tr transition time is specified with maximum load of 2 kΩ pull-up resistance and 400 pF load capacitance. Different load
resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times.
Refer to Figure 10.
Table 28.
ESD performance
Symbol
ESD
Parameter
All I/Os
Test conditions
Contact discharge
as per IEC61000-4-2 standard
Min
Typ
8
Max
Unit
kV
33/49
Maximum rating
STDVE001A
Figure 8.
Test circuit for electrical characteristics
VCC
CL
VOUT+
VIN+
Pulse
generator
VINRT
STDVE001A
100 Ω
VOUT-
RT
CL
AM00726V1
1. CL = load capacitance: include jig and probe capacitance.
2. RT = termination resistance; should be equal to ZOUT of the pulse generator.
Figure 9.
TMDS output driver
VCC
RT
RT
ZO = RT
TMDS
driver
ZO = RT
TMDS
receiver
CS00069
1. ZO = characteristic impedance of the cable.
2. RT = termination resistance: should be equal to ZO of the cable. Both are equal to 50W.
34/49
STDVE001A
Maximum rating
Figure 10. Test circuit for HDMI receiver and driver
VCC
RT
RT
A
VA
RT
Y
VID
TMDS
receiver
TMDS
driver
CL =
0.5pF
VCC
VY
B
Z
VB
VID = VA - VB
VSwing = VY - VZ
VZ
RT
CS00071
1. RT = 50 Ω.
35/49
Maximum rating
STDVE001A
Figure 11. Test circuit for turn off and turn off times
10μF
0.1 μF 0.01μF
CL
1.15 V
VCC
VIN+
1.0 V
50 Ω
1.2 V
50 Ω
STDVE001A
1.15 V
VIN1.0 V
SHDN_N
CL
REXT
Pulse
generator
GND
4.7 KΩ±1%
50 Ω
AM00727V1
1. CL = 5 pF
Figure 12. Test circuit for short circuit output current
50 Ω
ISC
TMDS
driver
50 Ω
0V or 3.465 V
36/49
STDVE001A
Maximum rating
Figure 13. Propagation delays
VCC
VA
VCM
VID
VCM
VB
VCC – 0.4
0.4V
VID
VID
VID(p-p)
0V
-0.4V
VOD(O)
tpLH
tpHL
100%
80%
VOD(p-p)
80%
0V Differential
20%
20%
Output
0%
VOD(U)
tr
tf
Figure 14. Turn-on and turn-off times
SHDN_N
3.0 V
1.50 V
1.50 V
0V
tOFF
tON
VOH
VOUT+ when VID= +150mV
VOUT- when VID= -150mV
50%
50%
1.2 V
tON
tOFF
1.2 V
VOUT+ when VID= -150mV
VOUT- when VID= +150mV
50%
50%
VOL
37/49
Maximum rating
STDVE001A
Figure 15. TSK(O)
3.5V
2.5V
Data In
1.5V
tpLHX
tpHLX
VOH
2.5V
2.5V
Data Out at Port 0
VOL
tSK(o)
VOH
2.5V
Data Out at Port 1
VOL
tpLHY
tpHLY
tSK(o) = | tpLHy – tpLHx | or | tpHLy – tpHLx |
Figure 16. TSK(P)
Figure 17. TSK(D)
38/49
STDVE001A
Maximum rating
Figure 18. AC waveform 1 (I2C lines)
Figure 19. Test circuit for AC measurements (I2C lines)
Figure 20. I2C bus timing
39/49
Application information
5
Application information
5.1
Power supply sequencing
STDVE001A
Proper power-supply sequencing is advised for all CMOS devices. It is recommended to
always apply VCC before applying any signals to the input/output or control pins.
5.2
Power supply requirements
Bypass each of the VCC pins with 0.1 μF and 1 nF capacitors in parallel as close to the
device as possible, with the smaller-valued capacitor as close to the VCC pin of the device as
possible.
All VCC pins can be tied to a single 3.3 V power source. A 0.01 μF capacitor is connected
from each VCC pin directly to ground to filter supply noise. The maximum power supply
variation can only be ±5% as per the HDMI specifications.
The maximum tolerable noise ripple on 3.3 V supply must be within a specified limit.
5.3
Differential traces
The high-speed TMDS inputs are the most critical parts for the device. There are several
considera-tions to minimize discontinuities on these transmission lines between the
connectors and the device.
(a) Maintain 100-Ω differential transmission line impedance into and out of the STDVE001A.
(b) Keep an uninterrupted ground plane below the high-speed I/Os.
(c) Keep the ground-path vias to the device as close as possible to allow the shortest return
current path.
(d) Layout of the TMDS differential inputs should be with the shortest stubs from the
connectors.
Output trace characteristics affect the performance of the STDVE001A. Use controlled
impedance traces to match trace impedance to both the transmission medium impedance
and termination resistor. Run the differential traces close together to minimize the effects of
the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities
in the differential trace layout. Avoid 90 degree turns and minimize the number of vias to
further prevent impedance discontinuities.
40/49
STDVE001A
5.3.1
Application information
I2C lines application information
A typical application is shown in the figure below. In the example, the system master is
running on a 3.3 V I2C-bus while the slave is connected to a 5 V bus. Both buses run at
100 kHz unless the slave bus is isolated and then the master bus can run at 400 kHz.
Master devices can be placed on either bus.
Figure 21. Typical application of I2C bus system
3.3V
5.0V
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
Bus master
400 kHz
Slave
100 kHz
STDVE 001 A
BUS 0
BUS 1
The STDVE001A DDC lines are 5 V tolerant; so it does not require any extra circuitry to
translate between the different bus voltages.
41/49
Package mechanical data
6
STDVE001A
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 22. TQFP48 (7 x 7 mm) package outline
42/49
STDVE001A
Package mechanical data
Table 29.
TQFP48 (7 x 7 mm) mechanical data
Millimeters
Symbol
Min
Typ
Max
A1
0.05
0.10
0.15
A2
0.95
1.00
1.05
D
8.80
9.00
9.20
D1
6.90
7.00
7.10
E
8.80
9.00
9.20
E1
6.90
7.00
7.10
L
0.45
0.60
0.75
A
L1
1.00
T
0.70
0.15
0.20
T1
0.10
0.13
1.15
a
0°
b
0.17
0.22
0.27
b1
0.17
0.20
0.23
7°
e
0.500
ccc / ddd
0.08
43/49
Package mechanical data
Figure 23. TQFP48 (7 x 7 mm) footprint recommendation
44/49
STDVE001A
STDVE001A
Package mechanical data
Figure 24. TQFP48 (7 x 7 mm) tape and reel information
45/49
Package mechanical data
Figure 25. QFN48 (7 x 7 mm) package outline
46/49
STDVE001A
STDVE001A
Package mechanical data
Table 30.
QFN48 (7 x 7 mm) package mechanical data
Millimeters
Symbol
Min
Typ
Max
0.80
0.90
1.00
A1
0.02
0.05
A2
0.65
1.00
A3
0.25
A
b
0.18
0.23
0.30
D
6.85
7.00
7.15
D2
2.25
4.70
5.25
E
6.85
7.00
7.15
E2
2.25
4.70
5.25
e
0.45
0.50
0.55
L
0.30
0.40
0.50
ddd
0.08
47/49
Revision history
7
STDVE001A
Revision history
Table 31.
48/49
Document revision history
Date
Revision
Changes
02-Jul-2008
1
Initial release.
21-Jul-2008
2
Modified: Figure 2 and Section 3: Functional description on page 13
Replaced ‘equation’ with ‘equalizer in the Features section.
STDVE001A
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49/49