STMICROELECTRONICS STE180NE10_07

STE180NE10
N-channel 100V - 4.5mΩ - 180A - ISOTOP
STripFET™ Power MOSFET
General features
Type
VDSS
RDS(on)
ID
STE180NE10
100V
<6mΩ
180A
■
100% avalanche tested
■
Low intrinsic capacitance
■
Gate charge minimized
■
Reduced voltage spread
ISOTOP
Description
This Power MOSFET is the latest development of
STMicroelectronics unique "Single Feature
Size™" strip-based process. The resulting
transistor shows extremely high packing density
for low on-resistance, rugged avalanche
characteristics and less critical alignment steps
therefore a remarkable manufacturing
reproducibility.
Internal schematic diagram
Applications
■
Switching application
Order codes
Part number
Marking
Package
Packaging
STE180NE10
E180NE10
ISOTOP
Tube
February 2007
Rev 6
1/12
www.st.com
12
Contents
STE180NE10
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................. 6
3
Test circuit
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
................................................ 8
STE180NE10
1
Electrical ratings
Electrical ratings
Table 1.
Symbol
Absolute maximum ratings
Value
Unit
Drain-source voltage (VGS = 0)
100
V
Drain-gate voltage (RGS = 20kΩ)
100
V
Gate-source voltage
± 20
V
ID
Drain current (continuous) at TC = 25°C
180
A
ID
Drain current (continuous) at
TC = 100°C
119
A
IDM (1)
Drain current (pulsed)
360
A
PTOT
Total dissipation at TC = 25°C
360
W
Derating factor
2.88
W/°C
VISO
Insulation withstand voltage (AC-RMS)
2500
V
Tj
Tstg
Operating junction temperature
storage temperature
-55 to 150
°C
VDS
VDGR
VGS
Parameter
1. Pulse width limited by safe operating area
Table 2.
Rthj-case
Table 3.
Symbol
Thermal data
Thermal resistance junction-case max
0.37
°C/W
Avalanche characteristics
Parameter
Max value
Unit
IAR
Avalanche Current, Repetitive or NotRepetitive
(pulse width limited by Tj max)
60
A
EAS
Single Pulse Avalanche Energy
(starting Tj = 25 °C, ID = IAR,
VDD = 25 V)
720
mJ
3/12
Electrical characteristics
2
STE180NE10
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 4.
On/off states
Symbol
Parameter
V(BR)DSS
Drain-source
breakdown voltage
ID =1mA, VGS =0
IDSS
Zero gate voltage
drain current (VGS = 0)
VDS = max rating
VDS = max rating,
TC = 125°C
IGSS
Gate-body leakage
current (VDS = 0)
VGS = ± 20V
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250µA
RDS(on)
Static drain-source on
resistance
VGS = 10V, ID = 40A
Table 5.
Symbol
Test conditions
Typ.
Max.
100
2
Unit
V
4
40
µA
µA
±400
nA
3
4
V
4.5
6
Ω
Typ.
Max.
Unit
Dynamic
Parameter
Test conditions
Min.
gfs (1)
Forward
transconductance
VDS>ID(on)xRDS(on)max
ID=80 A
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 25V, f = 1MHz,
VGS = 0
21
2.5
0.9
nF
nF
nF
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
VDD = 90V, ID = 490A
RG = 4.7Ω VGS = 10V
(see Figure 12)
100
600
430
440
ns
ns
ns
ns
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 80V, ID = 180A,
VGS = 10V, RG = 4.7Ω
(see Figure 13)
585
120
210
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%.
4/12
Min.
30
S
795
nC
nC
nC
STE180NE10
Electrical characteristics
Table 6.
Symbol
Source drain diode
Parameter
ISDM (1)
Source-drain current
Source-drain current
(pulsed)
VSD (2)
Forward on voltage
ISD
trr
Qrr
IRRM
Test conditions
Min.
Typ.
ISD = 180A, VGS = 0
ISD = 100A,
Reverse recovery time
di/dt = 100A/µs,
Reverse recovery charge
VDD = 50V, Tj = 150°C
Reverse recovery current
(see Figure 14)
235
1.65
14
Max.
Unit
180
540
A
A
1.5
V
ns
µC
A
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
5/12
Electrical characteristics
STE180NE10
2.1
Electrical characteristics (curves)
Figure 1.
Safe operating area
Figure 2.
Thermal impedance
Figure 3.
Output characteristics
Figure 4.
Transfer characteristics
Figure 5.
Transconductance
Figure 6.
Static drain-source on resistance
6/12
STE180NE10
Electrical characteristics
Figure 7.
Gate charge vs. gate-source voltage Figure 8.
Figure 9.
Normalized gate threshold voltage
vs. temperature
Capacitance variations
Figure 10. Normalized on resistance vs.
temperature
Figure 11. Source-drain diode forward
characteristics
7/12
Test circuit
3
STE180NE10
Test circuit
Figure 12. Switching times test circuit for
resistive load
Figure 13. Gate charge test circuit
Figure 14. Test circuit for inductive load
Figure 15. Unclamped Inductive load test
switching and diode recovery times
circuit
Figure 16. Unclamped inductive waveform
8/12
Figure 17. Switching time waveform
STE180NE10
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
9/12
Package mechanical data
STE180NE10
ISOTOP MECHANICAL DATA
mm
DIM.
MIN.
A
TYP.
11.8
inch
MAX.
MIN.
12.2
0.466
TYP.
MAX.
0.480
B
8.9
9.1
0.350
0.358
C
1.95
2.05
0.076
0.080
D
0.75
0.85
0.029
0.033
E
12.6
12.8
0.496
0.503
F
25.15
25.5
0.990
1.003
G
31.5
31.7
1.240
1.248
H
4
J
4.1
4.3
0.161
0.157
0.169
K
14.9
15.1
0.586
0.594
L
30.1
30.3
1.185
1.193
M
37.8
38.2
1.488
1.503
N
4
O
7.8
0.157
8.2
0.307
0.322
A
G
B
O
H
J
K
L
M
10/12
C
F
E
D
N
STE180NE10
5
Revision history
Revision history
Table 7.
Revision history
Date
Revision
Changes
09-Sep-2004
4
Complete document
03-Aug-2006
5
New template, no content change
20-Feb-2007
6
Typo mistake on page 1
11/12
STE180NE10
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