STMICROELECTRONICS STM7E1AR

STM7E1
7 e 1 channels switch array
Features
■
Main switches max. RON less than 2 Ω
■
Provides 7 auxiliary switches with RON < 75 Ω
■
6 VPP amplitude of analog input signal
■
Digital inputs are TTL levels compatible
Description
The STM7E1A consists of 7 identical ISDN E1
channels, each channel corresponding to 4 main
low-resistant switches (a and b) and 2 auxiliary
switches (c and d). The switches positions in all
the channels are identical and controlled by a
unique control resource driven by the digital
inputs Lm, Ls and Sc.
In each channel, the TX and RX lines can be
switched between a Main port or a Spare-port by
the main switches: if both "a" switches are closed
and both "b" switches are open, the Main port is
connected to the line, while if both "a" switches
are open and both "b' switches are closed, the
spare port is connected to the line.
TQFP64
The power supplies of the chip need to be de
coupled properly. This means that at least one
external capacitor C1 must be connected in
between GND and VPOS, one external capacitor
C2 between GND and VNEG, and one external
capacitor C3 between each pair of VNEG and
VPOS.
The 2 auxiliary switches enable to close a local
loop between the TX and RX access of a port: if
"c" is closed, the Spare port RX and TX access is
connected between each other to form a local
loop, while if "d" is closed, the Main port RX and
TX access is connected between each other to
form a local loop.
The Spare port is only used for test purpose on
the system board while the Main port is the
communication channel. Consequently, a
switching from the Main port to the Spare port
occurs very rarely (<10 times a day).
Table 1.
Device summary
Order code
Temperature range
Package
Packaging
STM7E1AR
-40 to 85 °C
TQFP64 (tape and reel)
1000 parts per reel
November 2007
Rev 3
1/16
www.st.com
16
Contents
STM7E1
Contents
1
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Test mode description (mode = 0, test = 1) . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/16
STM7E1
Application circuit
1
Application circuit
Figure 1.
Typical operating circuit
MODE
Sc
Ls
Lm
TEST/Sn
Control Decoding
Level Shifting & Buffering
a
Tx#0
CHANNEL 0
Txm#0
b
Txs#0
c
a
Rx#0
Rxm#0
b
Rxs#0
CHANNEL 1
Txm#1
Txs#1
Rxm#1
Rxs#1
CHANNEL 6
Txm#6
Txs#6
Rxm#6
Rxs#6
Tx#1
Rx#1
Tx#6
Rx#6
VNEG
d
GND
VPOS
3/16
Application circuit
Table 2.
STM7E1
Decoding of functional Mode 1 (Mode = L)
Switches
Status
Description
Sc low
a closed, b open
Main port is connected to the line
Sc high
a open, b closed
Spare port is connected to the line
Lm low
d open
Lm high
d closed
Main port local loop closed
Ls low
c open
Spare port local loop open
Ls high
c closed
Main
Main port local loop open
Auxiliary
Spare port local loop closed
When closing the main port local loop (Lm high), it is external system responsibility to
ensure that the main port has previously been disconnected from the line (Sc has to be
high). There is no internal mechanism to ensure this.
When closing the spare port local loop (Ls high), it is external system responsibility to
ensure that the spare port has previously been disconnected from the line (Sc has to be
high). There is no internal mechanism to ensure this.
Table 3.
Decoding of functional Mode 2 (Mode = H)
Input
Outputs
TEST/Sn
A_TX
B_TX
L
O
C
H
C
O
C = Closed
O = Open
Table 4.
Decoding of functional Mode 2 (Mode = H)
Inputs
Sc
Lm
Ls
A_RX
B_RX
c
d
L
L
L
C
C
O
O
L
L
H
C
O
C
O
L
H
L
O
C
O
C
L
H
H
C
O
O
O
H
L
L
O
C
O
O
C = Closed
O = Open
4/16
Outputs
STM7E1
1.1
Application circuit
Test mode description (mode = 0, test = 1)
In order to test the main switches (4-point measurement), test modes are foreseen where
the main switches can be controlled independently from each other. One can enter in test
mode by controlling the Sc, Lm and Ls pins according to the following table.
The digital part and auxiliary switches can be tested in functional mode
Table 5.
Test mode
Signification
Sc
Lm
Ls
A_TX closed
H
H
L
A_RX closed
L
H
L
B_TX closed
H
L
H
B_RX closed
L
L
H
B_TX & c closed
H
L
L
A_RX & d closed
L
L
L
H
H
H
L
H
H
All main switches open
Note:
Although there is an internal pull down in the TEST pin, an external hardware connection
from TEST to GND is required on the board to work in functional, mode.
5/16
Pin configuration
STM7E1
2
Pin configuration
Figure 2.
Pin configuration
Table 6.
Pin description
Pin n°
Symbol
Type
1, 17, 33, 47
VNEG(1)
P
2
Txm#2
IOA
Channel 2: TX main port
3
Tx#2
IOA
Channel 2: TX line
4
Txs#2
IOA
Channel 2: TX spare port
5, 12, 21, 25, 29, 38,
52, 56, 60
GND
G
6
Rxm#3
IOA
Channel 3: RX main port
7
Rx#3
IOA
Channel 3: RX line
8
Rxs#3
IOA
Channel 3: RX spare port
9
Txm#3
IOA
Channel 3: TX main port
6/16
Name and function
Negative power supply
Voltage reference for digital inputs
STM7E1
Pin configuration
Table 6.
Pin description (continued)
Pin n°
Symbol
Type
Name and function
10
Tx#3
IOA
Channel 3: TX line
11
Txs#3
IOA
Channel 3: TX spare port
13
Rxm#4
IOA
Channel 4: RX main port
14
Rx#4
IOA
Channel 4: RX line
15
Rxs#4
IOA
Channel 4: RX spare port
16, 34, 48, 64
VPOS(2)
P
18
Txm#4
IOA
Channel 4: TX main port
19
Tx#4
IOA
Channel 4: TX line
20
Txs#4
IOA
Channel 4: TX spare port
22
Rxm#5
IOA
Channel 5: RX main port
23
Rx#5
IOA
Channel 5: RX line
24
Rxs#5
IOA
Channel 5: RX spare port
26
Txm#5
IOA
Channel 5: TX main port
27
Tx#5
IOA
Channel 5: TX line
28
Txs#5
IOA
Channel 5: TX spare port
30
Rxm#6
IOA
Channel 6: RX main port
31
Rx#6
IOA
Channel 6: RX line
32
Rxs#6
IOA
Channel 6: RX spare port
35
Sc
I
Control digital input
36
Ls
I
Control digital input
37
Lm
I
Control digital input
39
Txm#6
IOA
Channel 6: TX main port
40
Tx#6
IOA
Channel 6: TX line
41
Txs#6
IOA
Channel 6: TX spare port
42
Mode
I
43
Rxm#0
IOA
Channel 0: RX main port
44
Rx#0
IOA
Channel 0: RX line
45
Rxs#0
IOA
Channel 0: RX spare port
46
TEST/Sn
I
Channel 6: RX main port
49
Txm#0
IOA
Channel 0: TX main port
50
Tx#0
IOA
Channel 0: TX line
51
Txs#0
IOA
Channel 0: TX spare port
53
Rxm#1
IOA
Channel 1: RX main port
54
Rx#1
IOA
Channel 1: RX line
55
Rxs#1
IOA
Channel 1: RX spare port
57
Txm#1
IOA
Channel 1: TX main port
Positive power supply
Control Digital Input
7/16
Pin configuration
Table 6.
Note:
8/16
STM7E1
Pin description (continued)
Pin n°
Symbol
Type
Name and function
58
Tx#1
IOA
Channel 1: TX line
59
Txs#1
IOA
Channel 1: TX spare port
61
Rxm#2
IOA
Channel 2: RX main port
62
Rx#2
IOA
Channel 2: RX line
63
Rxs#2
IOA
Channel 2: RX spare port
1
All VNEG pins to be connected together on board.
2
All VPOS pins to be connected together on board.
STM7E1
Maximum ratings
3
Maximum ratings
Table 7.
Absolute maximum ratings
Symbol
Description
Min.
Max.
Unit
VPOS
Positive power supply voltage
VNEG - 0.3
VNEG + 7
V
GND
Reference ground
VNEG - 0.3
VNEG + 7
V
Input voltage for digital inputs and analog input/output
pins
VNEG - 0.3
VNEG + 7
V
VIN
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these condition is not implied.
Table 8.
Recommended operating conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VPOS
Positive power supply voltage
3.3 - 5%
3.3 + 5%
V
VNEG
Negative power supply voltage
-3.3 - 5%
-3.3 + 5%
V
Tamb
Ambient temperature
-25
85
°C
TJ
Junction temperature
-25
120
°C
Admissible peak current in 1 switch
300
mA
Load capacitance on ASIC output
70
pF
Ipeak,
switch
CIa
Table 9.
Digital part specifications
Value
Symbol
Parameter
Unit
Min.
Typ.
Max.
VIL
Low input level
0
0.8
V
VIH
HigH input level
2
VPOS
V
VIT
Low-high switching threshold voltage
Ileak
Input leakage current
1.6
-3
V
3
A
9/16
Maximum ratings
Table 10.
STM7E1
Analog part specifications
Value
Symbol
Parameter
Test condition
Unit
Min.
Typ.
Max.
RON(main)(1)
On-resistance of the main
switches
1.6
2
Ω
RON(aux)(1)
On-resistance of the
auxiliary switches
50
75
Ω
ΔRON(main)(1)
Difference of RON between
VIN = 2V, TA = 25°C
devices
0.5
ΔRON(main)(1)
Difference of RON between
switches of the same
VIN = 2V, TA = 25°C
device
Ω
0.8
Ω
ROFF(1,2)
Off-resistance of the main
and auxiliary switches
CON(3)
Capacitance at any switch
pin, switch ON
120
pF
COFF(3)
Capacitance at any switch
pin, switch OFF
40
pF
Apeak,signal(1)
fsignal(1,4)
100
Peak amplitude of the
signal at switch pins
-3
3
Vp
Frequency of the signal at
switch pins (3dB
bandwidth)
50
12000
kHz
4
8
mVrms
0.15
1
µs
Cross-talk(1,5) Cross-talk between lines
Switch time of the main
switches (a and b)
t
Note:
10/16
kΩ
1
All the parameters are valid only with a 75Ω (5%) load to GND.
2
Measured with a 5 V DC voltage applied to a closed switch.
3
Not tested in production.
4
Measured with a 2 VPP signal.
5
Measured with the line connected to GND at one side with a 75 Ω resistor and all the other
lines driven by a 1 MHz, 2 VPP sine wave signal.
6
During the switching between the main and spare ports, the behavior of the component is
not guaranteed: both main switches can be open (break before make).
7
Measured with the line switching from a 2.5 V DC level (main or spare port) to a -2.5 V DC
level (spare or main port).
STM7E1
Table 11.
Maximum ratings
Current consumption specifications
Value
Symbol
Parameter
Unit
Min.
Typ.
Max.
Pmain(1)
Maximal average power dissipation in the main
switches
40
mW
Paux(1)
Maximal average power dissipation in the auxiliary
switches
150
mW
ISTDBY(VNEG)(1,3)
Standby (no switching) current of VNEG
-500
500
µA
ISTDBY(VPOS)(1,3)
Standby (no switching) current of VPOS
-500
500
µA
ESWITCH(VNEG)(1)
Energy to be delivered to by VPOS when switching
-100
100
nJ
ESWITCH(VPOS)(1)
Energy to be delivered to by VPOS when switching
-100
100
nJ
Note:
1
These parameters are not tested in production.
2
This power is not delivered by VPOS and VNEG supplies but by the signal sources.
3
Only valid with digital inputs to GND or VPOS levels.
11/16
Package mechanical data
4
STM7E1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
12/16
STM7E1
Package mechanical data
TQFP64 mechanical data
mm.
inch.
Dim.
Min.
Typ.
Max.
A
Min.
Typ.
Max.
1.6
A1
0.05
A2
1.35
B
0.17
C
0.09
D
11.80
D1
9.80
D3
0.063
0.15
0.002
0.006
1.40
1.45
0.053
0.055
0.057
0.22
0.27
0.007
0.009
0.011
0.20
0.004
12.00
12.20
0.465
0.472
0.480
10.00
10.20
0.386
0.394
0.402
0.008
7.50
0.295
E
11.80
12.00
12.20
0.465
0.472
0.480
E1
9.80
10.00
10.20
0.386
0.394
0.402
E3
7.50
0.295
e
0.50
0.020
L
0.45
0.60
L1
0.75
0.018
0.024
1.00
K
0°
0.030
0.039
3.5°
7°
0°
3.5°
7°
A
D
A2
D1
A1
D3
33
48
0.10mm
32
49
.004
E
E1
64
17
L
L1
E3
B
Seating Plane
K
1
e
16
C
0051434/E
13/16
Package mechanical data
STM7E1
Tape & reel TQFP64 mechanical data
mm.
inch.
Dim.
Min.
A
Max.
Min.
330
13.2
Typ.
Max.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
14/16
Typ.
0.504
30.4
0.519
1.196
Ao
12.25
12.45
0482
0.490
Bo
12.25
12.45
0482
0.490
Ko
2.1
2.3
0.083
0.091
Po
3.9
4.1
0.153
0.161
P
15.9
16.1
0.626
0.639
STM7E1
Revision history
5
Revision history
Table 12.
Document revision history
Date
Revision
22-Jun-2004
2
15-Nov-2007
3
Changes
Added Table 1.
15/16
STM7E1
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16/16