STMICROELECTRONICS STM802

STM690A, STM692A, STM703
STM704, STM802, STM805, STM817/8/9
5V Supervisor with Battery Switchover
FEATURES SUMMARY
■
■
■
■
■
■
■
■
■
■
■
■
■
5V OPERATING VOLTAGE
NVRAM SUPERVISOR FOR EXTERNAL
LPSRAM
CHIP-ENABLE GATING (STM818 only) FOR
EXTERNAL LPSRAM (7ns max PROP
DELAY)
RST AND RST OUTPUTS
200ms (TYP) trec
WATCHDOG TIMER - 1.6sec (TYP)
AUTOMATIC BATTERY SWITCHOVER
LOW BATTERY SUPPLY CURRENT - 0.4µA
(TYP)
POWER-FAIL COMPARATOR (PFI/PFO)
LOW SUPPLY CURRENT - 40µA (TYP)
GUARANTEED RST (RST) ASSERTION
DOWN TO VCC = 1.0V
OPERATING TEMPERATURE:
–40°C to 85°C (Industrial Grade)
RoHS COMPLIANCE
Lead-free components are compliant with the
RoHS Directive.
Figure 1. Packages
8
1
SO8 (M)
TSSOP8 3x3 (DS)*
Table 1. Device Options
Watchdog
Input
ActiveLow
RST(1)
STM690A
✔
STM692A
✔
ActiveHigh
RST(1)
Manual
Reset
Input
Battery
Switchover
Power-fail
Comparator
✔
✔
✔
✔
✔
✔
STM703
✔
✔
✔
✔
STM704
✔
✔
✔
✔
✔
✔
✔
✔
✔
STM802L/M
✔
STM805L
✔
STM817L/M
✔
✔
✔
STM818L/M
✔
✔
✔
STM819L/M
✔
✔
✔
✔
✔
ChipEnable
Gating
✔
✔
✔
Battery
Freshness
Seal
✔
✔
Note: 1. All RST and RST outputs are push-pull.
* Contact local ST sales office for availability.
Rev 7.0
January 2006
1/37
STM690A/692A/703/704/802/805/817/818/819
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram (STM690A/692A/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram (STM703/704/819). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Logic Diagram (STM818). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 5. STM690A/692A/802/805/817 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. STM703/704/819 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 7. STM818 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 8. Block Diagram (STM690A/692A/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 9. Block Diagram (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 10.Block Diagram (STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 11.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Push-button Reset Input (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Watchdog Input (NOT available on STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Back-up Battery Switchover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. I/O Status in Battery Back-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip-Enable Gating (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable Input (STM818 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable Output (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12.Chip-Enable Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 13.Chip Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-fail Input/Output (NOT available on STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14.Power-fail Comparator Waveform (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15.Power-fail Comparator Waveform (STM690A/692A/703/704/802/805) . . . . . . . . . . . . . 13
Using a SuperCap™ as a Backup Power Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Negative-Going VCC Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Battery Freshness Seal (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16.Using a SuperCap™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17.Freshness Seal Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 18.VCC-to-VOUT On-Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 19.VBAT-to-VOUT On-Resistance vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/37
STM690A/692A/703/704/802/805/817/818/819
Figure 20.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 21.Battery Current vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 22.VPFI Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 23.Reset Comparator Propagation Delay vs. Temperature (Other than STM817/818/819) 17
Figure 24.Reset Comparator Propagation Delay vs. Temperature (VBAT=3.0V; STM817/818/819)18
Figure 25.Power-up trec vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 28.E to ECON On-Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 29.PFI to PFO Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 30.Output Voltage vs. Load Current (VCC = 5V; VBAT = 2.8V; TA = 25°C). . . . . . . . . . . . . . 21
Figure 31.Output Voltage vs. Load Current (VCC = 0V; VBAT = 2.8V; TA = 25°C). . . . . . . . . . . . . . 21
Figure 32.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 33.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 34.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 35.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 36.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 37.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 38.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . . 25
Figure 39.E to ECON Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . .
Figure 40.E to ECON Propagation Delay Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . .
Figure 41.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 42.MR Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 43.Watchdog Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7. DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
......
......
......
......
......
......
. . . . 27
. . . . 28
. . . . 28
. . . . 28
. . . . 28
. . . . 29
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 44.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing. . . . 32
Table 8. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . . 32
Figure 45.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . . 33
Table 9. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data . . . . 33
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 11. Marking Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3/37
STM690A/692A/703/704/802/805/817/818/819
SUMMARY DESCRIPTION
The STM690A/692A/703/704/802/805/817/818/
819 Supervisors are self-contained devices which
provide microprocessor supervisory functions with
the ability to non-volatize and write-protect external LPSRAM. A precision voltage reference and
comparator monitors the VCC input for an out-oftolerance condition. When an invalid VCC condition occurs, the reset output (RST) is forced low
(or high in the case of RST). These devices also
offer a watchdog timer (except for STM703/704/
819) as well as a power-fail comparator (except for
STM818) to provide the system with an early
warning of impending power failure.
These devices are available in a standard 8-pin
SOIC package or a space-saving 8-pin TSSOP
package.
Figure 2. Logic Diagram (STM690A/692A/802/
805/817)
Figure 4. Logic Diagram (STM818)
VCC VBAT
VCC VBAT
VOUT
VOUT
WDI
PFI
STM690A/
692A/802/
805/817
WDI
STM818
RST(RST)(1)
RST
E
ECON
PFO
VSS
VSS
Table 2. Signal Names
Note: 1. For STM805, reset output is active-high.
MR
Push-button Reset Input
WDI
Watchdog Input
RST
Active-Low Reset Output
RST
Active-High Reset Output
VOUT
E(1)
Chip Enable Input
RST
ECON(1)
PFO
VOUT
Supply Voltage Output
VCC
Supply Voltage
VBAT
Back-up Supply Voltage
PFI
Power-fail Input
PFO
Power-fail Output
VSS
Ground
Figure 3. Logic Diagram (STM703/704/819)
VCC VBAT
MR
PFI
STM703/
704/819
VSS
Conditioned Chip Enable Output
AI07895
Note: 1. STM818
4/37
AI07896
AI07894
STM690A/692A/703/704/802/805/817/818/819
Figure 5. STM690A/692A/802/805/817
Connections
Figure 6. STM703/704/819 Connections
SO8/TSSOP8
SO8/TSSOP8
VOUT
VCC
VSS
PFI
1
2
3
4
8
7
6
5
VBAT
RST(RST)(1)
WDI
PFO
VOUT
VCC
VSS
PFI
1
2
3
4
VBAT
8
7
6
5
RST
MR
PFO
AI07890
AI07889
Note: 1. For STM805, reset output is active-high.
Figure 7. STM818 Connections
SO8/TSSOP8
VOUT
VCC
VSS
E
1
2
3
4
8
7
6
5
VBAT
RST
WDI
ECON
AI07892
5/37
STM690A/692A/703/704/802/805/817/818/819
Pin Descriptions
MR. A logic low on /MR asserts the reset output.
Reset remains asserted as long as MR is low and
for trec after MR returns high. This active-low input
has an internal pull-up. It can be driven from a TTL
or CMOS logic line, or shorted to ground with a
switch. Leave open if unused.
WDI. If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and reset is triggered. The internal watchdog timer clears while
reset is asserted or when WDI sees a rising or falling edge.
The watchdog function can be disabled by allowing the WDI pin to float.
RST. Pulses low for trec when triggered, and stays
low whenever VCC is below the reset threshold or
when MR is a logic low. It remains low for trec after
either VCC rises above the reset threshold, the
watchdog triggers a reset, or MR goes from low to
high.
RST. Pulses high for trec when triggered, and
stays high whenever VCC is above the reset
threshold or when MR is a logic high. It remains
high for trec after either VCC falls below the reset
threshold, the watchdog triggers a reset, or MR
goes from high to low.
VOUT. When VCC is above the switchover voltage
(VSO), VOUT is connected to VCC through a Pchannel MOSFET switch. When VCC falls below
VSO, VBAT connects to VOUT. Connect to VCC if no
battery is used.
VBAT. When VCC falls below VSO, VOUT switches
from VCC to VBAT. When VCC rises above VSO +
hysteresis, VOUT reconnects to VCC. VBAT may exceed VCC. Connect to VCC if no battery is used.
E. The input to the chip-enable gating circuit. Connect to ground if unused.
ECON. ECON goes low only when E is low and reset is not asserted. If ECON is low when reset is asserted, ECON will remain low for 15µs or until E
goes high, whichever occurs first. In the disabled
mode, ECON is pulled up to VOUT.
PFI. When PFI is less than VPFI or when VCC falls
below 2.4V (or VSO), PFO goes low; otherwise,
PFO remains high. Connect to ground if unused.
PFO. When PFI is less than VPFI, or VCC falls below 2.4V (or VSO), PFO goes low; otherwise, PFO
remains high. Leave open if unused.
Table 3. Pin Description
Pin
Function
–
6
7
–
1
2
2
2
2
VCC
Supply Voltage
8
4
5
8
–
–
8
–
–
8
–
–
VBAT
E
ECON
–
–
3
4
5
3
4
5
3
4
5
3
PFI
PFO
VSS
Backup-Battery Input
Chip Enable Input
Conditioned Chip Enable Output
PFI Power-fail Input
PFO Power-fail Output
Ground
STM818
6/37
Name
STM690A
STM692A
STM802
STM817
–
6
7
–
1
STM703
STM704
STM819
STM805
6
–
7
–
1
–
6
–
7
1
MR
WDI
RST
RST
VOUT
Push-button Reset Input
Watchdog Input
Active-Low Reset Output
Active-High Reset Output
Supply Output for External LPSRAM
STM690A/692A/703/704/802/805/817/818/819
Figure 8. Block Diagram (STM690A/692A/802/805/817)
VCC
VOUT
VBAT
VSO
COMPARE
VRST
COMPARE
WATCHDOG
TIMER
WDI
PFI
VPFI
trec
Generator
COMPARE
RST(RST)(1)
PFO
AI07897
Note: 1. For STM805, reset output is active-high.
Figure 9. Block Diagram (STM703/704/819)
VCC
VOUT
VBAT
VSO
COMPARE
VRST
COMPARE
trec
Generator
MR
PFI
VPFI
COMPARE
RST
PFO
AI07898
7/37
STM690A/692A/703/704/802/805/817/818/819
Figure 10. Block Diagram (STM818)
VCC
VOUT
VBAT
VSO
COMPARE
VRST
COMPARE
trec
Generator
WATCHDOG
TIMER
WDI
RST
ECON OUTPUT
CONTROL
E
ECON
AI07899a
Figure 11. Hardware Hookup
Regulator
Unregulated
Voltage
VIN
VCC
VCC
VCC
VOUT
VCC
0.1µF
STM690A/692A/
703/704/802/805/
817/818/819
LPSRAM
E
E
0.1µF
WDI(1)
From Microprocessor
E(2)
ECON(2)
R1
PFI(3)
PFO(3)
MR(4)
RST
To Microprocessor NMI
R2
Push-Button
To Microprocessor Reset
VBAT
AI07893
Note: 1.
2.
3.
4.
8/37
For STM690A/692A/802/805/817/818.
For STM818 only.
Not available on STM818.
For STM703/704/819.
STM690A/692A/703/704/802/805/817/818/819
OPERATION
Reset Output
The STM690A/692A/703/704/802/805/817/818/
819 Supervisor asserts a reset signal to the MCU
whenever VCC goes below the reset threshold
(VRST), a watchdog time-out occurs, or when the
Push-button Reset Input (MR) is taken low. RST is
guaranteed to be a logic low (logic high for
STM805) for 0V < VCC < VRST if VBAT is greater
than 1V. Without a back-up battery, RST is guaranteed valid down to VCC =1V.
During power-up, once VCC exceeds the reset
threshold an internal timer keeps RST low for the
reset time-out period, trec. After this interval RST
returns high.
If VCC drops below the reset threshold, RST goes
low. Each time RST is asserted, it stays low for at
least the reset time-out period (trec). Any time VCC
goes below the reset threshold the internal timer
clears. The reset timer starts when VCC returns
above the reset threshold.
Push-button Reset Input (STM703/704/819)
A logic low on MR asserts reset. Reset remains
asserted while MR is low, and for trec (see Figure
42., page 28) after it returns high. The MR input
has an internal 40kΩ pull-up resistor, allowing it to
be left open if not used. This input can be driven
with TTL/CMOS-logic levels or with open-drain/
collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is
not required. If MR is driven from long cables or
the device is used in a noisy environment, connect
a 0.1µF capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to
VCC when not used.
Watchdog Input (NOT available on STM703/
704/819)
The watchdog timer can be used to detect an outof-control MCU. If the MCU does not toggle the
Watchdog Input (WDI) within tWD (1.6sec typ), the
reset is asserted. The internal watchdog timer is
cleared by either:
1. a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high),
which can detect pulses as short as 50ns. If
WDI is tied high or low, a reset pulse is
triggered every 1.8sec (tWD + trec).
The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is released, the timer starts counting (see Figure
43., page 28).
Note: The watchdog function may be disabled by
floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10uA and the
maximum allowable load capacitance is 200pF.
Note: Input frequency greater than 20ns (50MHz)
will be filtered.
9/37
STM690A/692A/703/704/802/805/817/818/819
Back-up Battery Switchover
In the event of a power failure, it may be necessary
to preserve the contents of external SRAM
through VOUT. With a backup battery installed with
voltage VBAT, the devices automatically switch the
SRAM to the back-up supply when VCC falls.
Note: If back-up battery is not used, connect both
VBAT and VOUT to VCC.
This family of Supervisors does not always connect VBAT to VOUT when VBAT is greater than VCC.
VBAT connects to VOUT (through a 100Ω switch)
when VCC is below VRST and VBAT. This is done to
allow the back-up battery (e.g., a 3.6V lithium cell)
to have a higher voltage than VCC.
Assuming VBAT > 2.0V, switchover at VSO ensures
that battery back-up mode is entered before VOUT
gets too close to the 2.0V minimum required to reliably retain data in most external SRAMs. When
VCC recovers, hysteresis is used to avoid oscillation around the VSO point. VOUT is connected to
VCC through a 3Ω PMOS power switch.
Note: The back-up battery may be removed while
VCC is valid, assuming VBAT is adequately decoupled (0.1µF typ), without danger of triggering a reset.
Table 4. I/O Status in Battery Back-up
Pin
Status
VOUT
Connected to VBAT through internal switch
VCC
Disconnected from VOUT
PFI
Disabled
PFO
Logic low
E
High impedance
ECON
Logic high
WDI
Watchdog timer is disabled
WDO
Logic low
MR
Disabled
RST
Logic low
RST
Logic high
VBAT
Connected to VOUT
10/37
Chip-Enable Gating (STM818 only)
Internal gating of the chip enable (E) signal prevents erroneous data from corrupting the external
CMOS RAM in the event of an undervoltage condition. The STM818 uses a series transmission
gate from E to ECON (see Figure 12., page 11).
During normal operation (reset not asserted), the
E transmission gate is enabled and passes all E
transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from
corrupting the CMOS RAM. The short E propagation delay from E to ECON enables the STM818 to
be used with most µPs. If E is low when reset asserts, ECON remains low for typically 15µs to permit the current WRITE cycle to complete. Connect
E to VSS if unused.
Chip Enable Input (STM818 only)
The chip-enable transmission gate is disabled and
E is high impedance (disabled mode) while reset
is asserted. During a power-down sequence when
VCC passes the reset threshold, the chip-enable
transmission gate disables and E immediately becomes high impedance if the voltage at E is high.
If E is low when reset asserts, the chip-enable
transmission gate will disable 15µs after reset asserts (see Figure 13., page 11). This permits the
current WRITE cycle to complete during powerdown.
Any time a reset is generated, the chip-enable
transmission gate remains disabled and E remains
high impedance (regardless of E activity) for the
reset time-out period. When the chip enable transmission gate is enabled, the impedance of E appears as a 40Ω resistor in series with the load at
ECON. The propagation delay through the chip-enable transmission gate depends on VCC, the
source impedance of the drive connected to E,
and the loading on ECON. The chip enable propagation delay is production tested from the 50%
point on E to the 50% point on ECON using a 50Ω
driver and a 50pF load capacitance (see Figure
40., page 28). For minimum propagation delay,
minimize the capacitive load at ECON and use a
low-output impedance driver.
Chip Enable Output (STM818 only)
When the chip-enable transmission gate is enabled, the impedance of ECON is equivalent to a
40Ω resistor in series with the source driving E. In
the disabled mode, the transmission gate is off
and an active pull-up connects ECON to VOUT (see
Figure 12., page 11). This pull-up turns off when
the transmission gate is enabled.
STM690A/692A/703/704/802/805/817/818/819
Figure 12. Chip-Enable Gating
VCC
trec
Generator
COMPARE
VRST
RST
VOUT
ECON OUTPUT
CONTROL
E
ECON
AI08802
Figure 13. Chip Enable Waveform
VCC
ECON
RST
VRST
VBAT
trec
15µs
trec
E
AI08803b
11/37
STM690A/692A/703/704/802/805/817/818/819
Power-fail Input/Output (NOT available on STM818)
The Power-fail Input (PFI) is compared to an interDuring battery back-up, the power-fail comparator
nal reference voltage (independent from the VRST
turns off and PFO goes (or remains) low (see Figcomparator). If PFI is less than the power-fail
ure 14 and Figure 15., page 13). This occurs after
threshold (VPFI), the Power-Fail Output (PFO) will
VCC drops below 2.4V (or VSO). When power rego low. This function is intended for use as an unturns, PFO is forced high (STM817/819 only), irrespective of VPFI for the WRITE protect time (trec).
dervoltage detector to signal a failing power supAt the end of this time, the power-fail comparator
ply. Typically PFI is connected through an external
is enabled and PFO follows PFI. If the comparator
voltage divider (see Figure 11., page 8) to either
is unused, PFI should be connected to VSS and
the unregulated DC input (if it is available) or the
PFO left unconnected. PFO may be connected to
regulated output of the VCC regulator. The voltage
divider can be set up such that the voltage at PFI
MR on the STM703/704/818 so that a low voltage
on PFI will generate a reset output.
falls below VPFI several milliseconds before the
regulated VCC input to the STM690A/692A/703/
Applications Information
704/802/805/817/818/819 Supervisor or the miThese Supervisor circuits are not short-circuit procroprocessor drops below the minimum operating
tected. Shorting VOUT to ground - excluding powvoltage.
er-up transients such as charging a decoupling
capacitor - destroys the device. Decouple both
VCC and VBAT pins to ground by placing 0.1µF capacitors as close to the device as possible.
Figure 14. Power-fail Comparator Waveform (STM817/818/819)
VCC
VRST
VSO (or 2.4V)
trec
PFO
(STM817/819)
PFO follows PFI
PFO follows PFI
RST to ECON Delay (STM818)
RST
ECON (STM818)
AI08804a
12/37
STM690A/692A/703/704/802/805/817/818/819
Figure 15. Power-fail Comparator Waveform (STM690A/692A/703/704/802/805)
VCC
VRST
2.4V (or VSO)
trec
PFO
PFO follows PFI
PFO follows PFI
RST
AI08832a
13/37
STM690A/692A/703/704/802/805/817/818/819
Using a SuperCap™ as a Backup Power
Source
SuperCaps™ are capacitors with extremely high
capacitance values (e.g., order of 0.47F) for their
size. Figure 16 shows how to use a SuperCap as
a back-up power source. The SuperCap may be
connected through a diode to the 5V input. Since
VBAT can exceed VCC while VCC is above the reset
threshold, there are no special precautions when
using these supervisors with a SuperCap.
Negative-Going VCC Transients
The STM690A/692A/703/704/802/805/817/818/
819 Supervisor are relatively immune to negativetransients
(glitches).
Figure
going
VCC
38., page 25 shows typical transient duration versus reset comparator overdrive (for which the
STM690A/692A/703/704/802/805/817/818/819
will NOT generate a reset pulse). The graph was
generated using a negative pulse applied to VCC,
starting at VRST + 0.3V and ending below the reset
threshold by the magnitude indicated (comparator
overdrive). The graph indicates the maximum
pulse width a negative VCC transient can have
without causing a reset pulse. As the magnitude of
the transient increases (further below the threshold), the maximum allowable pulse width decreases. Any combination of duration and overdrive
which lies under the curve will NOT generate a reset signal. Typically, a VCC transient that goes
100mV below the reset threshold and lasts 40µs or
less will not cause a reset pulse. A 0.1µF bypass
capacitor mounted as close as possible to the VCC
pin provides additional transient immunity.
Battery Freshness Seal (STM817/818/819)
The battery freshness seal disconnects the backup battery from internal circuitry and VOUT until it is
needed. This allows an OEM to ensure that the
back-up battery connected to VBAT will be fresh
when the final product is put to use. To enable the
freshness seal:
1. Connect a battery to VBAT;
2. Ground PFO;
3. Bring VCC above the reset threshold and hold
it there until reset is deasserted following the
reset timeout period; and
4. Bring VCC down again (Figure 17).
14/37
Use the same procedure for the STM818, but
ground ECON instead of PFO. Once the battery
freshness seal is enabled (disconnecting the
back-up battery from internal circuitry and anything connected to VOUT), it remains enabled until
VCC is brought above VRST.
Figure 16. Using a SuperCap™
5V
VCC
VOUT
To external SRAM
STMXXX
VBAT
RST
To µP
GND
AI08805
Figure 17. Freshness Seal Enable Waveform
VRST
VCC
trec
RST
ECON
(Externally held at 0V)
(STM818)
PFO
(Externally held at 0V)
ECON out state latched
at 1/2 trec, Freshness
Seal enabled
PFO out state latched
at 1/2 trec, Freshness
Seal Enabled
(STM817/819)
AI08806
STM690A/692A/703/704/802/805/817/818/819
TYPICAL OPERATING CHARACTERISTICS
Note: Typical values are at TA = 25°C
Figure 18. VCC-to-VOUT On-Resistance vs. Temperature
VCC-to-VOUT On-Resistance (Ω)
5.0
VCC = 3.0V
4.0
VCC = 4.5V
VCC = 5.5V
3.0
2.0
1.0
0.0
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI10498
Figure 19. VBAT-to-VOUT On-Resistance vs. Temperature
VBAT - to - VOUT On-Resistance (Ω)
160
140
120
100
80
60
VBAT = 2.0V
40
VBAT = 3.0V
VBAT = 3.3V
20
VBAT = 3.6V
0
–40
–20
0
20
40
60
Temperature (°C)
80
100
120
AI09140b
15/37
STM690A/692A/703/704/802/805/817/818/819
Figure 20. Supply Current vs. Temperature (no load)
30
Supply Current (µA)
25
20
15
VCC = 2.7V
VCC = 3.0V
VCC = 3.6V
VCC = 4.5V
VCC = 5.5V
10
5
0
–40
–20
0
20
40
60
80
100
Temperature (°C)
120
AI09141b
Figure 21. Battery Current vs. Temperature
Battery Supply Current (nA)
1000
100
VBAT = 2.0V
VBAT = 3.0V
VBAT = 3.6V
10
1
0.1
–40
–20
0
20
40
60
Temperature (°C)
16/37
80
100
120
AI10499
STM690A/692A/703/704/802/805/817/818/819
Figure 22. VPFI Threshold vs. Temperature
1.270
1.265
VCC = 3.0V
VCC = 4.5V
VCC = 4.75V
VCC = 5.5V
VPFI Threshold (V)
1.260
1.255
1.250
1.245
1.240
1.235
1.230
1.225
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09142c
Figure 23. Reset Comparator Propagation Delay vs. Temperature (Other than STM817/818/819)
30
28
Propagation Delay (µs)
26
24
22
20
18
16
14
12
10
–40
–20
0
20
40
Temperature (°C)
60
80
100
120
AI09143b
17/37
STM690A/692A/703/704/802/805/817/818/819
Figure 24. Reset Comparator Propagation Delay vs. Temperature (VBAT=3.0V; STM817/818/819)
350
1v/ms
Propagation Delay (µs)
300
10V/ms
250
200
150
100
50
0
–40
–20
0
20
40
60
80
100
Temperature (°C)
120
AI11100
Figure 25. Power-up trec vs. Temperature
240
235
trec (ms)
230
VCC = 3.0V
225
VCC = 4.5V
VCC = 5.5V
220
215
210
–40
–20
0
20
40
60
Temperature (°C)
18/37
80
100
120
AI09144b
STM690A/692A/703/704/802/805/817/818/819
Figure 26. Normalized Reset Threshold vs. Temperature
Normalized Reset Threshold
1.004
1.002
1.000
0.998
0.996
–40
–20
0
20
40
60
80
100
120
Temperature (°C)
AI09145b
Figure 27. Watchdog Time-out Period vs. Temperature
Watchdog Time-out Period (sec)
1.90
1.85
1.80
1.75
VCC = 3.0V
VCC = 4.5V
VCC = 5.5V
1.70
1.65
1.60
–40
–20
0
20
40
Temperature (°C)
60
80
100
120
AI09146b
19/37
STM690A/692A/703/704/802/805/817/818/819
Figure 28. E to ECON On-Resistance vs. Temperature
60
E to ECON On-Resistance (Ω)
50
40
30
VCC = 3.0V
VCC = 4.5V
VCC = 5.5V
20
10
0
–40
–20
0
20
40
60
80
100
Temperature (°C)
120
AI09147b
Figure 29. PFI to PFO Propagation Delay vs. Temperature
PFI to PFO Propagation Delay (µs)
4.0
VCC = 3.0V
VCC = 3.6V
3.0
VCC = 4.5V
VCC = 5.5V
2.0
1.0
0.0
–40
–20
0
20
40
Temperature (°C)
20/37
60
80
100
120
AI09148b
STM690A/692A/703/704/802/805/817/818/819
Figure 30. Output Voltage vs. Load Current (VCC = 5V; VBAT = 2.8V; TA = 25°C)
5.00
VOUT (V)
4.98
4.96
4.94
0
10
20
30
40
IOUT (mA)
50
AI10496
Figure 31. Output Voltage vs. Load Current (VCC = 0V; VBAT = 2.8V; TA = 25°C)
2.80
2.78
VOUT (V)
2.76
2.74
2.72
2.70
2.68
2.66
0.0
0.2
0.4
IOUT (mA)
0.6
0.8
1.0
AI10497
21/37
STM690A/692A/703/704/802/805/817/818/819
Figure 32. RST Output Voltage vs. Supply Voltage
5
5
VRST (V)
4
4
3
3
2
2
1
1
0
VCC (V)
VRST
VCC
0
500ms/div
AI09149b
Figure 33. RST Output Voltage vs. Supply Voltage
5
VRST
VCC
VRST (V)
4
3
3
2
2
1
1
0
0
500ms/div
22/37
4
VCC (V)
5
AI09150b
STM690A/692A/703/704/802/805/817/818/819
Figure 34. RST Response Time (Assertion)
5V
1V/div
VCC
4V
5V
4V
RST
1V/div
0V
5µs/div
AI09151b
23/37
STM690A/692A/703/704/802/805/817/818/819
Figure 35. RST Response Time (Assertion)
5V
VCC
4V
1V/div
4V
RST
1V/div
0V
5µs/div
AI09152b
Figure 36. Power-fail Comparator Response Time (Assertion)
5V
1V/div
PFO
0V
1.3V
PFI
500mV/div
0V
500ns/div
24/37
AI09153b
STM690A/692A/703/704/802/805/817/818/819
Figure 37. Power-fail Comparator Response Time (De-Assertion)
5V
1V/div
PFO
0V
1.3V
PFI
500mV/div
0V
500ns/div
AI09154b
Figure 38. Maximum Transient Duration vs. Reset Threshold Overdrive
6000
Transient Duration (µs)
5000
4000
Reset occurs
above the curve.
3000
2000
1000
0
0.001
0.01
0.1
Reset Comparator Overdrive, VRST – VCC (V)
1
10
AI09156b
25/37
STM690A/692A/703/704/802/805/817/818/819
Figure 39. E to ECON Propagation Delay vs. Temperature
E to ECON Propagation Delay (ns)
4.0
3.0
2.0
VCC = 3.0V
VCC = 4.5V
VCC = 5.5V
1.0
0.0
–40
–20
0
20
40
60
Temperature (°C)
26/37
80
100
120
AI09157b
STM690A/692A/703/704/802/805/817/818/819
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 5. Absolute Maximum Ratings
Symbol
TSTG
TSLD(1)
VIO
Parameter
Value
Unit
–55 to 150
°C
260
°C
–0.3 to VCC +0.3
V
Storage Temperature (VCC Off)
Lead Solder Temperature for 10 seconds
Input or Output Voltage
VCC/VBAT
Supply Voltage
–0.3 to 6.0
V
IO
Output Current
20
mA
PD
Power Dissipation
320
mW
Note: 1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C for between 90 to 150
seconds).
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 6, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 6. Operating and AC Measurement Conditions
STM690A/692A/703/704/802/
805/817/818/819
Unit
VCC/VBAT Supply Voltage
1.0 to 5.5
V
Ambient Operating Temperature (TA)
–40 to 85
°C
≤5
ns
Input Pulse Voltages
0.2 to 0.8VCC
V
Input and Output Timing Ref. Voltages
0.3 to 0.7VCC
V
Parameter
Input Rise and Fall Times
27/37
STM690A/692A/703/704/802/805/817/818/819
Figure 40. E to ECON Propagation Delay Test Circuit
VCC
VCC
VBAT
3.6V
STMXXX
25Ω Equivalent
Source Impedance
E
50Ω
ECON
50Ω Cable
50pF CL(1)
50Ω
GND
AI08854
Note: 1. CL includes load capacitance and scope probe capacitance.
Figure 41. AC Testing Input/Output Waveforms
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Figure 42. MR Timing Waveform
MR
tMLRL
RST
(1)
tMLMH
trec
AI07837a
Note: 1. RST for STM805.
Figure 43. Watchdog Timing
VCC
RST
WDI
trec
tWD
AI07891
28/37
STM690A/692A/703/704/802/805/817/818/819
Table 7. DC and AC Characteristics
Sym
VCC,
VBAT(2)
ICC
IBAT(4)
VOUT1
VOUT2
ILI
Alternative
Description
Operating Voltage
Test Condition(1)
Min
TA = –40 to +85°C
1.2(3)
Typ
Max
Unit
5.5
V
VCC Supply Current
Excluding IOUT (VCC < 5.5V)
25
60
µA
VCC Supply Current in
Battery Back-up Mode
Excluding IOUT (VBAT = 2.3V,
VCC = 2.0V, MR = VCC)
25
35
µA
VBAT Supply Current in
Battery Back-up Mode
Excluding IOUT (VBAT = 3.6V)
0.4
1.0
µA
VOUT Voltage (Active)
VOUT Voltage (Battery
Back-up)
IOUT1 = 5mA(5)
VCC –
0.03
VCC –
0.015
V
IOUT1 = 75mA
VCC –
0.3
VCC –
0.15
V
IOUT1 = 250µA, VCC > 2.5V(5)
VCC –
0.0015
VCC –
0.0006
V
IOUT2 = 250µA, VBAT = 2.3V
VBAT –
0.1
VBAT –
0.034
V
VBAT –
0.14
V
IOUT2 = 1mA, VBAT = 2.3V
VCC to VOUT On-resistance
3
VBAT to VOUT On-resistance
100
4
Ω
Ω
Input Leakage Current (MR)
4.5V < VCC < 5.5V
75
125
300
µA
Input Leakage Current (PFI)
0V = VIN = VCC
–25
2
+25
nA
120
160
µA
Input Leakage Current
(WDI)(6)
WDI = VCC, time average
WDI = GND, time average
–20
–15
µA
VIH
Input High Voltage (MR)
4.5V < VCC < 5.5V
2.0
V
VIH
Input High Voltage (WDI)
VRST (max) < VCC < 5.5V
0.7VCC
V
VIL
Input Low Voltage (MR)
4.5V < VCC < 5.5V
0.8
V
VIL
Input Low Voltage (WDI)
VRST (max) < VCC < 5.5V
0.3VCC
V
Output Low Voltage (PFO,
RST, RST)
VCC = VRST (max), ISINK =
3.2mA
0.3
V
Output Low Voltage (ECON)
VCC = VRST (max),
IOUT = 1.6mA, E = 0V
0.2VCC
V
ISINK = 50µA, VCC = 1.0V,
VBAT = VCC, TA = 0°C to 85°C
0.3
V
ISINK = 100µA, VCC = 1.2V,
VBAT = VCC
0.3
V
VOL
VOL
Output Low Voltage (RST)
29/37
STM690A/692A/703/704/802/805/817/818/819
Sym
Alternative
Test Condition(1)
Min
ISOURCE = 1mA,
VCC = VRST (max)
2.4
V
Output High Voltage (ECON)
VCC = VRST (max),
IOUT = 1.6mA, E = VCC
0.8VCC
V
Output High Voltage (PFO)
ISOURCE = 75µA,
VCC = VRST (max)
0.8VCC
V
Description
Output High Voltage (RST,
RST)
VOH
VOH
Typ
Max
Unit
ISOURCE = 4µA, VCC = 1.1V,
VBAT = VCC, TA = 0°C to 85°C
0.8
V
ISOURCE = 4µA, VCC = 1.2V,
VBAT = VCC
0.9
V
Output High Voltage
VOH Battery Back-up (RST,
RST)
ISOURCE = 100µA,
VCC = 0, VBAT = 2.8V
0.8VBAT
V
VOH Battery Back-up (ECON)
ISOURCE = 75µA,
VCC = 0, VBAT = 2.8V
0.8VBAT
V
VOHB
Power-fail Comparator (NOT available on STM818)
VPFI
PFI Input Threshold
tPFD
PFI to PFO Propagation
Delay
ISC
PFO Output Short to
GND Current
PFI Falling
(VCC = 5V)
All other
versions
1.20
1.25
1.30
V
STM802
1.225
1.250
1.275
V
2
VCC = 5V, VPFO = 0V
0.1
0.75
µs
2.0
mA
Battery Switchover
VSO
Battery Back-up
Switchover Voltage (7,8)
(VCC < VBAT & VCC < VRST)
VRST > VBAT
VBAT
V
VRST < VBAT
VRST
V
VRST > VBAT
VBAT
V
VRST < VBAT
VRST
V
40
mV
Power-down
Power-up
Hysteresis
Reset Thresholds
VRST
Reset Threshold(9)
STM690A/703, STM8XXL
4.50
4.65
4.75
V
STM692A/704, STM8XXM
4.25
4.40
4.50
V
Reset Threshold Hysteresis
VCC to RST Delay (from
VRST, VCC falling at 10V/ms)
trec
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RST Pulse Width
STM817/818/819
140
25
mV
100
µs
200
280
ms
STM690A/692A/703/704/802/805/817/818/819
Sym
Alternative
Description
Test Condition(1)
Min
STM703/704
150
ns
STM819
1
µs
Typ
Max
Unit
Push-button Reset Input (STM703/704/819)
tMLMH
tMR
MR Pulse Width
tMLRL
tMRD
MR to RST Output Delay
STM703/704
250
ns
STM819
120
ns
MR Glitch Immunity
STM819
100
ns
MR Pull-up Resistor
MR = 0V, VCC = 5V
45
63
85
kΩ
1.60
2.24
s
Watchdog Timer (NOT available on STM703/704/819)
tWD
Watchdog Timeout Period
VRST (max) < VCC < 5.5V
1.12
WDI Pulse Width
VRST (max) < VCC < 5.5V
50
ns
Chip-Enable Gating (STM818 only)
E-to-ECON Resistance
VCC = VRST (max)
40
150
Ω
E-to-ECON Propagation Delay
4.5V < VCC < 5.5V
2
7
ns
Reset-to-ECON High Delay
(Power-down)
15
ECON Short Circuit Current
VCC = 5V, Disable Mode,
E = Logic high, ECON = 0V
0.1
0.75
µs
2.0
mA
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.75V to 5.5V for “L” versions; VCC = 4.5V to 5.5V for “M” versions; and VBAT = 2.8V (except where noted).
2. VCC supply current, logic input leakage, Watchdog functionality, Push-button Reset functionality, PFI functionality, state of RST and
RST tested at VBAT = 3.6V, and VCC = 5.5V. The state of RST or RST and PFO is tested at VCC = VCC (min). Either VCC or VBAT
can go to 0V if the other is greater than 2.0V.
3. VCC (min) = 1.0V for TA = 0°C to +85°C.
4. Tested at VBAT = 3.6V, VCC = 3.5V and 0V.
5. Guaranteed by design.
6. WDI input is designed to be driven by a three-state output device. To float WDI, the “high impedance mode” of the output device
must have a maximum leakage current of 10µA and a maximum output capacitance of 200pF. The output device must also be able
to source and sink at least 200µA when active.
7. When VBAT > VCC > VRST, VOUT remains connected to VCC until VCC drops below VRST.
8. When VRST > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) – 75mV.
9. For VCC falling.
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STM690A/692A/703/704/802/805/817/818/819
PACKAGE MECHANICAL
Figure 44. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing
h x 45˚
A2
A
C
B
ddd
e
D
8
E
H
1
A1
α
L
SO-A
Note: Drawing is not to scale.
Table 8. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
–
1.35
1.75
–
0.053
0.069
A1
–
0.10
0.25
–
0.004
0.010
B
–
0.33
0.51
–
0.013
0.020
C
–
0.19
0.25
–
0.007
0.010
D
–
4.80
5.00
–
0.189
0.197
ddd
–
–
0.10
–
–
0.004
E
–
3.80
4.00
–
0.150
0.157
e
1.27
–
–
0.050
–
–
H
–
5.80
6.20
–
0.228
0.244
h
–
0.25
0.50
–
0.010
0.020
L
–
0.40
0.90
–
0.016
0.035
α
–
0°
8°
–
0°
8°
N
32/37
8
8
STM690A/692A/703/704/802/805/817/818/819
Figure 45. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8BM
Note: Drawing is not to scale.
Table 9. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
–
–
1.10
–
–
0.043
A1
–
0.05
0.15
–
0.002
0.006
A2
0.85
0.75
0.95
0.034
0.030
0.037
b
–
0.25
0.40
–
0.010
0.016
c
–
0.13
0.23
–
0.005
0.009
CP
–
–
0.10
–
–
0.004
D
3.00
2.90
3.10
0.118
0.114
0.122
e
0.65
–
–
0.026
–
–
E
4.90
4.65
5.15
0.193
0.183
0.203
E1
3.00
2.90
3.10
0.118
0.114
0.122
L
0.55
0.40
0.70
0.022
0.016
0.030
L1
0.95
–
–
0.037
–
–
α
–
0°
6°
–
0°
6°
N
8
8
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STM690A/692A/703/704/802/805/817/818/819
PART NUMBERING
Table 10. Ordering Information Scheme
Example:
STM690A
M
6
E
Device Type
STM690A/692A/703/704/802/805/817/818/819
Reset Threshold Voltage
STM690A/703: blank = VRST = 4.50V to 4.75V
STM8xxL: L = VRST = 4.50V to 4.75V
STM692A/704: blank = VRST = 4.25V to 4.50V
STM8xxM: M = VRST = 4.25V to 4.50V
Package
M = SO8
DS(1) = TSSOP8
Temperature Range
6 = –40 to 85°C
Shipping Method
E = ECOPACK Package, Tubes
F = ECOPACK Package, Tape & Reel
Note: 1. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
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STM690A/692A/703/704/802/805/817/818/819
Table 11. Marking Description
Part Number
Reset Threshold
Package
Topside Marking
STM690A
4.65V
SO8
690A
STM692A
4.40V
SO8
692A
STM703
4.65V
SO8
703
STM704
4.40V
SO8
704
STM802L
4.65V
SO8
802L
STM802M
4.40V
SO8
802M
STM805L
4.65V
SO8
805L
STM817L
4.65V
SO8
817L
TSSOP8
SO8
STM817M
4.40V
817M
TSSOP8
SO8
STM818L
4.65V
818L
TSSOP8
SO8
STM818M
4.40V
818M
TSSOP8
SO8
STM819L
4.65V
819L
TSSOP8
SO8
STM819M
4.40V
819M
TSSOP8
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STM690A/692A/703/704/802/805/817/818/819
REVISION HISTORY
Table 12. Document Revision History
Date
Version
October 2003
1.0
First Issue
31-Oct-03
1.1
Update DC Characteristics (Table 7)
22-Dec-03
2.0
Reformatted; updated characteristics (Figure 1, 3, 4, 7, 8, 9, 10, 11, 12, 13, 14, 15,
17; Table 3, 4, 7, 9, 11)
16-Jan-04
2.1
Add Typical Characteristics (Figure 19, 20, 22, 23, 25, 26, 27, 28, 29, 32, 33, 34,
35, 36, 37, 38, 39)
08-Apr-04
2.2
Update characteristics (Figure 13, 23, 29, 33, 34, 35, 38; Table 1,7)
25-May-04
3.0
Remove references to ‘Open Drain’ (Figure 2, 5, 8; Table 2); update characteristics
(Table 3, 7)
05-Jul-04
4.0
Update package availability, pin description; promote document (Figure 1, 14, 15;
Table 3. 7, 10)
29-Sep-04
5.0
Clarify root part numbers, pin descriptions (Figure 11, 13, 40; Table 7, 10)
01-Mar-05
6.0
Update characteristics (Figure 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
32, 33, 34, 35, 36, 37, 38, 39)
20-Jan-05
7.0
Correct marking, update Lead-free text (Table 10, 11)
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Revision Details
STM690A/692A/703/704/802/805/817/818/819
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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