STMICROELECTRONICS STN8815A09

34.807IRELESS
IMPORTANT NOTICE
Dear customer,
As from August 2nd 2008, the wireless operations of STMicroelectronics have moved to a
new company, ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
●
Company name - STMicroelectronics NV is replaced with ST-NXP Wireless.
●
Copyright - the copyright notice at the bottom of the last page “© STMicroelectronics
200x - All rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights
reserved”.
●
Web site - http://www.st.com is replaced with http://www.stnwireless.com
●
Contact information - the list of sales offices is found at http://www.stnwireless.com
under Contacts.
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
34.807IRELESS
www.stnwireless.com
STn8815A09
Mobile multimedia application processor
Data Brief
Nomadik is a registered trademark of STMicroelectronics
Features
■
Smart video accelerator
– MPEG-4 Simple Profile L5
encoding/decoding up to SDTV 30 fps
– DVB-H class C H264 BP L2 2Mbps
CIF 30fps
– DVB-H class B VC1 SP 384kbps
QVGA 20fps
– H.264 decode resolution up to VGA bit-rate
up to 4Mbps
– JPEG encode up to 40 Mpixel/s, decode up
to 10 Mpixel/s
■
Advanced power management unit
■
ARM926EJ® 32-bit RISC CPU, up to 393 MHz
– 16-Kbyte instruction cache, 16-Kbyte data
cache, 128-Kbyte level 2 cache
■
On-chip SRAM: 512 Kbytes + 16 Kbytes with
secured access + 1 Kbyte backup
■
On-chip ROM: 32 Kbytes for boot
+ 64 Kbytes with secured access
■
Enhanced security framework and protected
access to secured ROM and RAM
■
16-bit DDR/SDR-SDRAM memory controller
(up to 166 MHz)
■
Smart audio accelerator with extensive digitalaudio software library
■
NOR Flash/NAND Flash/CompactFlash/CF+
controller
■
Smart imaging accelerator
– 5 Mpixel camera support
– 2 SMIA CCP2 camera interfaces up to
650 Mbit/s and parallel camera CCIR-656
interface up to 80 MHz
– Real-time image reconstruction up to
80 Mpixel/s and 10-bit raw Bayer interface
■
VFBGA 9.0mm x 9.0mm x 1.0mm package
■
Smart graphics accelerator
■
Ultra low-power implementation
■
TV output
Figure 1.
Description
The STn8815A09 application processor enables
smart phones, mobile multimedia, internet
appliances and in-car entertainment systems to
playback media content, record video clips and
pictures, receive mobile-TV and perform real-time
bidirectional audio-visual communication.
STn8815A09 block diagram
Host port interface
Color LCD controller
Display interfaces
Multichannel DMA
controller
Secured
RAM/ROM
TV output
Camera interface x3
USB-OTG x2
I²C x3
eSRAM
buffer
NAND/NOR Flash
controller
RTC
January 2008
HSI x2
Smart graphics
accelerator
Smart imaging
accelerator
UART x3
SSP
DDR SDRAM
controller
Watchdog
Smart audio
accelerator
MSP x4
SD/MMC/MS
Timers
Smart video
accelerator
FIrDA
Power
management
L2 cache
System
controller
Security toolbox
Dcache
Interrupt
controller
PLLs
Icache
ARM926EJ
Rev 2
For further information contact your local STMicroelectronics sales office.
1-Wire/HDQ interface
Rotary encoder i/f
Keypad interface
JTAG/trace
GPIO x124
1/21
www.st.com
1
Contents
STn8815A09
Contents
1
2
2/21
STn8815A09 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3
Low power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4
Open platform strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
Smart video accelerator (SVA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Smart audio accelerator (SAA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
Smart imaging accelerator (SIA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4
Smart graphics accelerator (SGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5
Advanced power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6
ARM926EJ processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7
Embedded memory units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.8
Advanced security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.9
Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 13
2.10
SDRAM memory controller (SDMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.11
Real time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.12
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.13
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.14
Vectored interrupt controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.15
System and reset controller (SRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.16
Direct memory access (DMA) controllers . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.17
Universal asynchronous receivers-transmitters (UARTs) . . . . . . . . . . . . . 14
2.18
Synchronous serial port (SSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.19
Camera interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.20
TV interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.21
Liquid crystal display controller (LCDC) . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.22
Master display interface (MDIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.23
Pulse width light modulator (PWL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.24
General purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 15
STn8815A09
Contents
2.25
Memory card interface (MMC/SD/MS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.26
USB-OTG high-speed interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.27
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.28
Fast IrDA interface (FIrDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.29
Multichannel serial ports (MSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.30
Scroll key and keypad encoder (SKE) interface . . . . . . . . . . . . . . . . . . . . 17
2.31
High-speed serial interface (HSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.32
Host port interface (HPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3/21
STn8815A09 overview
1
STn8815A09 overview
●
●
●
Smart video accelerator
–
MPEG-4 encoder/decoder Simple Profile (SP) L5 SDTV 30 fps
–
MPEG4 decode up to 2 x SDTV 30 fps decode
–
DVB-H class C H264 baseline L2 2Mbps CIF 30 fps
–
DVB-H class B VC1 SP Main-Level 384kbps QVGA 20 fps/CIF 15 fps
–
H264 decode resolution up to VGA, bit-rate up to 4Mbps
–
H264 codec QCIF 15 fps
–
H263 codec up to CIF 30fps
–
T-DMB profile 1 and 2: H264 baseline L1.3 768 kbps CIF 30 fps
–
T-DMB two streams H264 baseline profile L1.3 768 kbps QVGA 30 fps each
–
JPEG encode up to 40 Mpixel/s, decode up to 10 Mpixel/s
–
Ultra low-power implementation
Smart audio accelerator
–
Extensive digital-audio software library
–
Ultra low-power implementation
Smart imaging accelerator
–
5 Mpixel camera support
–
2 SMIA CCP2 camera interfaces up to 650 Mbit/s
–
Parallel camera CCIR-656 interface up to 80 MHz
–
Real-time image reconstruction up to 80 Mpixel/s
–
10-bit raw Bayer interface
–
Ultra low-power implementation
●
Smart graphics accelerator for 2-D and 3-D OSD
●
TV output
●
Advanced power management unit
●
4/21
STn8815A09
–
Run, idle, doze and sleep modes
–
CPU clock with programmable frequency
–
Enhanced dynamic power-domain management
–
Dynamic voltage scaling
ARM926EJ® 32-bit RISC CPU, up to 393 MHz
–
16-Kbyte instruction cache, 16-Kbyte data cache
–
128-Kbyte level 2 cache
–
3 instruction sets: 32-bit for high performance, 16-bit (Thumb) for efficient code
density, byte Java mode (Jazelle™) for direct execution of Java code
–
Embedded medium trace module (ETM Medium+)
●
On-chip SRAM: 512 Kbytes + 16 Kbytes with secured access + 1 Kbyte backup
●
On-chip ROM: 32 Kbytes for boot
+ 64 Kbytes with secured access
STn8815A09
●
STn8815A09 overview
Advanced security
–
Enhanced security framework
–
Protected access to secured ROM and RAM
●
16-bit DDR/SDR-SDRAM memory controller (up to 166 MHz)
●
NOR Flash/NAND Flash/CompactFlash/CF+ controller
●
High-speed MMC/SD Card/Memory Stick Pro host controller
●
Color LCD controller for STN or TFT panels or display interface for display module
●
–
24-bpp true color
–
MIPI™ legacy DBI and DPI
Two high speed USB 2.0 On-The-Go controller interfaces (12 and 480 Mbit/s)
–
ULPI v1.1 compliance
–
ULPI SDR support, DDR not supported
●
Host port interface
●
I/O peripherals
–
3 autobaud UARTs (one with modem control signals) up to 6 Mbit/s
–
One IrDA (SIR/MIR/FIR) interface up to 4 Mbit/s
–
One synchronous serial port (SSP) up to 24 Mbit/s
–
4 multichannel serial ports (MSP) up to 48 Mbit/s
–
3 I²C master/slave interfaces, 1 dedicated to SIA
–
Two 8-channel, full-duplex high-speed serial interfaces, 110 Mbit/s (MIPI legacy
HSI)
–
Rotary encoder interface; keypad matrix interface
–
1-Wire®/HDQ interface (1)
●
124 general-purpose I/Os (muxed with peripheral I/Os)
●
System and peripheral controller
–
Multichannel DMA controller
–
64-source interrupt controller
–
Eight 32-bit timers/counters
–
Real-time clock (RTC)
–
Real-time timer (RTT)
–
Watchdog timer
●
Programmable PLL for CPU and system clocks
●
Two crystal oscillators:
32 kHz and 13/19.2 MHz
●
JTAG IEEE 1149.1 boundary scan
●
Supply voltages
●
–
1.2 V to 1.4 V logic; 1.8 V to 2.5 V I/O, PLL analog; 2.5 V OTP
VFBGA 9.0mm x 9.0mm x 1.0mm, pitch 0.4 mm, 329 balls (216 + 88 + 25)
1. 1-Wire is a registered trademark of Dallas Semiconductor.
5/21
STn8815A09 overview
STn8815A09
The convergence of computing, multimedia and mobile communications is well underway.
Already the familiar voice phone is being transformed into a personal device with a wide
range of multimedia capabilities. Soon mobile users will be able to benefit from a broad
spectrum of multimedia features and services, to include capturing, sending and receiving
images, videos and music. To deliver such data-heavy, processing-intensive services,
portable handheld systems must be optimized for high performance but low power, space
and cost.
In response to this need, the STn8815A09 processor platform from STMicroelectronics is a
culmination of breakthroughs in video coding efficiency, inventive algorithms and chip
implementation schemes. It will enable smart phones, wireless PDAs, internet appliances
and car entertainment systems to play back media content, record pictures and video clips,
and perform bidirectional audio-visual communication with other systems in real time.
The STn8815A09 focuses on the essential features to meet the future needs of mobile
products and services: a high-performance multimedia capability coupled with low power
consumption, and based on an open platform strategy.
Figure 2.
Typical system architecture using the STn8815A09
Touch screen
controller
Rotary
wheel
Camera1
TFT
Mono/color STN
smart panel
Camera 2
Keypad
SKE
SSP
NAND Flash
PWL
CLCD/
MDIF
TV
output
NOR Flash
RF
Camera
interfaces
High-speed
serial interface
SRAM
ROM
Camera 3
Denc
STw8009
LCD backlight
FSMC
Host port
interface
I²C
Energy
management
STw4810
FIrDA
Fast IrDA
CompactFlash/CF+
ATA device
Low-power
SDRAM
Mobile
DDR SDRAM
Nomadik
STn8815
SDMC
UART
Bluetooth
I²C
FM radio
UART
MMC
SD-Card
USB-OTG
high speed
MMCI
Memory Stick Pro
RTC
ETM9
JTAG
Debug, trace
6/21
Clock, reset
Reset
32 kHz 13/19.2 MHz
I²S
Audio
codecs
STw5095
GSM/GPRS/EDGE
xCDMA
modem chip set
GPS module
USB device
MSP
802.11x WLAN
MSP
Digital TV
demodulator
STn8815A09
1.1
STn8815A09 overview
Key benefits
The STn8815A09 brings the following key benefits to mobile manufacturers and consumers:
1.2
●
Unsurpassed audio, video and imaging quality,
●
Ultra-low power consumption for longer battery operation,
●
Easier application development for shorter time-to-market,
●
Scalability for multiple market segments and future multimedia applications.
Main features
The STn8815A09 processor platform enables compelling multimedia applications by means
of its unique distributed-processing architecture.
The application processor features low-power smart accelerators which handle all audio,
video and graphics functions. These free the main CPU for control and program flow tasks,
or allow the CPU to enter power-saving modes to prolong battery life. The smart
accelerators operate independently and concurrently to ensure the lowest absolute system
power and deterministic high-performance.
The main features of the platform are:
●
A smart video accelerator for SDTV video encoding and decoding, with MIPI and SMIA
camera interfaces.
●
A smart audio accelerator containing a comprehensive set of digital audio decoders
and encoders, and offering a large number of 3-D surround effects.
●
A smart imaging accelerator, providing real-time, programmable image reconstruction
engine.
●
A smart graphics accelerator.
●
A dynamic, multi-mode power management unit.
●
The ARM926EJ processor, a powerful industry-standard CPU with Java acceleration.
●
On-chip ROM and SRAM memory devices, including a 3-Mbit frame buffer.
●
Security framework for enhanced mobile security, including stronger DRM.
●
Multichannel DMA controller for efficient data transfer without CPU intervention.
●
A multi-layer AMBA crossbar interconnect for optimized data transfers between the
CPU, accelerators, memory devices and peripherals.
●
Hardware semaphores for flexible inter-process management.
●
A wide range of peripheral interfaces (GPIO, USB-OTG high speed, UART, I²C, FIrDA,
SD/high-speed MMC/Memory Stick Pro, fast serial ports, TV output, color LCD and
camera interfaces, scroll-key encoder, key-pad scanner).
●
Direct support for high-level operating system such as Symbian™, Linux and WinCE®
operating systems (OSs).
7/21
STn8815A09 overview
1.3
STn8815A09
Low power consumption
The new multimedia functionality of mobile products brings with it an increase in power
consumption that is outpacing advances in battery technology. The STn8815A09 chip saves
on power by avoiding the need for high clock speeds wherever possible, but its extremely
low power consumption results from a systematic effort at all design levels to reduce power
requirements. These include:
1.4
●
The use of smart accelerators and distributed processing to off load from the CPU,
●
Efficient code execution by means of innovative algorithms, energy-efficient instruction
set architectures and Java acceleration,
●
The efficient use of bandwidth for on-chip data transport, achieved by data
compression, buffering and image scaling,
●
Aggressive power management which includes turning off inactive parts of the chip and
keeping the CPU in power-saving modes as much as possible.
Open platform strategy
STMicroelectronics is a founding member of the MIPI™ Alliance working towards mobile
software and hardware interface standards.
Our open platform strategy provides manufacturers with roadmap flexibility, allowing them to
avoid becoming locked into a proprietary CPU architecture or vendor technology. This
approach is facilitated by the following design points.
8/21
●
The STn8815A09 employs the third-party ARM® processor which is the standard CPU
for mobile devices, with industry-wide application support.
●
Open, standard APIs are provided for the development of application code on a level
which is abstracted from the physical hardware. This allows the development of
multimedia plug-ins that are portable between products and which can be reused on
future products without modification.
●
The STn8815A09 facilitates best-in-class algorithm development on its smart
accelerators.
●
The STn8815A09 is provided with development kits and tools that speed-up the
integration of new operating systems, middleware, and signal processing algorithms.
STn8815A09
2
Architecture overview
Architecture overview
The STn8815A09 platform comprises an industry-standard ARM CPU supported by smart
audio, video, imaging and graphics accelerators, on-chip memory and controllers, a rich set
of peripheral interfaces, and a power management system. The processors, controllers,
memory and peripheral interfaces are connected by a multi-layer advanced microcontroller
bus architecture (AMBA) for efficient data transport between the components. The overall
STn8815A09 architecture is illustrated in Figure 3.
The main hardware components of the STn8815A09 are listed and outlined in the sections
below.
Figure 3.
STn8815A09 block diagram
3 cameras
(parallel or TV
output
serial)
LCD panel
(STN/TFT/module)
NOR
NAND
Flash
control
Backup
RAM 1 KB
Boot ROM
32 Kbytes
Trace
Smart
imaging
accelerator
LCD
MDIF
controller
controller
JTAG
ETM/JTAG
eROM
I/D cache
16/16 Kbytes
64 Kbytes
L2 cache
128 Kbytes
secured
eRAM
16 Kbytes
secured
DDR-
ARM926EJ
eSRAM
Smart
video
accelerator
SDRAM
memory
512 Kbytes
control
Security
toolbox
Interconnect (data/instruction, memory/peripherals)
Host port
interface
Vector
interrupt
Smart audio
controller
USB-OTG
high speed (x2)
accelerator
HSI (x2)
MSP (x3)
System
32 kHz
124 GPIOs
control
RTC
Timers (x8)
PWL
Watchdog
Power
Secure
manager
watchdog
RTT
Semaphores
(x16)
interface
Smart graphics
accelerator
UART (x3)
SD/MMC
MS Pro interface
SSP
Clocks
I²C interface
13/19.2 MHz
(x3)
PLL
FIrDA
CPU/buses/peripherals
interface
Rotary encoder/
keypad interface
9/21
Architecture overview
2.1
STn8815A09
Smart video accelerator (SVA)
Using leading-edge technology, this block is a low-power, high-performance video
accelerator that supports the following features:
●
MPEG-4 encoder/decoder Simple Profile (SP) L5 SDTV 30 fps
●
MPEG4 decode up to 2 x SDTV 30 fps decode
●
DVB-H class C H264 baseline L2 2Mbps CIF 30 fps
●
DVB-H class B VC1 SP Main-Level 384kbps QVGA 20 fps/CIF 15 fps
●
H264 decode resolution up to VGA, bit-rate up to 4Mbps
●
H264 codec QCIF 15 fps
●
H263 codec up to CIF 30fps
●
T-DMB profile 1 and 2: H264 baseline L1.3 768 kbps CIF 30 fps
●
T-DMB two streams H264 baseline profile L1.3 768 kbps QVGA 30 fps each
●
JPEG encode up to 40 Mpixel/s, decode up to 10 Mpixel/s
●
Ultra low-power implementation
This list of codecs is non-exhaustive, and is a baseline for the SVA performances.
2.2
Smart audio accelerator (SAA)
This high-performance block is a flexible sophisticated audio accelerator based on the
MMDSP+ programmable audio DSP, clocked up to 166 MHz, and features:
●
24-bit data path,
●
ultra-low power implementation.
The audio accelerator handles:
10/21
●
Speech and audio codecs: AMR (WB, NR), MP3, AAC, WMA and more,
●
Sample-rate conversion to 8, 16, 32, 44.1 and 48 kHz,
●
Extension of sound field and 3-D surround effects,
●
Noise reduction and echo cancelling.
STn8815A09
2.3
Architecture overview
Smart imaging accelerator (SIA)
The smart imaging accelerator is provided by the image preprocessing module of the SVA.
This flexible imaging engine provides real-time, programmable image processing, and
features:
●
2.4
Shot-to-shot performance (with CMOS sensor):
–
3 Mpixel, up to 15 image/s,
–
5 Mpixel, up to 9 image/s.
●
Direct support for smart sensors (CMOS/CCD modules), unlimited resolution (YUV
input with JPEG compression).
●
Image reconstruction up to 80 Mpixel/s with raw Bayer input.
●
With shutter, maximum sensor resolution depends on external SDRAM size and on
target shot-to-shot delay.
●
Auto-focus control, auto exposure control.
●
Automatic white balance, contrast enhancement, brightness control.
●
On-the-fly zoom, flash-gun control.
●
Noise reduction, gamma correction, image sharpening.
●
Ultra-low power implementation.
Smart graphics accelerator (SGA)
The smart graphics accelerator provides an efficient 2D and 3D drawing tool that enables
next generation of games and user interfaces while minimizing power consumption.
2D features
●
ROP4.
●
Line drawing.
●
Triangle and rectangle fill.
●
Alpha blending bit blit.
●
Stretch/scale/rotate/mirror bit blit.
●
Gradient color fill (horizontal and vertical).
●
Full picture anti-aliasing filter.
●
Image resizing.
●
Font-expansion and anti-aliasing text drawing.
3D features
●
Texture mapping.
●
Texture transparency/blending/clamping/wrapping/mirroring.
●
Flat and Gouraud shading.
●
16-bit Z buffering.
●
Fog and depth cueing.
●
Embossed bump mapping texture generation.
11/21
Architecture overview
2.5
STn8815A09
Advanced power management unit (PMU)
The dynamic PMU optimizes power consumption of the STn8815A09. It delivers all the
platform clocks, and handles reset management. It also manages GPIO levels during sleep
mode and emergency self-refresh of SDRAM.
The PMU controls the external voltage regulator, in order to change its settings in different
modes. In deep-sleep mode, only GPIOs, real-time clock (RTC), system and reset controller
(SRC), PMU and secured RAM remain in operation.
Voltage scaling supports two modes: standard 1.2 V and overdrive 1.4 V.
The family of power manager ICs, STw481x companion chips, seamlessly interface with the
Nomadik STn8815A09 and optimize global system power consumption leveraging on the
PMU.
2.6
ARM926EJ processor
The STn8815A09 CPU is an ARM926EJ reduced instruction set computer (RISC)
processor. This 32-bit processor core supports 32-bit ARM and 16-bit Thumb instruction
sets, enabling the user to trade off between high performance and high code density.
The cached ARM CPU features a memory management unit (MMU) and is clocked at a
frequency up to 350 MHz. It has a 16-Kbyte instruction cache, a 16-Kbyte data cache, and a
128-Kbyte level 2 cache, and supports the Jazelle™ extensions for Java acceleration.
It also includes an embedded trace module (ETM Medium+) for real-time CPU activity
tracing and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed
trace mode, with normal or half-rate clock.
2.7
2.8
Embedded memory units
●
32 Kbytes of public ROM (for boot purposes),
●
64 Kbytes of secured ROM (for security purposes),
●
512 Kbytes of public RAM,
●
16 Kbytes of secured RAM (for security code and/or data),
●
1 Kbyte backup.
Advanced security
The device contains 64 Kbytes of ROM and 16 Kbytes of RAM that are only accessible
when the system is in a trusted environment. An advanced security framework enables
M-commerce as well as authentication applications drawing on ST smart card expertise:
12/21
●
SHA-1/MD5/AES/DES/3DES hardware accelerators,
●
True random number generator (RNG),
●
Secured watchdog timer,
●
Unique die identification.
STn8815A09
2.9
Architecture overview
Flexible static memory controller (FSMC)
The FSMC interfaces to off-chip multiplexed burst NOR Flash memory devices and NAND
Flash memory devices, and to CompactFlash/CF+ cards. The FSMC manages up to 4 chipselects of NOR Flash memories, and up to 2 chip-selects of NAND Flash memories or
CompactFlash/CF+ devices. The memory controller features error code correction
accelerated by hardware that reduces host CPU workload to support NAND Flash very fast
read/write transfers.
2.10
SDRAM memory controller (SDMC)
The SDMC is used to interface with simple-data rate synchronous dynamic random access
memory (SDR-SDRAM) and double-data rate (DDR) SDRAM (133 MHz in standard mode
and 166 MHz in overdrive mode). The SDMC manages up to two chip-selects of 16-bit wide
SDR-SDRAM or DDR-SDRAM. It can address up to 1 Gbits of SDRAM.
2.11
Real time clock (RTC)
The RTC provides a 1-second resolution clock. This keeps time when the system is inactive
and can be used to wake the system up when a programmed alarm time is reached. It has a
clock trimming feature to compensate for the accuracy of the 32.768 kHz crystal and a
secured time update.
2.12
Timers
The STn8815A09 provides eight 16- or 32-bit (configurable) timers, as two groups of four.
They generate the periodic and timed interrupts required by OS services.
2.13
Watchdog timer
This OS resource is used to trigger a system reset in the event of software failure.
2.14
Vectored interrupt controller (VIC)
The VIC allows the OS interrupt handler to quickly dispatch interrupt service routines in
response to peripheral interrupts. There are 64 interrupt lines and the VIC uses a separate
bit position for each interrupt source. Software controls each request line to generate
software interrupts.
2.15
System and reset controller (SRC)
The SRC provides a control interface for clock generation components external to the
subsystem. It also controls system-wide and peripheral-specific energy management
features.
13/21
Architecture overview
2.16
STn8815A09
Direct memory access (DMA) controllers
Direct memory accesses can be employed for data transfers involving DMA peripherals. A
DMA controller services FIFO fill/empty requests from these peripherals immediately
without CPU interaction. Peripheral-to-peripheral and memory-to-memory DMAs are also
supported. A multichannel DMA controller is provided for efficient and concurrent data
transfers.
2.17
Universal asynchronous receivers-transmitters (UARTs)
The STn8815A09 provides three autobaud UARTs, one of which offers all modem
control/status signals. They are enhanced versions of the industry-standard 16C550 UART
with a high data rate up to 6 Mbit/s and an embedded hardware Xon/Xoff handshake.
2.18
Synchronous serial port (SSP)
The STn8815A09 provides one SSP for synchronous serial communication with external
peripherals. SPI, MicroWire and TI protocols are supported, with programmable word length
of up to 32 bits and data rate up to 24 Mbit/s.
The SSP has the following features in both master and slave configurations:
2.19
●
Parallel-to-serial conversion of data written to an internal, 32-bit wide, 32-location deep,
transmit FIFO.
●
Serial-to-parallel conversion of received data, which is buffered in a 32-bit wide, 32location deep, receive FIFO.
●
Programmable data frame size from 4 to 32 bits.
●
Programmable clock bit rate and prescaler.
●
Programmable clock phase and polarity in SPI mode.
●
Support for direct memory accesses.
●
Support for serial LCD smart panels.
Camera interfaces
●
2.20
3 camera interfaces that can be selected alternately:
–
2 serial SMIA CCP2 camera interfaces (mutually exclusive): up to 650 Mbit/s data
strobe,
–
Parallel camera CCIR-656 interface up to 80-MHz with embedded/external sync.
●
Direct support of 8-bit and 10-bit raw Bayer RGB data formats.
●
High resolution up to 5 Mpixels for camera sensors (raw Bayer data).
●
Unlimited resolution for camera modules with JPEG compression.
TV interface
The STn8815A09 interfaces seamlessly with the STw8009 companion-chip, which performs
signal conversion and connects directly to a TV set.
The TV interface is compatible with video and S-video.
14/21
STn8815A09
2.21
Architecture overview
Liquid crystal display controller (LCDC)
This interface drives LCD panels, and supports the following displays:
●
STN displays: single- or dual-panel with 8-bit color and 4- or 8-bit monochrome,
●
TFT displays: 12-, 16-, 18- and 24-bit color.
The resolution can be set as follows:
●
1-, 2- or 4-bits-per-pixel (bpp) palettized for mono STN,
●
1-, 2-, 4- or 8-bpp palettized for color STN and TFT,
●
16-bpp true-color non-palettized for color STN and TFT,
●
24-bpp packed and non-packed true-color (non-palettized) for color TFT.
The interface supports frame modulation and directly supports Sharp HR-TFT panels.
2.22
Master display interface (MDIF)
This interface drives LCD display modules, that is, panels that include their own display
memory and perform LCD panel refresh themselves. The MDIF is a parallel bidirectional
interface that can send commands or data to or read data from the display panel logic. It has
a DMA engine to automatically fetch data/commands from main memory without CPU
intervention.
In addition, the MDIF includes a submode to drive serial LCD smart panels.
2.23
Pulse width light modulator (PWL)
The PWL provides control of LCD backlighting. It produces a series of pulses that are fed to
the backlighting, where the width (or duty cycle) of the pulses determines the perceived
lighting level. An 8-bit random sequence generator decreases the spectral power at the
modulator harmonic frequencies.
2.24
General purpose inputs/outputs (GPIOs)
The STn8815A09 provides 124 programmable inputs or outputs that have switchable pull-up
and pull-down resistors and are controllable in two modes:
●
Software mode through an APB bus interface,
●
Hardware mode through a hardware control interface.
The GPIO interface provides the following individually programmable functions.
●
Any number of pins may be configured as interrupt sources.
●
Debouncing logic can be enabled for each GPIO to filter out glitches on I/Os.
●
Any GPIO may be used to wake up the device from sleep mode independent of
interrupt programming, and the input level that triggers wake-up is definable for each
enabled GPIO.
15/21
Architecture overview
2.25
STn8815A09
Memory card interface (MMC/SD/MS)
This interface can directly control one of the following memory cards:
●
SD card (without encryption/decryption logic),
●
MultiMediaCard (high-speed rate 96 Mbit/s),
●
Memory Stick and Memory Stick Pro.
It also supports several of each card type using the GPIOs for card selection.
2.26
USB-OTG high-speed interface
The STn8815A09 provides two USB-OTG high-speed interfaces. The USB-OTG features:
2.27
●
High-speed signalling rate at 480 Mbit/s.
●
Support for full-speed (12 Mbit/s) signaling bit rate.
●
Support for session request protocol (SRP) and host negotiation protocol (HNP).
●
Up to 16 bidirectional endpoints plus control endpoint 0.
●
A digital interface to external PHY, such as the AOC018 companion chip.
●
ULPI v1.1 compliant interface and ULPI DDR support.
●
Backward compatibility with the STw481x family of power-manager ICs at full speed.
I2C bus interface
The STn8815A09 provides three I²C bus interfaces, one of which is dedicated to the smart
imaging accelerator. The I²C interfaces support the following features:
●
Slave transmitter/receiver and master transmitter/receiver modes.
●
Multi-master capability.
●
10-bit addressing.
●
Standard (100 kHz) and fast (400 kHz) speeds.
●
Compliance with I²C standards.
In addition to receiving and transmitting data, the interface converts data from serial to
parallel format and vice-versa using an interrupt or polled handshake.
2.28
Fast IrDA interface (FIrDA)
This interface supports IrDA half-duplex communications. It performs modulation and
demodulation of infrared signals, and the wrapping of IrLAP frames. The IrDA interface
supports the following infrared modes and baud rates:
16/21
●
Serial infrared (SIR): 9.6 Kbit/s, 19.2 Kbit/s, 38.4 Kbit/s, 57.6 Kbit/s and 115.2 Kbit/s,
●
Medium infrared (MIR): 576 Kbit/s and 1.152 Mbit/s,
●
Fast infrared (FIR): 4 Mbit/s.
STn8815A09
2.29
Architecture overview
Multichannel serial ports (MSP)
The STn8815A09 includes 4 MSP synchronous receive and transmit serial interfaces. The
MSPs support a data rate of up to 48 Mbit/s with the following features:
●
Philips I²S format: left aligned with one cycle between leading edge of frame
synchronization and first data bit, 16 or 24 bits per sample.
●
Sony format: right aligned, 48 cycles per frame, 16 or 24 bits per sample.
●
Matsushita format: right aligned, 64 cycles per frame, 16 or 24 bits per sample.
●
Programmable number of bit-clock cycles per frame: 32, 48 or 64.
●
Programmable polarity of bit-clock and frame synchronization.
●
Programmable number of bits per sample: 16, 18, 20 or 24 bits.
They also provide:
2.30
2.31
●
µ-Law and A-Law compressing/expanding,
●
Independent framing and clocking for receive and transmit.
●
External shift clock or an internal, programmable frequency shift clock for data transfer.
●
Support for DMA transfers.
Scroll key and keypad encoder (SKE) interface
●
This interface supports up to 2 scroll-key inputs such as jog-dials or thumb wheels.
●
The keypad interface supports auto-scanning with debouncing of a keypad matrix up to
8 x 8.
High-speed serial interface (HSI)
The STn8815A09 includes two full-duplex high-speed serial interfaces (MIPI legacy
specification). These high-speed, 8-channel interfaces operate at up to 110 Mbit/s.
2.32
Host port interface (HPI)
The host port interface features:
●
16-bit parallel data bus.
●
Multiplexed or non-multiplexed address/data bus.
●
Indirect host access.
●
Direct host access to a segment of STn8815A09 memory in multiplexed mode.
17/21
Package mechanical data
3
STn8815A09
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Table 1.
Ref.
Package dimensions
Min
A
Typ
Max
Unit
-
1.00
mm
A1
0.125
-
-
mm
A2
-
0.775
-
mm
A3
0.19
A4
0.60
mm
b
0.22
0.26
0.30
mm
D
8.95
9.00
9.05
mm
D1
E
18/21
mm
8.00
8.95
9.00
mm
9.05
mm
E1
8.00
mm
e
0.40
mm
F
0.50
mm
ddd
0.08
mm
eee
0.13
mm
fff
0.04
mm
STn8815A09
Package mechanical data
Figure 4.
VFBGA 9.0mm x 9.0mm x 1.0mm 329 3R21x21 pitch 0.4mm ball 0.25
Note:
The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink
or metallized markings, or other feature of package body or integral heatslug.
A distinguishing feature is allowable on the bottom surface of the package to identify the
terminal A1 corner. Exact shape of each corner is optional.
19/21
Ordering information
4
STn8815A09
Ordering information
Table 2.
Order codes
Part number
Package
STN8815D0A09H11
5
VFBGA 9mm x 9mm x 1.0mm, 0.4mm pitch
Tray
Revision history
Table 3.
20/21
Packing
Document revision history
Date
Revision
Changes
20-Jul-2007
1
Initial release
28-Jan-2008
2
Updated the maximum ARM926EJ® frequency value on the cover
page and in Chapter 1: STn8815A09 overview.
STn8815A09
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2008 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
21/21