STMICROELECTRONICS STP40NF03L_07

STP40NF03L
N-channel 30V - 0.018Ω - 40A - TO-220
STripFET™ Power MOSFET
General features
■
Type
VDSS
RDS(on)
ID
STP40NF03L
30V
<0.022Ω
40A
Low threshold device
Description
3
1
This Power MOSFET is the latest development of
STMicroelectronics unique "Single Feature
Size™" strip-based process. The resulting
transistor shows extremely high packing density
for low on-resistance, rugged avalanche
characteristics and less critical alignment steps
therefore a remarkable manufacturing
reproducibility.
2
TO-220
Internal schematic diagram
Applications
■
Switching application
Order codes
Part number
Marking
Package
Packaging
STP40NF03L
P40NF03L
TO-220
Tube
February 2007
Rev 4
1/12
www.st.com
12
Contents
STP40NF03L
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................. 6
3
Test circuit
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
................................................ 8
STP40NF03L
1
Electrical ratings
Electrical ratings
Table 1.
Absolute maximum ratings
Symbol
Parameter
VDS
Drain-source voltage (VGS = 0)
VGS
Gate- source voltage
Value
Unit
30
V
± 16
V
ID
Drain current (continuous) at TC = 25°C
40
A
ID
Drain current (continuous) at TC = 100°C
28
A
Drain current (pulsed)
160
A
Total dissipation at TC = 25°C
70
W
Derating Factor
0.46
W/°C
Single pulse avalanche energy
250
mJ
-55 to 175
°C
IDM
(1)
Ptot
EAS (2)
Tstg
Tj
Storage temperature
Max. operating junction temperature
1. Pulse width limited by safe operating area.
2. Starting Tj = 25 °C, ID = 20A, VDD = 15V
Table 2.
Thermal data
Rthj-case
Thermal resistance junction-case max
2.1
°C/W
Rthj-amb
Thermal resistance junction-ambient max
62.5
°C/W
TJ
Maximum lead temperature for soldering
purpose
300
°C
3/12
Electrical characteristics
2
STP40NF03L
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 3.
On/off states
Symbol
Parameter
V(BR)DSS
Drain-source
breakdown voltage
ID = 250µA, VGS =0
IDSS
Zero gate voltage
drain current (VGS = 0)
VDS = max ratings
VDS = max ratings,
TC = 125°C
IGSS
Gate-body leakage
current (VDS = 0)
VGS = ±16V
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250µA
RDS(on)
Static drain-source on
resistance
VGS = 10V, ID = 20A
VGS = 4.5V, ID = 20A
Table 4.
Symbol
Test conditions
Typ.
Max.
30
1
Unit
V
1
10
µA
µA
±100
nA
1.7
2.5
V
0.018
0.028
0.022
0.035
Ω
Ω
Typ.
Max.
Unit
Dynamic
Parameter
Test conditions
Min.
gfs (1)
Forward
transconductance
VDS = 10V, ID = 20A
20
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 25V, f = 1MHz,
VGS = 0
770
255
60
pF
pF
pF
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
VDD = 15V, ID = 20A
RG = 4.7Ω VGS = 4.5V
(see Figure 13)
14
80
25
16
ns
ns
ns
ns
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 15V, ID = 40A,
VGS = 4.5V
(see Figure 14)
10.5
4
4.5
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%.
4/12
Min.
15
nC
nC
nC
STP40NF03L
Electrical characteristics
Table 5.
Symbol
Source drain diode
Parameter
ISDM (1)
Source-drain current
Source-drain current
(pulsed)
VSD (2)
Forward on voltage
ISD
trr
Qrr
IRRM
Test conditions
Min.
Typ.
ISD = 40A, VGS = 0
ISD = 40A,
Reverse recovery time
di/dt = 100A/µs,
Reverse recovery charge
VDD = 15V, Tj = 150°C
Reverse recovery current
(see Figure 15)
34.5
30
2
Max.
Unit
40
160
A
A
1.5
V
ns
nC
A
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
5/12
Electrical characteristics
STP40NF03L
2.1
Electrical characteristics (curves)
Figure 1.
Safe operating area
Figure 2.
Thermal impedance
Figure 3.
Output characteristics
Figure 4.
Transfer characteristics
Figure 5.
Transconductance
Figure 6.
Static drain-source on resistance
6/12
STP40NF03L
Electrical characteristics
Figure 7.
Gate charge vs. gate-source voltage Figure 8.
Figure 9.
Normalized gate threshold voltage
vs. temperature
Figure 11. Source-drain diode forward
characteristics
Capacitance variations
Figure 10. Normalized on resistance vs.
temperature
Figure 12. Normalized BVDSS vs. temperature
7/12
Test circuit
3
STP40NF03L
Test circuit
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
Figure 15. Test circuit for inductive load
Figure 16. Unclamped Inductive load test
switching and diode recovery times
circuit
Figure 17. Unclamped inductive waveform
8/12
Figure 18. Switching time waveform
STP40NF03L
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
9/12
Package mechanical data
STP40NF03L
TO-220 MECHANICAL DATA
DIM.
mm.
MIN.
inch
MAX.
MIN.
TYP.
MAX.
A
4.40
4.60
0.173
0.181
b
0.61
0.88
0.024
0.034
b1
1.15
1.70
0.045
0.066
c
0.49
0.70
0.019
0.027
D
15.25
15.75
0.60
0.620
E
10
10.40
0.393
0.409
e
2.40
2.70
0.094
0.106
e1
4.95
5.15
0.194
0.202
F
1.23
1.32
0.048
0.052
H1
6.20
6.60
0.244
0.256
J1
2.40
2.72
0.094
0.107
0.551
L
13
14
0.511
L1
3.50
3.93
0.137
L20
16.40
L30
10/12
TYP
0.154
0.645
28.90
1.137
øP
3.75
3.85
0.147
0.151
Q
2.65
2.95
0.104
0.116
STP40NF03L
5
Revision history
Revision history
Table 6.
Revision history
Date
Revision
Changes
09-Sep-2004
1
Preliminary version
21-Jun-2005
2
Complete version with curves
16-Aug-2006
3
New template, no content change
21-Feb-2007
4
Typo mistake on page 1
11/12
STP40NF03L
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