STS15N4LLF3 N-channel 40V - 0.0042Ω - 15A - SO-8 STripFET™ Power MOSFET General features Type VDSS RDS(on) ID STS15N4LLF3 40V <0.005Ω 15A ■ Optimal RDS(on)x Qg trade-off @ 4.5V ■ Conduction losses reduced ■ Switching losses reduced SO-8 Description This N-channel enhancement mode Power MOSFET is the latest refinement of STMicroelectronic unique “Single Feature Size™“ strip-based process with less critical aligment steps and therefore a remarkable manufacturing reproducibility. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and low gate charge. Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STS15N4LLF3 15N4LL- SO-8 Tape & reel November 2006 Rev 2 1/12 www.st.com 12 Contents STS15N4LLF3 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history 2/12 ................................................ 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 STS15N4LLF3 Electrical ratings 1 Electrical ratings Table 1. Symbol Absolute maximim ratings Parameter Value Unit 40 V VDS Drain-source voltage (VGS = 0) VGS Gate-source voltage ± 16 V Gate- source voltage ±18 V ID Drain current (continuous) at TC = 25°C 15 A ID Drain current (continuous) at TC = 100°C 9.3 A Drain current (pulsed) 60 A Total dissipation at TC = 25°C 2.7 W Single pulse avalanche energy 2 J Value Unit 47 °C/W Maximum lead temperature for soldering -55 to 150 °C Storage temperature -55 to 150 °C (1) VGS IDM (2) PTOT EAS (3) 1. Guaranteed for test time < 15ms 2. Pulse width limited by Tjmax 3. Starting Tj =25°C, ID =7.5A, VDD =25V Table 2. Symbol Thermal resistance Parameter Rthj-pcb(1) Thermal resistance junction-pcb max Tl Tstg 1. When mounted of FR-4 board with 1 inch2 pad, 2oz of Cu and t< 10sec 3/12 Electrical characteristics 2 STS15N4LLF3 Electrical characteristics (TJ = 25 °C unless otherwise specified) Table 3. Symbol Parameter Test conditions Min. Typ. Max. Unit Drain-source breakdown voltage ID = 250µA, VGS= 0 IDSS Zero gate voltage drain current (VGS = 0) VDS = max rating, VDS =max rating @125°C 10 100 µA µA IGSS Gate body leakage Current (VDS = 0) VGS = ±16V ±200 nA VGS(th) Gate threshold voltage VDS= VGS, ID = 250µA RDS(on) Static drain-source on resistance VGS= 10V, ID= 7.5A VGS= 4.5V, ID= 7.5A V(BR)DSS Table 4. Symbol 40 V 1 V 0.0042 0.005 0.005 0.007 Ω Ω Dynamic Parameter Test conditions Min. Typ. Max. Unit Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS = 25V, f=1 MHz, VGS= 0 2530 574 29 Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 20V, ID = 15A VGS = 4.5V (see Figure 13) 21.5 6.9 8.2 28 nC nC nC Gate input resistance f=1 MHz Gate DC Bias = 0 Test signal level = 20mV open drain 1 3 5 Ω Test conditions Min. Typ. Max. Unit RG Table 5. Symbol 4/12 On/off states pF pF pF Switching times Parameter td(on) tr Turn-on delay time Rise time VDD = 20V, ID = 7.5A, RG = 4.7Ω, VGS = 10V (see Figure 15) 17 25 ns ns td(off) tf Turn-off delay time Fall time VDD = 20V, ID = 7.5A, RG = 4.7Ω, VGS = 10V (see Figure 15) 62 9 ns ns STS15N4LLF3 Electrical characteristics Table 6. Source drain diode Symbol Parameter ISD ISDM(1) Source-drain current Source-drain current (pulsed) VSD (2) Forward on voltage ISD = 15A, VGS = 0 Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 15A, VDD = 30V, di/dt = 100A/µs, Tj = 150°C (see Figure 14) trr Qrr IRRM Test conditions Min. Typ. 43 64 3 Max. Unit 15 60 A A 1.2 V ns nC A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300µs, duty cycle 1.5% 5/12 Electrical characteristics STS15N4LLF3 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Normalized BVDSS vs temperature Figure 6. Static drain-source on resistance 6/12 STS15N4LLF3 Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs temperature Capacitance variations Figure 10. Normalized on resistance vs temperature Figure 11. Source-drain diode forward characteristics 7/12 Test circuit 3 STS15N4LLF3 Test circuit Figure 12. Switching times test circuit for resistive load Figure 13. Gate charge test circuit Figure 14. Test circuit for inductive load Figure 15. Unclamped Inductive load test switching and diode recovery times circuit Figure 16. Unclamped inductive waveform 8/12 Figure 17. Switching time waveform STS15N4LLF3 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: twww.st.com 9/12 Package mechanical data STS15N4LLF3 SO-8 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. TYP. 1.75 0.1 MAX. 0.068 0.25 a2 0.003 0.009 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 c1 45 (typ.) 1.27 e e3 3.81 0.150 3.8 4.0 0.14 L 0.4 1.27 0.015 S 0.244 0.050 F M 10/12 MIN. 0.6 0.157 0.050 0.023 8 (max.) STS15N4LLF3 Revision history 5 Revision history Table 7. Revision history Date Revision Changes 09-Jun-2006 1 First release 22-Nov-2006 2 Corrected part number 11/12 STS15N4LLF3 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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