STMICROELECTRONICS STS17NF3LL

STS17NF3LL
N-channel 30V - 0.0045Ω - 17A - SO-8
STripFET™ II Power MOSFET for DC-DC conversion
General features
Type
VDSS
RDS(on)
ID
STS17NF3LL
30V
<0.0055Ω
17A
■
Optimal RDS(on) x Qg trade-off @ 4.5V
■
Conduction losses reduced
■
Switching losses reduced
SO-8
Description
This application specific Power MOSFET is the
second generation of STMicroelectronis unique
"Single Feature Size™" strip-based process. The
resulting transistor shows the best trade-off
between on-resistance and gate charge. Such
features make it the best choice in high efficiency
DC-DC converters for Telecom and computer
industries.
Internal schematic diagram
Applications
■
Switching application
Order codes
Part number
Marking
Package
Packaging
STS17NF3LL
S17NF3LL
SO-8
Tape & reel
October 2006
Rev 5
1/12
www.st.com
12
Contents
STS17NF3LL
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................. 6
3
Test circuit
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
................................................ 8
STS17NF3LL
1
Electrical ratings
Electrical ratings
Table 1.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage (VGS = 0)
30
V
VGS
Gate-source voltage
±18
V
ID
Drain current (continuous) at TC = 25°C
17
A
ID
Drain current (continuous) at TC = 100°C
12
A
Drain current (pulsed)
68
A
Total dissipation at TC = 25°C
3.2
W
IDM
(1)
PTOT
1. Pulse width limited by safe operating area
Table 2.
Thermal data
Rthj-amb
Thermal resistance junction-ambient max (1)
47
°C/W
Rthj-lead
Thermal resistance junction-leads max
16
°C/W
Maximum operating junction temperature
-55 to 175
°C
Storage temperature
-55 to175
°C
Tj
Tstg
1. When mounted on FR-4 board of 1in², 2oz Cu. t<10sec
3/12
Electrical characteristics
2
STS17NF3LL
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 3.
On/off states
Symbol
Parameter
V(BR)DSS
Drain-source
breakdown voltage
ID = 250µA, VGS =0
IDSS
Zero gate voltage
drain current (VGS = 0)
VDS = max rating
VDS =max rating,
TC = 125°C
IGSS
Gate-body leakage
current (VDS = 0)
VGS = ± 18V
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250µA
RDS(on)
Static drain-source on
resistance
VGS = 10V, ID = 8.5A
VGS = 4.5V, ID = 8.5A
Table 4.
Symbol
Test conditions
Typ.
Max.
30
Unit
V
1
10
µA
µA
±100
nA
1
V
0.0045
0.0055
0.0055
0.007
Ω
Ω
Typ.
Max.
Unit
Dynamic
Parameter
Test conditions
Min.
gfs (1)
Forward
transconductance
VDS = 10V, ID = 8.5A
37
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 25V, f = 1MHz,
VGS = 0
2160
614
98
pF
pF
pF
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
VDD = 15V, ID = 8.5A
RG = 4.7Ω VGS = 4.5V
(see Figure 13)
23.5
39
47.5
37
ns
ns
ns
ns
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 24V, ID = 12.5A,
VGS = 4.5V, RG = 4.7Ω
(see Figure 14)
26
7
12
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
4/12
Min.
35
nC
nC
nC
STS17NF3LL
Electrical characteristics
Table 5.
Symbol
Source drain diode
Parameter
ISDM (1)
Source-drain current
Source-drain current
(pulsed)
VSD (2)
Forward on voltage
ISD
trr
Qrr
IRRM
Test conditions
Min.
Typ.
ISD = 17A, VGS = 0
Reverse recovery time
ISD = 17A, di/dt = 100A/µs,
Reverse recovery charge VDD = 15V; Tj = 150°C
Reverse recovery current (see Figure 15)
39
45
2.3
Max.
Unit
17
68
A
A
1.2
V
ns
nC
A
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
5/12
Electrical characteristics
STS17NF3LL
2.1
Electrical characteristics (curves)
Figure 1.
Safe operating area
Figure 2.
Thermal impedance
Figure 3.
Output characterisics
Figure 4.
Transfer characteristics
Figure 5.
Transconductance
Figure 6.
Static drain-source on resistance
6/12
STS17NF3LL
Electrical characteristics
Figure 7.
Gate charge vs gate-source voltage Figure 8.
Figure 9.
Normalized gate threshold voltage
vs temperature
Figure 11. Source-drain diode forward
characteristics
Capacitance variations
Figure 10. Normalized on resistance vs
temperature
Figure 12. Normalized breakdown voltage vs
temperature
7/12
Test circuit
3
STS17NF3LL
Test circuit
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
Figure 15. Test circuit for inductive load
Figure 16. Unclamped Inductive load test
switching and diode recovery times
circuit
Figure 17. Unclamped inductive waveform
8/12
Figure 18. Switching time waveform
STS17NF3LL
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
9/12
Package mechanical data
STS17NF3LL
SO-8 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
TYP.
1.75
0.1
MAX.
0.068
0.25
a2
0.003
0.009
1.65
0.064
a3
0.65
0.85
0.025
0.033
b
0.35
0.48
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.25
0.5
0.010
0.019
D
4.8
5.0
0.188
0.196
E
5.8
6.2
0.228
c1
45 (typ.)
1.27
e
e3
3.81
0.150
3.8
4.0
0.14
L
0.4
1.27
0.015
S
0.244
0.050
F
M
10/12
MIN.
0.6
0.157
0.050
0.023
8 (max.)
STS17NF3LL
5
Revision history
Revision history
Table 6.
Revision history
Date
Revision
Changes
21-Jun-2004
4
Complete document
04-Oct-2006
5
New template, no content change
11/12
STS17NF3LL
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