STSJ50NH3LL N-channel 30V - 0.008Ω - 12A - PowerSO-8™ Ultra low gate charge STripFET™ Power MOSFET General features Type VDSS RDS(on) ID STSJ50NH3LL 30V < 0.0105Ω 12A(1) ■ Optimal RDS(on) x Qg trade-off @ 4.5V ■ Reduced switching losses ■ Reduced conduction losses ■ Improved junction-case thermal resistance PowerSO-8™ Description This series utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology, and a propriertary process for integrating a monolithic Scottky diode. The new Power MOSFET is optimized for the most demanding synchronous switch function in DC-DC converter for Computer and Telecom. Internal schematic diagram Applications ■ Switching application DRAIN CONTACT ALSO ON THE BACKSIDE Order codes Part number Marking Package Packaging STSJ50NH3LL 50H3LL- PowerSO-8 Tape & reel April 2006 Rev 5 1/13 www.st.com 13 Contents STSJ50NH3LL Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 ................................................ 9 STSJ50NH3LL 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit Drain-source voltage (VGS = 0) 30 V VGS(1) Gate-source voltage ±16 V VGS(2) Gate-source voltage ±18 V ID(4) Drain current (continuous) at TC = 25°C 50 A ID(3) Drain current (continuous) at TC=25°C 12 A ID(4) Drain current (continuous) at TC=100°C 31.3 A ID(3) Drain current (continuous) at TC=100°C 7.5 A Drain current (pulsed) 48 A Total dissipation at T C = 25°C Total dissipation at T C = 25°C (4) 3 50 W W Operating junction temperature Storage temperature -55 to 150 °C VDS IDM(5) (3) PTOT TJ Tstg 1. Continuous mode 2. Guaranteed for test time < 15ms 3. This value is rated accordingly to Rthj-pcb 4. This value is rated accordingly to Rthj-c 5. Pulse width limited by safe operating area Table 2. Symbol Thermal resistance Parameter Value Unit Rthj-c Thermal resistance junction-case Max 2.5 °C/W Rthj-pcb(1) Thermal resistance junction-pcb Max 42 °C/W Value Unit 1. When mounted on 1 inch² FR-4 board, 2oz Cu (t<10sec.) Table 3. Symbol Avalanche data Parameter IAV Not repetitive avalanche current (pulse width limited by Tjmax) 6 A EAS Single pulse avalanche energy (starting Tj=25°C, ID=IAV, VDD=24V) 800 mJ 3/13 Electrical characteristics 2 STSJ50NH3LL Electrical characteristics (TCASE=25°C unless otherwise specified) Table 4. Symbol V(BR)DSS On/off states Parameter Drain-source breakdown voltage Test condictions ID = 250µA, V GS= 0 Zero gate voltage drain current (V GS = 0) IGSS Gate body leakage current (V DS = 0) VGS = ±16V VGS(th) Gate threshold voltage VDS= VGS, ID =250µA RDS(on) Static drain-source on resistance VGS= 10V, ID= 6A VGS= 4.5V, ID= 6A RDS(on) Static drain-source on resistance VGS= 4.5V, ID= 6A @125°C Symbol gfs (1) Ciss Coss Crss Qg 30 1 10 µA µA ±100 nA 1 V 0.008 0.010 VGS= 10V, ID= 6A @125°C Unit V VDS = Max rating TC=125°C Parameter Test Condictions 0.0105 0.013 Ω Ω Ω Ω 0.012 0.016 Min. Typ. Max. Unit Forward transconductance VDS =10V, ID = 12A 38 S Input capacitance Output capacitance Reverse transfer capacitance VDS =25V, f=1MHz, VGS=0 965 285 38 pF pF pF Qgd RG Gate input resistance VDD=15V, ID =12A VGS =4.5V,(see Figure 15) f=1MHz Gate DC Bias=0 Test signal level =20mv open drain 1. Pulsed: pulse duration=300µs, duty cycle 1.5% 4/13 Max. Dynamic Total gate charge Gate-source charge Gate-drain charge Qgs Typ. VDS = Max rating IDSS Table 5. Min. 0.5 9 3.7 3 12 nC nC nC 1.5 2.5 Ω STSJ50NH3LL Electrical characteristics Table 6. Switching times Symbol Parameter td(on) tr td(off) tf Table 7. Symbol Turn-on delay time Rise time Turn-off delay time Fall time Test condictions VDD =15V, ID=6A, RG=4.7Ω, VGS=4.5V (see Figure 14) VDD =15V, ID=6A, RG=4.7Ω, VGS=4.5V (see Figure 14) Parameter Test Condictions ISDM(1) VSD(2) Forward on voltage ISD=12A, VGS=0 Reverse recovery time Reverse recovery charge Reverse recovery current ISD=12A, di/dt = 100A/µs, VDD=20V, Tj=150°C trr Qrr IRRM Typ. Max. Unit 15 32 ns ns 18 8.5 ns ns Source drain diode Source-drain current Source-drain current (pulsed) ISD Min. (see Figure 19) Min. Typ. 24 17.4 1.45 Max. Unit 12 48 A A 1.3 V ns nC A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300µs, duty cycle 1.5% 5/13 Electrical characteristics STSJ50NH3LL 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/13 STSJ50NH3LL Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs temperature Figure 11. Source-drain diode forward characteristics Capacitance variations Figure 10. Normalized on resistance vs temperature Figure 12. Normalized BVDSS vs temperature 7/13 Electrical characteristics STSJ50NH3LL Figure 13. Allowable Iav vs time in avalanche The previous curve gives the single pulse safe operating area for unclamped inductive loads under the following conditions: PD(AVE) =0.5*(1.3*BV DSS *I AV ) EAS(AR) =PD(AVE) *tAV Where: IAV is the Allowable Current in Avalanche PD(AVE) is the Average Power Dissipation in Avalanche (Single Pulse) tAV is the Time in Avalanche 8/13 STSJ50NH3LL 3 Test circuit Test circuit Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test switching and diode recovery times circuit Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform 9/13 Package mechanical data 4 STSJ50NH3LL Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 10/13 STSJ50NH3LL Package mechanical data PowerSO-8™ MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.25 a2 MAX. 0.068 0.003 0.009 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 0.196 c1 45° (typ.) D 4.8 5.0 0.188 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 e4 2.79 0.110 F 3.8 4.0 0.14 0.157 L 0.4 1.27 0.015 0.050 M S 0.6 0.023 8° (max.) 11/13 Revision history 5 STSJ50NH3LL Revision history Table 8. 12/13 Revision history Date Revision Changes 21-Jul-2004 1 Initial release. 24-May-2005 2 New value on Table 6 23-Jun-2005 3 New Rg value on Table 6 16-Nov-2005 4 Complete version 03-Apr-2006 5 New template STSJ50NH3LL Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST, ST PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS, WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 13/13