STMICROELECTRONICS STSR2PCD-TR

STSR2P/
STSR2PM
FORWARD SYNCHRONOUS
RECTIFIERS SMART DRIVER
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SUPPLY VOLTAGE RANGE: 4.5V TO 5.5V
TYPICAL PEAK OUTPUT CURRENT:
SOURCE -2A, SINK 3.5A
OPERATING FREQUENCY: 20 TO 750 KHZ
SMART TURN-OFF ANTICIPATION TIMING
OPERATION INDEPENDENT FROM THE
FORWARD MAGNETIC RESET TECHNIQUE
POSSIBILITY TO OPERATE IN
DISCONTINUOUS MODE
SO-8
anticipation in turning-off the OUT GATE1 with
respect to the clock signal transition is provided,
while the anticipation in turning off the OUTGATE2
can be set through external components. The
adopted transitions revelation mechanism makes
circuit operation independent by the forward
magnetic reset technique used, avoiding most of
the common problems inherent in self-driven
synchronous rectifiers. A special Inhibit function
allows the shut-off of OUTGATE2. This feature
makes discontinuous conduction mode possible
and prevents the freewheeling mosfet from
sinking current from the output.
STSR2P automatically turns off the outputs when
duty-cycle is lower than 13%, while STSR2PM
works even at very low duty-cycle values.
DESCRIPTION
STSR2P Smart Driver IC provides two
complementary high current outputs to drive
Power Mosfets. The IC is dedicated to properly
drive secondary Synchronous Rectifiers in
medium power, low output voltage, high efficiency
Forward Converters. From a synchronizing clock
input, STSR2P generates two driving signals with
the self-setting of dead time between
complementary pulses. The IC operation prevents
secondary
side
shoot-through
conditions
providing proper timing at the outputs turn-off
transition. This smart function operates through a
fast cycle-after-cycle control logic mechanism
based on an internal high frequency oscillator,
synchronized by the clock signal. A fixed
SCHEMATIC DIAGRAM
Vcc
2
5.7V
+
BIAS
UVLO
CK 4
PEAK
DETECTOR
ANTICIPATION
SET
+
+
1 OUTGate1
HIGH
FREQUENCY
OSCILLATOR
INHIBIT 5
3 SETANT2
DIGITAL
CONTROL
OUTPUT
BUFFERS
7 OUTGate2
+
25mV
6
SGLGND
September 2003
8
PWRGND
1/12
STSR2P/STSR2PM
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
DC Input Voltage
VOUTGATE Max Gate Drive Output Voltage
VINHIBIT
Max INHIBIT Voltage (*)
VCK
Clock Input Voltage Range (*)
ILX
Switching Peak Current
Unit
-0.3 to 6
V
-0.3 to VCC
-0.6 to VCC
V
-0.3 to VCC
2
V
270
mW
V
A
±1
±0.9
KV
KV
Tstg
Continuous Power Dissipation at TA=105°C without heatsink
Human Body Model
Pins 1,2, 4, 5, 6, 7, 8
Pin 3
Storage Temperature Range
-55 to +150
°C
Top
Operating Junction Temperature Range
-40 to +125
°C
PTOT
ESD
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
(*) A higher positive voltage level can be applied to the pin with a resistor which limits the current flowing into the pin to 10mA maximum
THERMAL DATA
Symbol
SO-8
Unit
Rthj-amb
Thermal Resistance Junction-case
Parameter
40
°C/W
Rthj-amb
Thermal Resistance Junction-ambient (*)
160
°C/W
(*) This value is referred to one layer pcb board with minimum copper connections for the leads. a minimum value of 120 °C/W can be
obtained improving thermal conductivity of the board
ORDERING CODES
TYPE
SO-8
SO-8 (T&R)
STSR2P
STSR2PM
STSR2PCD
STSR2PMCD
STSR2PCD-TR
STSR2PMCD-TR
CONNECTION DIAGRAM (top view)
2/12
STSR2P/STSR2PM
PIN DESCRIPTION
Pin N°
Symbol
1
OUTGATE1
2
VCC
3
SETANT2
4
CK
5
INHIBIT
6
SGLGND
7
OUTGATE2
8
PWRGND
Name and Function
Gate Drive signal for Rectifier MOSFET. Anticipation (tANT1) in turning off
OUTGATE1 is provided when the clock input goes to low level.
The supply voltage range from 4.5V to 5.5V allows applications with logic gate
threshold mosfets. UVLO feature guarantees proper start-up while it avoids
undesirable driving during eventual dropping of the supply voltage.
The voltage on this pin sets the anticipation (tANT1) in turning off the OUTGATE2. It
is possible to choose among three different anticipation times by discrete
partitioning of the supply voltage.
This input provides synchronization for IC’s operations, being the transitions
between the two output conditions based on a positive threshold, equal for the
two slopes. A smart internal control logic mechanism using a 15MHz internal
oscillator generates proper anticipation timing at the turn-off of each output. This
feature allows safe turn-off of Synchronous Rectifiers avoiding any eventual
shoot-through situation on secondary side at both transitions. Smart clock
revelation mechanism makes these operations independent by false triggering
pulses generated in light load conditions and by particular demagnetization
techniques.Absolute maximum voltage rating of the pin can be exceeded limiting
the current flowing into the pin to 10mA max.
This input enables OUTGATE2 to work when its voltage is lower than the negative
threshold voltage (VINHIBIT<VH). If VINHIBIT>VH the OUTGATE2 will be high for a
minimum conduction time (tON(GATE2)). In typical forward converter application, it
is possible to turn off the freewheeling MOSFET when the current through it tends
to reverse, allowing discontinuous conduction mode and providing protection to
the converter from eventual sinking current from the load.Absolute maximum
voltage rating of the pin can be exceeded limiting the current flowing into the pin
to 10mA max.
Reference for all the control logic signals. This pin is completely separated from
the PWRGND to prevent eventual disturbances to affect the control logic.
Gate Drive signal for Freewheeling MOSFET. Anticipation [tANT2] in turning off
OUTGATE2 is provided when the clock input goes to high level.
Reference for power signals, this pin carries the full peak currents for the two
outputs.
3/12
STSR2P/STSR2PM
ELECTRICAL CHARACTERISTICS (VCC=5V, CK= 250kHz, VINHIBIT =-200mV, TJ =-40 to 125°C, unless
otherwise specified.)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
3.8
4
3.5
3.6
5.5
5.8
6
V
22
30
mA
3
5
0.10
0.16
SUPPLY INPUT AND UNDER VOLTAGE LOCK OUT
VCCON Start Threshold
VZ
Turn OFF Threshold After
Start
Zener Voltage
ICC
Unloaded Supply Current
VCCOFF
CK=0V
OUTGATE1,2= no load
CK=0V
GATE DRIVER OUTPUTS
VOL
Output Low Voltage
VOH
Output High Voltage
IOUT
tR
Output Source Peak
Current
Output Sink Peak Current
Output Series Source
Resistance
Output Series Sink
Resistance
OUTGATE1,2 Rise Time
tF
OUTGATE1,2 Fall Time
tP1
tP2
ROUT
OUTGATE1,2= no load
IOUTGATE1,2=-200mA
IOUTGATE1,2=200mA
4.70
V
V
V
4.85
V
2
A
IOUTGATE1,2=-200mA
3.5
0.75
1.5
IOUTGATE1,2=200mA
0.5
0.8
CLOAD=5nF (Note 1)
40
ns
CLOAD=5nF (Note 1)
30
ns
Clock Propagation Delay to No Load
Turn ON of OUTGATE1
130
ns
Clock Propagation Delay to No Load
Turn ON of OUTGATE2
50
ns
No Load
75
ns
VANT2 = 0 to 1/3VCC; no load
75
ns
VANT2 = 1/3VCC to 2/3VCC; no load
150
VANT2 = 2/3VCC to VCC; no load
225
TURN-OFF ANTICIPATION TIME
OUTGATE1 Turn-off
tANT1
Anticipation Time
OUTGATE2 Turn-off
tANT2
Anticipation Time
ISETANT2
IZ = 2mA
Unit
Leakage Current (Note 2)
-0.1
0.1
Ω
µA
INHIBIT OUTGATE2 ENABLE
VH
Threshold Voltage
TJ = 25°C
IH
Leakage Current (Note 2)
VINHIBIT = 200mV
-30
-25
mV
-400
nA
VINHIBIT = -200mV
tON(GATE2) OUTGATE1 Turn-off
Anticipation Time
Reference Voltage
VCK
ICK
DOFF
tPW
1
VINHIBIT = 200mVNo Load
250
TJ = 25°C
2.6
LX Leakage Current
Duty Cycle Shut Down
TJ = 25°C
for STSR2P
Duty Cycle Turn ON after
Shut Down
Minimum Pulse Width
TJ = 25°C
for STSR2P
STSR2PM
13
ns
2.8
V
600
µA
14
18
%
20
200
Note1: tR is measured between 10% and 90% of the final voltage; tF is measured between 90% and 10% on the initial voltage
Note2: Parameter guaranteed by design
4/12
µA
ns
STSR2P/STSR2PM
TIMING DIAGRAM
APPLICATION INFORMATION: STSR2 IN FORWARD CONVERTER SECONDARY SIDE
NOTES
1) Ceramic Capacitors C1 and C2 must be placed very close to the IC;
2) R1 and R2 set the anticipation time by partitioning the VCC voltage;
3) R3 and R4 is a resistor divider meant to provide the correct CK voltage range;
4) R5 limits the current flowing through diode D2 when Freewheeling drain voltage is high;
5) D1 could be necessary to protect INHIBIT pin from negative voltages.
6) D2 could be necessary to protect INHIBIT pin from voltages higher than VCC
7) D3 could be necessary to protect CK pin from voltages higher than VCC.
8) SGLGND layout trace must not include OUTGATE1,2 current paths.
9) A capacitor in parallel with R4 could be necessary to eliminate turn off voltage spike.
5/12
STSR2P/STSR2PM
EXAMPLE OF COMPONENTS SELECTION FOR A FORWARD CONVERTER
Forward Specification:
VIN=36-72V
VOUT=3.3V
n=Np/Ns=4.5
R3 and R 4 are calculated assuring a minimum voltage of 2.8V at CK pin. At 36V input, the voltage on the
secondary winding is 36/4.5=8V. Choosing R3=1.5KΩ, R4 results to be:
V CK × R 3
2.8V × ( 1.5 kΩ )
R 4 ≥ ---------------------------------------------------------------- = 1k Ω × -------------------------------------------------------------------------- = 862 Ω
8 V – 220µA × 1.5 kΩ – 2.8V
V IN – I CK ( 2.8 ) × R 3 – V CK
R4=1kΩ is chosen. At 72V input the current at CK pin is calculated as:
V IN ( max ) – V CC – 0.3
16 – 5 – 0.3
I CK = ----------------------------------------------------- = ------------------------------ = 7.13mA
R3
1.5kΩ
This value is below the maximum allowable current flowing into the CK pin (10mA). If the 10mA value is
exceeded an external diode connected to VCC must be added (D3).
R1 and R 2 values set the anticipation time for OUTGATE2. For R1=∞ and R2=0, tANT2=75ns; for
R1=R 2=10kΩ, tANT2=150ns; for R 1=0 and R2=∞, tANT2=225ns.
The RC group composed by R5 and the parasitic capacitance of Inhibit pin (typically 5pF) delays the
signal on Inhibit comparator. This delay must be lower than 200ns. This condition imposes a maximum
value for R5 of about 20kΩ.
In general a suggested value for R5 is 10kΩ. At 72V input, the secondary voltage is 16V, so the maximum
current flowing into Inhibit pin is 16V/10kΩ=1.6mA which is below the maximum allowable current for the
pin (10mA). If the 10mA value is exceeded an external diode (D2) connected to VCC must be added.
The maximum negative voltage of –0.6V must be guaranteed for the Inhibit pin. If this negative voltage is
exceeded the current must be limited to 50mA. If necessary, a diode (D1) connected to SGLGND can be
added to satisfy this specification.
INHIBIT OPERATION OF OUTGATE2 IN DISCONTINUOUS CONDUCTION MODE
6/12
STSR2P/STSR2PM
INHIBIT OPERATION OF OUTGATE2
NOTE: VINHIBIT =+200mV
7/12
STSR2P/STSR2PM
TYPICAL PERFORMANCE CHARACTERISTICS (unless otherwise specified Tj = 25°C
Figure 1 : Zener Characteristics
Figure 4 : Sink-Source ON Resistance vs
Temperature
Figure 2 : Rise and Fall Time vs Load Capacitor
Figure 5 : Clock Threshold Voltage vs
Temperature
Figure 3 : OUTGATE1,2 vs Characteristics
Figure 6 : INHIBIT Threshold Voltage vs
Temperature
8/12
STSR2P/STSR2PM
Figure 7 : Supply Current vs Load Capacitor
(each output)
Figure 10 : Duty Cycle Shut Down vs
Temperature
Figure 8 : Supply Current vs Clock Frequency
Figure 11 : Duty Cycle Turn ON After Shut Down
vs Temperature
Figure 9 : TON(GATE2) vs Temperature
Figure 12 : Clock Leakage Current vs Clock
Voltage
9/12
STSR2P/STSR2PM
SO-8 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
inch
MAX.
MIN.
TYP.
MAX.
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.04
0.010
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.00
0.150
0.157
e
1.27
0.050
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
k
ddd
8˚ (max.)
0.1
0.04
0016023/C
10/12
STSR2P/STSR2PM
Tape & Reel SO-8 MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
TYP
MAX.
MIN.
330
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
13.2
TYP.
0.504
22.4
0.519
0.882
Ao
8.1
8.5
0.319
0.335
Bo
5.5
5.9
0.216
0.232
Ko
2.1
2.3
0.082
0.090
Po
3.9
4.1
0.153
0.161
P
7.9
8.1
0.311
0.319
11/12
STSR2P/STSR2PM
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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