SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS SCLS121B – DECEMBER 1982 – REVISED MAY 1997 D D D D D Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs SN54HC191 . . . J OR W PACKAGE SN74HC191 . . . D OR N PACKAGE (TOP VIEW) B QB QA CTEN D/U QC QD GND description The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock (CLK) input if the count-enable (CTEN) input is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up, and when D/U is high, it counts down. 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC A CLK RCO MAX/MIN LOAD C D QB B NC VCC A SN54HC191 . . . FK PACKAGE (TOP VIEW) QA CTEN NC D/U QC 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 CLK RCO NC MAX/MIN LOAD QD GND NC D C The ’HC191 are 4-bit synchronous, reversible, up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (rippleclock) counters. 1 NC – No internal connection These counters feature a fully independent clock circuit. Change at the control (CTEN and D/U) inputs that modifies the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter is dictated solely by the condition meeting the stable setup and hold times. These counters are fully programmable; that is, each of the outputs can be preset to either level by placing a low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the level of CLK. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. Two outputs are available to perform the cascading function: ripple clock (RCO) and maximum/minimum (MAX/MIN) count. MAX/MIN produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down, or maximum (9 or 15) counting up. RCO produces a low-level output pulse under those same conditions, but only while CLK is low. The counters can be easily cascaded by feeding RCO to CTEN of the succeeding counter if parallel clocking is used, or to CLK if parallel enabling is used. MAX/MIN can be used to accomplish look ahead for high-speed operation. The SN54HC191 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74HC191 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS SCLS121B – DECEMBER 1982 – REVISED MAY 1997 logic symbol† CTEN 4 5 D/U G1 CTRDIV16 M2 [DOWN] 2(CT=0) Z6 M3 [UP] CLK 14 LOAD A B C D 15 1 10 9 1,2–/1,3+ 6,1,4 13 RCO C5 5D [1] [2] [4] [8] † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, and W packages. 2 MAX/MIN 3(CT=15) Z6 G4 11 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 2 6 7 QA QB QC QD SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS SCLS121B – DECEMBER 1982 – REVISED MAY 1997 logic diagram (positive logic) 12 CTEN 4 13 D/U 5 CLK 14 LOAD 11 A 15 S 3 C1 1D R B MAX/MIN RCO QA 1 S 2 QB C1 1D R C 10 S 6 C1 1D R D QC 9 S 7 QD C1 1D R Pin numbers shown are for the D, J, N, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS SCLS121B – DECEMBER 1982 – REVISED MAY 1997 typical load, count, and inhibit sequence The following sequence is illustrated below: 1. Load (preset) to binary 13 2. Count up to 14, 15 (maximum), 0, 1, and 2 3. Inhibit 4. Count down to 1, 0 (minimum), 15, 14, and 13 LOAD A Data Inputs B C D CLK D/U CTEN QA Data Outputs QB QC QD MAX/MIN RCO 13 14 15 0 1 2 2 Count Up Load POST OFFICE BOX 655303 1 0 15 14 Count Down Inhibit 4 2 • DALLAS, TEXAS 75265 13 SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS SCLS121B – DECEMBER 1982 – REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions SN54HC191 VCC Supply voltage VIH High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL Low-level input voltage VI VO Input voltage Output voltage tt‡ Input transition (rise and fall) time SN74HC191 MIN NOM MAX MIN NOM MAX 2 5 6 2 5 6 1.5 1.5 3.15 3.15 4.2 4.2 V V 0 0.5 0 0.5 0 1.35 0 1.35 0 1.8 0 1.8 0 0 0 VCC VCC 0 VCC VCC VCC = 2 V VCC = 4.5 V 0 1000 0 1000 0 500 0 500 VCC = 6 V 0 400 0 400 VCC = 4.5 V VCC = 6 V UNIT V V V ns TA Operating free-air temperature –55 125 –40 85 °C ‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS SCLS121B – DECEMBER 1982 – REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –20 µA VOH VI = VIH or VIL IOH = –4 mA IOH = –5.2 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci 6 VI = VCC or 0 VI = VCC or 0, IO = 0 VCC MIN TA = 25°C TYP MAX SN54HC191 MIN MAX SN74HC191 MIN 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 MAX UNIT V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 8 160 80 µA 3 10 10 10 pF 6V 2 V to 6 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS SCLS121B – DECEMBER 1982 – REVISED MAY 1997 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency LOAD low tw Pulse duration CLK high or low Data before LOAD↑ ↑ CTEN before CLK↑ ↑ tsu Setup time D/U before CLK↑ ↑ LOAD inactive before CLK↑ ↑ Data after LOAD↑ ↑ th Hold time CTEN after CLK↑ ↑ D/U after CLK↑ ↑ POST OFFICE BOX 655303 TA = 25°C MIN MAX SN54HC191 SN74HC191 MIN MAX MIN MAX 2V 0 4.2 0 2.8 0 3.3 4.5 V 0 21 0 14 0 17 6V 0 24 0 16 0 19 2V 120 180 150 4.5 V 24 36 30 6V 21 31 26 2V 120 180 150 4.5 V 24 36 30 6V 21 31 26 2V 150 230 188 4.5 V 30 46 38 6V 25 38 32 2V 205 306 255 4.5 V 41 61 51 6V 35 53 44 2V 205 306 255 4.5 V 41 61 51 6V 35 53 44 2V 150 225 190 4.5 V 30 45 38 6V 25 38 32 2V 5 5 5 4.5 V 5 5 5 6V 5 5 5 2V 5 5 5 4.5 V 5 5 5 6V 5 5 5 2V 5 5 5 4.5 V 5 5 5 6V 5 5 5 • DALLAS, TEXAS 75265 UNIT MHz ns ns ns 7 SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS SCLS121B – DECEMBER 1982 – REVISED MAY 1997 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax LOAD A, B, C, or D CLK Any Q SN54HC191 2V 4.2 8 2.8 3.3 4.5 V 21 42 14 17 6V 24 48 16 19 MIN MAX SN74HC191 MIN MAX 2V 130 264 396 330 4.5 V 40 53 79 66 6V 33 45 67 56 2V 135 240 360 300 36 48 72 60 6V 30 41 61 51 2V 58 120 180 150 RCO 4.5 V 17 24 36 30 6V 14 21 31 26 2V 107 192 288 240 4.5 V 31 38 58 48 Any Q RCO D/U MAX/MIN RCO Any UNIT MHz 4.5 V MAX/MIN tt TA = 25°C TYP MAX QA, QB, QC, or QD tpd d CTEN MIN VCC 6V 26 32 49 41 2V 123 252 378 315 4.5 V 39 50 76 63 6V 32 43 65 54 2V 102 228 342 285 4.5 V 29 46 68 57 6V 24 38 59 49 2V 86 192 288 240 4.5 V 24 38 58 48 6V 20 32 49 41 2V 50 132 198 165 4.5 V 15 26 40 33 6V 13 23 34 28 2V 38 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 ns ns operating characteristics, TA = 25°C PARAMETER Cpd 8 TEST CONDITIONS Power dissipation capacitance No load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 50 UNIT pF SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS SCLS121B – DECEMBER 1982 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 50% 10% 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% tPHL Out-of-Phase Output 90% VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES tPLH 50% 10% tf tf VOH 50% 10% VOL tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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