TDA7565 Quad power amplifier with built-in voltage converter Features ■ Multipower BCD technology ■ DMOS power output ■ Non-switching high efficiency amplifier ■ Switching high efficiency voltage converter ■ High output power capability 4x60W EIAJ/4Ω ■ Flexiwatt27 2 Full I C Bus driving: – St-by – Independent front/rear soft play/mute – Selectable gain 26dB - 12dB (for low noise line output function) – High efficiency enable/disable – Voltage converter enable/disable – Regulated voltage selection – Switching frequency selection ■ Hardware mute function ■ Full fault protection ■ DC offset detection ■ Four independent short circuit protection ■ Clipping detector with selectable threshold (1 % / 10 %) via I2C bus Table 1. July 2008 Description The TDA7565 is a new BCD technology quad bridge type of car radio amplifier in Flexiwatt27 package specially intended for car radio applications. Thanks to the DMOS output stage the TDA7565 has a very low distortion allowing a clear powerful sound. The built-in voltage converter control block assures a very high output power with an extremely low number of added components. The dissipated power under average listening condition is aligned to the conventional solutions (4 x 40 W). Device summary Order code Package Packing TDA7565 Flexiwatt27 Tube Rev 2 1/18 www.st.com 1 Contents TDA7565 Contents 1 Block and pins connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Software specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 Examples of bytes sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/18 TDA7565 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DB4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3/18 List of figures TDA7565 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. 4/18 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Demoboard schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data validity on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timing diagram on the I2C bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Acknowledge on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flexiwatt27 (vertical) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . 16 TDA7565 1 Block and pins connection diagrams Block and pins connection diagrams Figure 1. Block diagram VS MUTE CLK VCC1 DATA VCC2 I2C BUS CC GND CLIP DETECTOR MUTE1 MUTE2 IN RF VOLTAGE CONVERTER CONTROL MG VOLTAGE CONVERTER EXTERNAL CIRCUIT F OUT RF+ 12/26dB OUT RF- IN RR SHORT CIRCUIT PROTECTION R OUT RR+ 12/26dB OUT RR- IN LF SHORT CIRCUIT PROTECTION F OUT LF+ 12/26dB OUT LF- IN LR SHORT CIRCUIT PROTECTION R OUT LR+ 12/26dB OUT LRSHORT CIRCUIT PROTECTION SVR AC_GND RF RR LF LR TAB D00AU1232A PW_GND Figure 2. S_GND Pins connection (top view) 27 MUTE 26 DATA 25 PW_GND RR 24 OUT RR- 23 CK 22 OUT RR+ 21 VCC2 20 OUT RF- 19 PW_GND RF 18 OUT RF+ 17 AC_GND 16 IN RF 15 IN RR 14 S_GND 13 IN LR 12 IN LF 11 SVR 10 OUT LF+ 9 PW_GND LF 8 OUT LF- 7 VCC1 6 OUT LR+ 5 CC GND 4 OUT LR- 3 PW_GND LR 2 MG 1 TAB D00AU1233A 5/18 Electrical specification TDA7565 2 Electrical specification 2.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Value Unit Vopc OFF Operating supply voltage, converter off 18 V Vopc ON Operating supply voltage, converter on 25 V DC supply voltage 28 V Vpeak Peak supply voltage (for t = 50 ms) 50 V VCK CK pin voltage 6 V Data pin voltage 6 V IO Output peak current (not repetitive t = 100 μs) 8 A IO Output peak current (repetitive f > 10 Hz) 6 A Power dissipation Tcase = 70 °C 80 W -55 to 150 °C Value Unit 1 °C/W VS VDATA Ptot Tstg, Tj 2.2 Parameter Storage and junction temperature Thermal data Table 3. Thermal data Symbol Rth j-case Description Thermal resistance junction to case Max. 2.3 Electrical characteristics Table 4. Electrical characteristics (Refer to the test circuit, VS = 13.5V; RL = 4Ω; f = 1 kHz; voltage converter disabled (VCOff); Tamb = 25°C; unless otherwise specified). Symbol Parameter Test condition Min. Typ. Max. Unit 18 V 300 mA Power amplifier VS Supply voltage range Id Total quiescent drain current 180 Id Total quiescent drain current (VCon) TBD mA EIAJ (VS = 13.7 V) 35 W PO Output power (VCoff) V = 14.4 V THD = 10 % THD = 1 % 25 20 W W 6/18 8 TDA7565 Table 4. Electrical specification Electrical characteristics (continued) (Refer to the test circuit, VS = 13.5V; RL = 4Ω; f = 1 kHz; voltage converter disabled (VCOff); Tamb = 25°C; unless otherwise specified). Symbol PO THD Parameter Output power (VCon) V = 14.4V Total harmonic distortion CT Cross talk RIN Input impedance GV1 Voltage gain 1 ΔGV1 GV2 Test condition Min. Typ. Max. Unit EIAJ (VS = 13.7V) 60 W THD = 10% THD = 1% 40 31 W W PO = 1 W to 12 W; STDMODE HE MODE; PO = 1-2 W HE MODE; PO = 4-12 W 0.03 0.03 0.1 0.1 % % % PO = 1-12 W, f = 10 kHz 0.15 0.5 % f = 1 kHz to 10 kHz, RG = 600 Ω Voltage gain match 1 50 55 60 100 130 KΩ 25.5 26 26.5 dB 1 dB 12.5 dB 1 dB -1 Voltage gain 2 11.5 12 dB ΔGV2 Voltage gain match 2 EIN1 Output noise voltage 1 Rg = 600 Ω; GV = 26 dB filter 20 Hz to 22 kHz 60 100 μV EIN2 Output noise voltage 2 Rg = 600 Ω; GV = 26 dB filter 20 Hz to 12 kHz 15 20 μV SVR Supply voltage rejection f = 100 Hz to 10 kHz; Vr = 1V pk; Rg = 600 Ω 50 BW Power bandwidth (-3 dB) 75 ASB Stand-by attenuation ISB Stand-by current AM Mute attenuation VOS Offset voltage VAM Min. supply voltage threshold 6.5 Slew rate 1.5 -1 70 60 dB KHz 100 dB 100 70 Mute and play 90 -100 7 μA dB 100 mV 7.5 V V/μs TON Turn on delay D2/D1 (IB1) 0 to 1 10 20 ms TOFF Turn off delay D2/D1 (IB1) 1 to 0 10 20 ms 155 170 185 °C D0 (IB1) = 0 0 1 2 % D0 (IB1) = 1 5 10 15 % ±1.5 ±2 ±2.5 V Thermal foldback junction temperature CDTHD Clip det thd. level VO Offset detection Thw Thermal warning Power amplifier = play AC Input = 0 165 °C 7/18 Electrical specification Table 4. TDA7565 Electrical characteristics (continued) (Refer to the test circuit, VS = 13.5V; RL = 4Ω; f = 1 kHz; voltage converter disabled (VCOff); Tamb = 25°C; unless otherwise specified). Symbol Parameter Test condition Min. Typ. Max. Unit I2C Bus interface fSCL Clock frequency 400 KHz VIL Input low voltage 1.5 V VIH Input high voltage VMin(pin27) Mute in threshold voltage 2.3 V Amp. mute 1.5 VMout(pin27) Mute out threshold voltage 3.5 AM(pin 27) Mute attenuation 80 V V 90 Voltage converter Converter output voltage (VC = ON) VS = 14 V D3 (IB2) = 0; D6 (IB2) = 0 D3 (IB2) = 1; D6 (IB2) = 0 D3 (IB2) = 0; D6 (IB2) = 1 D3 (IB2) = 1; D6 (IB2) = 1 15 16.5 17.5 18.5 V V V V Voltage converter switching frequency D6 (IB1) = 0; D7 (IB1) = 0 D6 (IB1) = 1; D7 (IB1) = 0 D6 (IB1) = 0; D7 (IB1) = 1 D6 (IB1) = 1; D7 (IB1) = 1 100 150 260 400 kHz kHz kHz kHz Vmgl MOS gate output low voltage Io = 250 mA Vmgh MOS gate output high voltage Vcc1, Vcc2 Fs Vmgcla mp V Io = 20 mA 10.5 V Io = 200 mA 10 V MOS gate output clamp voltage Io = 5 mA TBD V tf Fall time Co = 1 nF 20 ns tr Rise time Co = 1 nF 50 ns MOS gate output voltage with voltage converter disabled Io = 5 mA Vmgl (VCoff) 8/18 1 0.5 V TDA7565 Electrical specification Figure 3. Demoboard schematic C10 2.2nF VS (Vbatt) C7 2200μF R5 10 1W L1 100μH STPS30L40CT C8 220nF D1 DGND SCL SDA 23 26 VCC C11 3300μF C12 100nF C13 10μF R1 50Ω C9 10nF R4 3.3 1W Q1 R3 10Ω 2 7 5 21 OUT RF+ 18 STP60NE06 C1 220nF 20 16 IN RF OUT RFOUT RR+ 22 C2 220nF 15 IN RR 24 TDA7565 OUT RROUT LF+ C3 220nF 10 12 IN LF 8 C4 220nF IN LR 13 MUTE 27 OUT LFOUT LR+ 6 4 11 14 17 C6 10μF C5 1μF 9 3 19 25 1 OUT LR- D00AU1224B 9/18 I2C bus interface 3 TDA7565 I2C bus interface Data transmission from microprocessor to the TDA7565 and vice versa takes place through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 3.1 Data validity As shown by Figure 4, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.2 Start and stop conditions As shown by Figure 5 a start condition is a high to low transition of the SDA line while SCL is HIGH. The stop condition is a low to high transition of the SDA line while SCL is high. 3.3 Byte format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 3.4 Acknowledge The transmitter* puts a resistive high level on the SDA line during the acknowledge clock pulse (see Figure 6). The receiver** the acknowledges has to pull-down (low) the SDA line during the acknowledge clock pulse, so that the SDA line is stable low during this clock pulse. * Transmitter – master (μP) when it writes an address to the TDA7565 – slave (TDA7565) when the μP reads a data byte from TDA7565 ** Receiver – slave (TDA7565) when the μP writes an address to the TDA7565 – master (µP) when it reads a data byte from TDA7565 Figure 4. Data validity on the I2C bus SDA SCL DATA LINE STABLE, DATA VALID 10/18 CHANGE DATA ALLOWED D99AU1031 I2C bus interface TDA7565 Figure 5. Timing diagram on the I2C bus SCL I2CBUS SDA D99AU1032 START Figure 6. STOP Acknowledge on the I2C bus SCL 1 2 3 7 8 9 SDA MSB START D99AU1033 ACKNOWLEDGMENT FROM RECEIVER 11/18 Software specifications 4 TDA7565 Software specifications All the functions of the TDA7565 are activated by I2C interface. The bit 0 of the "ADDRESS BYTE" defines if the next bytes are write instruction (from µP to TDA7565) or read instruction (from TDA7565 to µP). Table 5. Chip address Bit Instruction D7 Address bit D6 Address bit D5 Address bit D4 Address bit D3 Address bit D2 Address bit D1 Address bit D0(R/W) Read/Write bit 0 = Write instruction 1 = read instruction If R/W = 0, the µP sends 2 "Instruction Bytes": IB1 and IB2. Table 6. IB1 Bit 12/18 Instruction D7 Sel. freq. switch 1 D6 Sel. freq. switch 2 D5 Offset detection start (D5 = 1) Offset detection stop (D5 = 0) (off) D4 Front channel Gain = 26dB (D4 = 0) Gain = 12dB (D4 = 1) D3 Rear channel Gain = 26dB (D3 = 0) Gain = 12dB (D3 = 1) D2 Mute front channels (D2 = 0) Unmute front channels (D2 = 1) D1 Mute rear channels (D1 = 0) Unmute rear channels (D1 = 1) D0 CD 1% (D0 = 0) CD 10% (D0 = 1) TDA7565 Software specifications Table 7. IB2 Bit Instruction D7 Voltage converter enabled (D7 = 1) Voltage converter disabled (D7 = 0) D6 Regulated voltage selection 1 D5 Test speed D4 Stand-by on - amplifier not working - (D4 = 0) Stand-by off - amplifier working - (D4 = 1) D3 Regulated voltage selection 0) D2 To be forced to “Level 1” D1 Right channel Power amplifier working in standard mode (D1 = 0) Power amplifier working in Hi Eff. mode(D1 = 1) D0 Left channel Power amplifier working in standard mode (D0 = 0) Power amplifier working in Hi Eff. mode(D0 = 1) Table 8. DB1 Bit Instruction D7 Thermal warning D6 X D5 X D4 X D3 X D2 Offset (LF) D1 Short circuit protection (CH1) D0 X Table 9. DB2 Bit Instruction D7 Off status D6 X D5 Clip detector output D4 X D3 X D2 Offset (LR) D1 Short circuit protection (CH2) D0 X 13/18 Software specifications Table 10. TDA7565 DB3 Bit Instruction D7 St-by status D6 X D5 X D4 X D3 X D2 Offset (RF) D1 Short circuit protection (CH3) D0 X Table 11. DB4 Bit 14/18 Instruction D7 X D6 X D5 X D4 X D3 X D2 Offset (RR) D1 Short circuit protection (CH4) D0 X TDA7565 5 Examples of bytes sequence Examples of bytes sequence 1 - Turn-on of the power amplifier with 26 dB gain, mute on, diagnostic defeat, high eff. mode, voltage converter disabled. Start Address byte with D0 = 0 ACK IB1 ACK XX00X000 IB2 ACK STOP ACK STOP ACK STOP 0XX1XX10 2 - Turn-off of the power amplifier Start Address byte with D0 = 0 ACK IB1 ACK XXXXXXXX IB2 XXX0XXX0 4 - Offset detection procedure start Start Address byte with D0 = 0 ACK IB1 XX1XX11X ACK IB2 XXX1XXX0 5 - Offset detection procedure stop and reading operation. Start Address byte with D0 = 1 ACK DB1 STOP ● The purpose of this test is to check if a D.C. offset (2V typ.) is present on the outputs, produced by input capacitor with anomalous leakage current or humidity between pins. ● The delay from 3 to 4 can be selected by software, starting from 1 ms 15/18 Package information 6 TDA7565 Package information In order to meet environmental requirements, ST (also) offers these devices in ECOPACK® packages. ECOPACK® packages are lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 7. Flexiwatt27 (vertical) mechanical data and package dimensions DIM. MIN. 4.45 1.80 A B C D E F (1) G G1 H (2) H1 H2 H3 L (2) L1 L2 (2) L3 L4 L5 M M1 N O R R1 R2 R3 R4 V V1 V2 V3 0.75 0.37 0.80 25.75 28.90 22.07 18.57 15.50 7.70 3.70 3.60 mm TYP. 4.50 1.90 1.40 0.90 0.39 1.00 26.00 29.23 17.00 12.80 0.80 22.47 18.97 15.70 7.85 5 3.5 4.00 4.00 2.20 2 1.70 0.5 0.3 1.25 0.50 MAX. 4.65 2.00 MIN. 0.175 0.070 1.05 0.42 0.57 1.20 26.25 29.30 0.029 0.014 0.031 1.014 1.139 22.87 19.37 15.90 7.95 0.869 0.731 0.610 0.303 4.30 4.40 0.145 0.142 inch TYP. 0.177 0.074 0.055 0.035 0.015 0.040 1.023 1.150 0.669 0.503 0.031 0.884 0.747 0.618 0.309 0.197 0.138 0.157 0.157 0.086 0.079 0.067 0.02 0.12 0.049 0.019 MAX. 0.183 0.079 OUTLINE AND MECHANICAL DATA 0.041 0.016 0.022 0.047 1.033 1.153 0.904 0.762 0.626 0.313 0.169 0.173 5˚ (Typ.) 3˚ (Typ.) 20˚ (Typ.) 45˚ (Typ.) Flexiwatt27 (vertical) (1): dam-bar protusion not included (2): molding protusion included V C B V H H1 V3 A H2 O H3 R3 L4 R4 V1 R2 L2 N L3 R L L1 V1 V2 R2 D R1 L5 Pin 1 R1 R1 E G G1 F FLEX27ME M M1 7139011 16/18 TDA7565 7 Revision history Revision history Table 12. Document revision history Date Revision Changes 20-Sep-2003 1 Initial release. 01-Jul-2008 2 Document reformatted. Document status promoted from product preview to datasheet. 17/18 TDA7565 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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