TDA8133/D ® +5.1 V AND +8 V DUAL-VOLTAGE REGULATOR WITH DISABLE AND RESET FUNCTIONS PRELIMINARY DATA FEATURES ■ Input Voltage Range: 7 V to 18 V ■ Output Currents up to 750 mA ■ Fixed Precision Output 1 Voltage: 5.1 V ±2% ■ Fixed Precision Output 2 Voltage: 8 V ±2% ■ Output 1 with Reset Function ■ Output 2 with Disable Function by TTL Input ■ Short-circuit Protection at both Outputs ■ Thermal Protection SIP9 (Plastic Package) ORDER CODE: TDA8133 ■ Low Dropout Voltage DESCRIPTION The TDA8133 and the TDA8133D are monolithic dual positive voltage regulators designed to provide fixed precision output voltages of 5.1 V and 8.0 V for currents up to 750 mA. An internal reset circuit generates a reset pulse when the voltage of Output 1 drops below the regulated voltage value. Output 2 can be disabled via the TTL input. Short-circuit and thermal protections are included in all versions. 9 8 7 6 5 4 3 2 1 DIP16 (8 + 8) ORDER CODE: TDA8133D INPUT1 1 16 GROUND OUTPUT1 INPUT2 OUTPUT2 DELAY CAPACITOR NTBC DISABLE RESET GROUND RESET DISABLE NTBC DELAY CAPACITOR OUTPUT2 INPUT2 INPUT1 OUTPUT1 2 15 GROUND 3 14 GROUND 4 13 GROUND 5 12 GROUND 6 11 GROUND 7 10 GROUND 8 9 GROUND Tab is connected to GROUND September 2003 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/13 TDA8133/D TABLE OF CONTENTS Chapter 1 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Chapter 2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 Absolute Maximum Ratings ................................................................................................ 4 2.2 Thermal Data ...................................................................................................................... 4 2.3 Electrical Characteristics ...................................................................................................... 4 Chapter 3 CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Chapter 4 APPLICATION DIAGRAMS Chapter 5 POWER DISSIPATION AND LAYOUT INDICATIONS . . . . . . . . . . . . . . . . . . . . . .9 Chapter 6 PACKAGE MECHANICAL DATA Chapter 7 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 2/13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 TDA8133/D 1 GENERAL INFORMATION GENERAL INFORMATION Figure 1: TDA8133 Block Diagram DELAY CAPACITOR 3 6 RESET 9 OUTPUT1 8 OUTPUT2 Reference 1 INPUT1 Regulator 1 Protection INPUT2 2 DISABLE 4 Regulator 2 7 NTBC 5 GROUND NTBC: Not to be Connected Figure 2: TDA8133D Block Diagram DELAY CAPACITOR 3 5 RESET 8 OUTPUT1 7 OUTPUT2 Reference INPUT1 1 Regulator 1 Protection INPUT2 2 DISABLE 4 Regulator 2 6 NTBC Pins 9 to 16 GROUND NTBC: Not to be Connected 3/13 ELECTRICAL CHARACTERISTICS TDA8133/D 2 ELECTRICAL CHARACTERISTICS 2.1 Absolute Maximum Ratings Symbol Parameter Value Unit VIN DC Input Voltage at pins INPUT1 and INPUT2 20 V VDIS Disable Input Voltage at pin DISABLE 20 V VRST Output Voltage at pin RESET 20 V IO1,2 Output Currents Internally Limited Power Dissipation Internally Limited Pt TSTG Storage Temperature -65 to +150 °C TJ Junction Temperature 0 to +150 °C Value Unit 2.2 Thermal Data Symbol Parameter RthJC Thermal Resistance (Junction-to-Case) TDA8133 TDA8133D 9 15 °C/W RthJA Thermal Resistance 1 (Junction-to-Ambient) TDA8133 TDA8133D 50 56 °C/W 140 °C 0 to +70 °C TJ Maximum Recommended Junction Temperature TOPER Operating Free Air Temperature Range 1. Mounted on board. For more information, refer to Section 5. 2.3 Electrical Characteristics TAMB = 25° C, VIN1 = 7 V, VIN2 = 10 V, unless otherwise specified. Symbol Parameter Test Conditions Min. Typ. Max. Unit VO1 Output Voltage IO1 = 10 mA 5 5.1 5.2 V VO2 Output Voltage IO2 = 10 mA 7.84 8.00 8.16 V VIO1,2 Dropout Voltage IO1,2 = 750 mA 1.4 V VO1,2LI Line Regulation 7 V < VIN1 < 14 V 10 V < VIN2 < 14 V IO1,2 = 200 mA 50 80 mV VO1,2LO Load Regulation 5 mA < IO1 < 600 mA 5 mA < IO2 < 600 mA 100 160 mV Quiescent Current IO1 = 10 mA, OUTPUT2 Disabled 2 mA IQ 4/13 TDA8133/D Symbol ELECTRICAL CHARACTERISTICS Parameter Test Conditions Min. Typ. Max. Unit K - 0.4 K - 0.25 K - 0.1 V 20 50 75 mV Reset Threshold Voltage K = VO1, VIN1 ≥ 7 V Reset Threshold Hysteresis See circuit description. tRD Reset Pulse Delay Ce = 100 nF See circuit description. VRL Saturation Voltage in Reset Condition IRESET = 5 mA 0.4 V IRH Leakage Current in Normal Condition VRESET= 10 V 10 µA VO1RST VRTH KO1, 2 25 ∆V 0 ⋅ 10 6 K 0 = -----------------------∆T ⋅ V 0 Output Voltage Thermal Drift ms 100 ppm/°C TJ = 0 to + 125°C VIN1 = 7 V, VIN2 = 10 V VIN1,2 = 16 V1 IO1,2SC Short Circuit Output Current VDISH Disable Voltage when pin DISABLE is High (OUTPUT2 active) VDISL Disable Voltage when pin DISABLE is Low (OUTPUT2 disabled) IDIS Disable Bias Current TJSD Junction Temperature for Thermal Shutdown 0 V < VDIS < 7 V 1.6 1.0 2 A V -100 145 0.8 V 2 µA °C 1. The output short-circuit currents are tested one channel at time. During a short-circuit, a large consumption of power occurs, but the thermal protection circuit prevents any excessive temperatures. A safe permanent short-circuit protection is only guaranteed for input voltages up to 16 V. 5/13 CIRCUIT DESCRIPTION 3 TDA8133/D CIRCUIT DESCRIPTION The TDA8133 and the TDA8133D are dual-voltage regulators with Reset and Disable functions. The two regulation parts are supplied from a single voltage reference circuit trimmed by zener zapping during EWS testing. Since the supply voltage of this voltage reference is connected to pin INPUT1 (VIN1), the second regulator will not work if pin INPUT1 is not supplied. The output stages are designed using a Darlington configuration with a typical dropout voltage of 1.2 V. The Disable circuit will switch off pin OUTPUT2 if a voltage less than 0.8 V is applied to pin DISABLE. The Reset circuit checks the voltage at pin OUTPUT1. If this voltage drops below VO1 - 0.25 V (4.85 V Typ.), the "a" comparator (Figure 3) rapidly discharges the external capacitor (Ce) and the reset output immediately switches to low. When the voltage at pin OUTPUT1 exceeds VO1 - 0.2 V (4.9 V Typ.), the VCe voltage increases linearly to the reference voltage (VREF = 2.5 V) corresponding to a Reset Pulse Delay (tRD) as shown in Figure 4. C e × 2.5V t RD = -------------------------10µA Afterwards, the reset output returns to high. To avoid glitches in the reset output, the second comparator "b" has a large hysteresis (1.9 V). Figure 3: Reset Diagram 10 µA VREF OUTPUT1 + a 50 - + 3 REG VREF = 2.5 V 6/13 Ce VREF 0.6V b RESET TDA8133/D CIRCUIT DESCRIPTION Figure 4: Internal Reset Voltage VO1 K VO1RST VRTH RESET K = Actual Value of VO1 Power On tRD tRD Power Off 7/13 APPLICATION DIAGRAMS 4 TDA8133/D APPLICATION DIAGRAMS Figure 5: TDA8133 Typical Application RESET Ce 6 RESET 0.1 µF 3 DELAY CAPACITOR VIN1 1 INPUT1 OUTPUT1 9 VO1 VIN2 2 INPUT2 OUTPUT2 8 VO2 C1 C2 GROUND 5 NTBC 7 DISABLE 4 C3 C4 DISABLE C1 to C4 = 10 µF Figure 6: TDA8133D Typical Application RESET Ce 5 RESET 0.1 µF 3 DELAY CAPACITOR VIN1 1 INPUT1 OUTPUT1 8 VO1 VIN2 2 INPUT2 OUTPUT2 7 VO2 C1 C2 GROUND NTBC 6 DISABLE 4 Pins 9 to 16 DISABLE C1 to C4 = 10 µF 8/13 C3 C4 TDA8133/D 5 POWER DISSIPATION AND LAYOUT INDICATIONS POWER DISSIPATION AND LAYOUT INDICATIONS The power is mainly dissipated by the two device buffers. It can be calculated by the equation: P = (VIN1-VO1) x IO1 + (VIN2-VO2) x IO2 The following table lists the different RthJA values of these packages with or without a heat sink and the corresponding maximum power dissipation assuming: ● Maximum Ambient Temperature = 70° C ● Maximum Junction Temperature = 140° C Device Heat Sink RthJA in °C/W PMAX in W No 50 1.4 Yes 20 3.5 No 56 to 40 1.25 to 1.75 Yes 32 2.2 TDA8133 TDA8133D Figure 7: Thermal Resistance (Junction-to-Ambient) of DIP16 Package without Heat Sink To optimize the thermal conductivity of the copper layer and the exchanges with the air, the solder must cover the maximum amount of this area. RthJA °C/W 60 55 Test Board with “On Board” square heat sink area. 50 45 40 6 0 2 4 8 10 12 Copper area (cm²) (35 µm plus solder) Board is face-down Figure 8: Metal plate mounted near the TDA8133D for heat sinking Top View Bottom View 9/13 PACKAGE MECHANICAL DATA 6 TDA8133/D PACKAGE MECHANICAL DATA Figure 9: 9-Pin Plastic Single In Line Package mm Inches Dim. Min. Typ. A a1 2.7 3 B Typ. 0.106 0.118 24.8 0.85 0.976 0.020 1.6 0.033 0.063 C 3.3 0.130 c1 0.43 0.017 c2 1.32 0.052 21.2 d1 0.835 14.5 0.571 e 2.54 0.100 e3 20.32 0.800 L Max. 0.280 0.5 D 3.1 1.122 L1 3 L2 17.6 L3 10/13 Min. 7.1 b1 b3 Max. 0.116 0.693 0.25 0.010 M 3.2 0.126 N 1 0.039 TDA8133/D PACKAGE MECHANICAL DATA Figure 10: 16-Pin Plastic Dual In-Line Package, 300-mil Width mm Inches Dim. Min. Typ. A Max. Min. Typ. 5.33 A1 0.38 A2 2.92 b 0.36 b2 Max. 0.210 0.015 3.30 4.95 0.115 0.56 0.014 0.130 0.195 0.022 1.52 1.78 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 D 18.67 19.18 19.69 0.735 0.755 0.775 e 2.54 0.100 E1 6.10 6.35 7.11 0.240 0.250 0.280 L 2.92 3.30 3.81 0.115 0.130 0.150 11/13 REVISION HISTORY 7 TDA8133/D REVISION HISTORY Revision Main Changes 1.0 First Issue 1.1 Datasheet Update and addition of DIP16 Package 1.2 General Update; DISABLE pin renamed DISABLE (function remains unchanged). 1.3 Thermal Data updated. 1.4 Thermal Data updated. Figure 1 and Figure 2 updated. 12/13 Date March 1994 July 2001 August 2001 September 2001 October 2001 TDA8133/D Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com 13/13