TI SN74ABTE16246DGGR

SN74ABTE16246
11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER
WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS
SCBS227J – JULY 1993 – REVISED AUGUST 2003
D
D
D
D
D
D
D
D
D
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
Supports the VME64 ETL Specification
Reduced TTL-Compatible Input Threshold
Range
High-Drive Outputs (IOH = –60 mA,
IOL = 90 mA) Support Equivalent 25-Ω
Incident-Wave Switching
VCCBIAS Pin Minimizes Signal Distortion
During Live Insertion
Internal Pullup Resistor on OE Keeps
Outputs in High-Impedance State During
Power Up or Power Down
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Equivalent 25-Ω Series Damping Resistor
on B Port
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
11OE
11DIR
11B
GND
10B
9B
VCC
8BI
8BO
GND
7BO
6BI
6BO
5BO
GND
4BO
4BI
VCC
3BO
2BI
GND
2BO
1BO
1BI
description/ordering information
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
VCCBIAS
11A
10DIR
GND
10A
9A
VCC
9DIR
8A
GND
7A
7BI
6A
5A
GND
5BI
4A
VCC
3A
3BI
GND
2A
1A
OE
27
The SN74ABTE16246 is an 11-bit noninverting
23
26
transceiver designed for asynchronous two-way
24
25
communication between buses. This device has
open-collector and 3-state outputs. The device
allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level
at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the
buses are effectively isolated. When OE is low, the device is active.
The B port has an equivalent 25-Ω series output resistor to reduce ringing. Active bus-hold inputs on the B port
hold unused or floating inputs at a valid logic level.
The A port provides for the precharging of the outputs via VCCBIAS, which establishes a voltage between 1.3 V
and 1.7 V when VCC is not connected.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
–40°C
85°C
–40 C to 85
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SSOP – DL
Tube
SN74ABTE16246DL
Tape and reel
SN74ABTE16246DLR
TOP-SIDE
MARKING
ABTE16246
TSSOP – DGG Tape and reel
SN74ABTE16246DGGR
ABTE16246
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright  2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ABTE16246
11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER
WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS
SCBS227J – JULY 1993 – REVISED AUGUST 2003
FUNCTION TABLE
INPUTS
OPERATION
OE
9DIR
10DIR
11DIR
11OE
H
X
X
X
X
L
X
X
X
X
L
L
X
X
X
9A data to 9B bus
L
H
X
X
X
9B data to 9A bus
L
X
L
X
X
10A data to 10B bus
L
X
H
X
X
10B data to 10A bus
L
X
X
L
L
11A data to 11B bus
L
X
X
L
H
11A, 11B isolation
L
X
X
H
X
11B data to 11A bus
Isolation
1BI–8BI data to 1A–8A bus (OC†),
1A–8A data to 1BO–8BO bus
† OC = Open-collector outputs
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ABTE16246
11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER
WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS
SCBS227J – JULY 1993 – REVISED AUGUST 2003
logic diagram (positive logic)
11OE
11DIR
11B
1
2
3
47
OE
10DIR
10B
25
46
5
44
9DIR
9B
1BO
10A
41
6
43
1BI
11A
26
24
9A
1A
23
To Seven Other Channels
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74ABTE16246
11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER
WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS
SCBS227J – JULY 1993 – REVISED AUGUST 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC and VCCBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC,
VCCBIAS
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
VI
High-level output voltage
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
OE
Except OE
MIN
NOM
MAX
4.5
5
5.5
2
0.8
Except OE
1.4
1A–8A
B bus
9A–11A
V
V
1.6
OE
Input voltage
UNIT
V
0
5.5
V
0
VCC
–12
V
–64
B bus
12
A bus
90
Outputs enabled
10
mA
mA
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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• DALLAS, TEXAS 75265
SN74ABTE16246
11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER
WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS
SCBS227J – JULY 1993 – REVISED AUGUST 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
B port
VOH
VCC = 4.5 V,
VCC = 5.5 V,
II = –18 mA
IOH = –100 µA
VCC = 4.5 V
IOH = –1 mA
IOH = –12 mA
VCC = 5.5 V,
9A–11A
IOH
TEST CONDITIONS
1A–8A
B port
VCC = 4.5 V
VCC = 4.5 V,
IOH = –64 mA
VOH = 5.5 V
II
IOZH‡
IOZL‡
IO
UNIT
–1.2
V
VCC–0.2
2
4.5
B port
2
20
VCC = 4.5 V
0.4
VCC = 4.5 V
IOL = 64 mA
IOL = 90 mA
0.55
VCC = 4.5 V
VI = 0.8 V
VI = 2 V
Control inputs
A or B ports
VCC = 5.5 V,
VCC = 5.5 V
0.8
mV
µA
A
–100
±500
VI = 0 to 5.5 V
±1
VI = VCC or GND
±20
9A–11A
VCC = 5.5 V,
VO = 2.7 V
VO = 0.5 V
VCC = 5.5 V,
VO = 2.5 V
VCC = 0, VI or VO ≤ 4.5 V,
VCCBIAS = 0
Outputs high
28
36
Outputs low
38
48
20
32
A or B ports
VCC = 5.5 V, IO = 0,
VI = VCC or GND
ICCD
A or B ports
VCC = 5 V, CL = 50 pF
Ci
Control inputs
Cio
I/O ports
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
Outputs disabled
V
100
9A–11A
B port
µA
0.9
VCC = 5.5 V, OE = VCC
VCC = 5.5 V,
A port
V
2.4
100
Ioff
ICC
MAX
2.4
Vhys
II(hold)
TYP†
IOL = 1 mA
IOL = 12 mA
VOL
A port
IOH = –1 mA
IOH = –32 mA
MIN
10
µA
–10
µA
–50
–180
–25
–90
±100
OE high
0.02
OE low
0.33
µA
mA
µA
mA
mA/
MHz
2.5
4
pF
4.5
8
pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The parameters IOZH and IOZL include the input leakage current.
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• DALLAS, TEXAS 75265
5
SN74ABTE16246
11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER
WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS
SCBS227J – JULY 1993 – REVISED AUGUST 2003
live-insertion specifications over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
ICC (VCCBIAS)
VCC = 0 to 4.5 V,
VCC = 4.5 V to 5.5 V‡,
VCCBIAS = 4.5 V to 5.5 V,
VCCBIAS = 4.5 V to 5.5 V,
VO
A port
VCC = 0
VCCBIAS = 4.5 V to 5.5 V
VCCBIAS = 4.75 V to 5.25 V
IO
A port
VCC = 0,
VCCBIAS = 4.5 V
MIN
IO(DC) = 0
IO(DC) = 0
TYP†
MAX
250
700
20
VO = 0
VO = 3 V
1.1
1.5
1.9
1.3
1.5
1.7
–20
–100
20
100
UNIT
µA
V
µA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ VCC – 0.5 V < VCCBIAS
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH§
tPLH¶
tPHL
FROM
(INPUT)
TO
(OUTPUT)
A
B
9B–11B
9A–11A
1B–8B
1A–8A
tPZH
tPZL
OE
tPZH
tPZL
OE
tPHZ
tPLZ
OE
tPHZ
tPLZ
OE
MAX
4.2
1.5
5.2
3.5
4.6
1.5
5.2
1.5
3
3.8
1.5
4.5
1.5
3.2
4
1.5
4.5
1.5
3.2
4
1.5
4.5
7.5
8.9
9.7
7.5
10.3
TYP
MAX
1.5
3.1
1.5
1.5
3.2
4
1.5
4.5
2
4.3
5.3
2
6.2
1A–11A
2
4.4
5.4
2
6.8
2
4.3
6
2
7.1
2
4.5
6.4
2
7.3
9A–11A
2
4.2
5.9
2
6.7
1A–11A
2
3.5
4.6
2
5.1
2.5
4.3
6.2
2.5
7
2
3.6
5
2
5.5
B
B
POST OFFICE BOX 655303
MIN
MIN
9A–11A
§ Measurement point is VOL + 0.3 V.
¶ Measurement point is VOL + 1.5 V.
6
VCC = 5 V,
TA = 25°C
• DALLAS, TEXAS 75265
UNIT
ns
ns
ns
ns
ns
ns
ns
SN74ABTE16246
11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER
WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS
SCBS227J – JULY 1993 – REVISED AUGUST 2003
extended switching characteristics over recommended ranges of supply voltage and operating
free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
FROM
(INPUT)
TO
(OUTPUT)
LOAD
9B–11B
9A–11A
RX = 13 Ω
1B–8B
1A–8A
RX = 13 Ω
9B–11B
9A–11A
RX = 26 Ω
1B–8B
1A–8A
RX = 26 Ω
9B–11B
1A–8A
RX = 56 Ω
1B–8B
1A–8A
RX = 56 Ω
B
A
A
B
B
MIN
MAX
4
1.5
4.8
3.8
4.7
1.5
5.6
1.5
3.3
4.2
1.5
4.8
1.5
3.1
4
1.5
4.6
1.5
3.5
4.4
1.5
4.9
1.5
3.1
4
1.5
4.4
1.5
3
3.8
1.5
4.5
1.5
3.3
4.2
1.5
4.7
1.5
3
4
1.5
4.4
RX = Open
0.1
0.6
2
RX = Open
0.4
0.8
2
A
RX = 26 Ω
0.3
0.8
2
B
A
RX = Open
0.3
0.7
1.3
A
B
RX = Open
0.7
1.1
1.3
B
A
RX = 26 Ω
0.5
1
1.3
B
A
0.8
1.5
0.5
1.5
ns
B
RX = 26 Ω
RX = Open
0.5
A
3.5
5.5
7.3
3.5
7.9
ns
tPHL
tPHL
tPLH
tPHL
tPHL
tPLH
tPHL
tPHL
tsk(p)
tsk(o)
tt†
tt‡
VCC = 5 V,
TA = 25°C
MIN
TYP
MAX
1.5
3.2
1.5
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
† tt is measured between 1 V and 2 V of the output waveform.
‡ tt is measured between 10% and 90% of the output waveform.
extended output characteristics over recommended ranges of supply voltage and operating
free-air temperature, CL = 50 pF (see Figures 1 and 2)
PARAMETER
tsk(temp)
tsk(load)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
B
A
TEST CONDITIONS
LOAD
VCC = constant,
∆TA = 20°C
RX = 56 Ω
4
VCC = constant,
Temperature = constant
RX = 13, 26, or 56 Ω
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
MAX
2.5
UNIT
ns
ns
7
SN74ABTE16246
11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER
WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS
SCBS227J – JULY 1993 – REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
Device 1
A
Y1
A
B
Y2
Yn
Device
1 – Y1
tPLH1
tPHL1
tsk(o)
tsk(load)
In
Device n
Device
1 – Yn
tsk(temp)
Y1
tPLH2
Device
n – Yn
B
Y2
Yn
NOTES: A. Pulse skew, tsk(p), is defined as the difference in propagation-delay times tPLH1 and tPHL1 on the same terminal at identical
operating conditions.
B. Output skew, tsk(o), is defined as the difference in propagation delay of any two outputs of the same device switching in the same
direction (e.g., |tPLH1 – tPLH2|) .
C. Temperature skew, tsk(temp), is the output skew of two devices, both having the same value of VCC ± 1% and with package
temperature differences of 20°C.
D. Load skew, tsk(load), is measured with RX in Figure 2 at 13 Ω for one unit and 56 Ω for the other unit.
Figure 1. Voltage Waveforms for Extended Characteristics
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74ABTE16246
11-BIT INCIDENT-WAVE SWITCHING BUS TRANSCEIVER
WITH 3-STATE AND OPEN-COLLECTOR OUTPUTS
SCBS227J – JULY 1993 – REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
7V
Open
S2
3.65 V
500 Ω
94 Ω
S1
RX
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
2 nF
RX = 13, 26, or 56 Ω
SWITCHING TABLE LOADS
tPLH/tPHL (9A–11A and B port)
tPLH/tPHL (1A–8A)
tPLZ/tPZL
tPHZ/tPZH (except 1A–8A)
EXTENDED
SWITCHING TABLE LOADS
tPLH/tPHL/tsk (A port)
tPLH/tPHL/tsk (B port)
tt (A port) (see Note E)
tt (B port) (see Note F)
1.5 V
Input
1.5 V
1.5 V
0V
tPLH
VOH
Output
Output
Waveform 1
S2 at 7 V
(see Note B)
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
S2
Down
Up
Down
Up
X
Open
X
Open
1.5 V
tPLZ
3.5 V
1.5 V
tPZH
tPHL
S1
0V
tPZL
3V
S2
Open
7V
7V
Open
3V
Output
Control
(low-level
enabling)
LOAD CIRCUIT
S1
Up
Up
Up
Up
Output
Waveform 2
S2 at Open
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tt is measured between 1 V and 2 V of the output waveform.
F. tt is measured between 10% and 90% of the output waveform.Figure 1
Figure 2. Load Circuit and Voltage Waveforms
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9
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74ABTE16246DGGRE4
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABTE16246DGGR
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABTE16246DL
ACTIVE
SSOP
DL
48
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABTE16246DLG4
ACTIVE
SSOP
DL
48
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABTE16246DLR
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABTE16246DLRG4
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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