STMICROELECTRONICS TS4851EIJT

TS4851
Mono 1W Speaker and Stereo 160mW Headset
BTL Drivers with Digital Volume Control
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Operating from VCC = 3V to 5.5V
Rail to rail input/output
Speaker driver with 1 W output @ Vcc = 5V,
THD+N = 1%, F = 1kHz, 8Ω load
Headset drivers with 160 mW output @
Vcc = 5V, THD+N = 1%, F = 1kHz, 32Ω load
Headset output is 30mW in stereo @
Vcc = 3V
THD+N < 0.5% Max @ 20mW into 32Ω BTL,
50Hz < Frequency < 20kHz
32-step digital volume control from 34.5dB to +12dB
+6dB power up volume and full standby
8 different output modes
Pop & click reduction circuitry
Low shutdown current (< 100nA)
Thermal shutdown protection
Flip-chip package 18 x 300µm bumps
Pin Connections (top view)
TS485IJT - Flip-chip
TS485EIJT - Lead free Flip-chip
Pin Out (top view)
Description
The TS4851 is a low power audio amplifier that
can drive either both a mono speaker or a stereo
headset. To the speaker, it can deliver 400 mW
(typ.) of continuous RMS output power into an 8Ω
load with a 1% THD+N value. To the headset
driver, the amplifier can deliver 30 mW (typ.) per
channel of continuous average power into a
stereo 32 Ω bridged-tied load with 0.5% THD+N
@ 3.3V.
R
OUT<
-
L
OUT -
GND
R
OUT +
R
IN
L
OUT +
VCC
L
IN
PHONE
IN
DATA
NC
VCC
BYPASS
ENB
SPKR
OUT -
SPKR
OUT+
GND
CLK
This device features a 32-step digital volume
control and 8 different output selections. The
digital volume and output modes are controlled
through a three-digit SPI interface bus.
Applications
■
Mobile Phones
Order Codes
Part Number
TS4851IJT
TS4851EIJT
Temperature Range
Package
Packaging
Marking
-40, +85°C
Flip-Chip
Lead free Flip-Chip
Tape & Reel
A51
A51
J = Flip Chip Package - only available in Tape & Reel (JT))
March 2005
Revision 5
1/28
TS4851
Application Information
1 Application Information
Figure 1: Application information for a typical application
Table 1. External component description
Component
Functional Description
Cin
Cs
This is the input coupling capacitor. It blocks the DC voltage at, and couples the input signal to the
amplifier’s input terminals. Cin also creates a highpass filter with the internal input impedance Zin at Fc
=1/ (2πi x Zin x Cin).
This is the Supply Bypass capacitor. It provides power supply filtering.
CB
This is the Bypass pin capacitor. It provides half-supply filtering.
2/28
SPI Bus Interface
TS4851
2 SPI Bus Interface
Table 2. Pin description
Pin
Functional Description
DATA
CLK
ENB
This is the serial data input pin.
This is the clock input pin.
This is the SPI enable pin active at high level.
2.1 Description of SPI operation
The serial data bits are organized into a field containing 8 bits of data as shown in Table 3. The DATA 0 to
DATA 2 bits determine the output mode of the TS4851 as shown in Table 2. The DATA 3 to DATA 7 bits
determine the gain level setting as illustrated by Table 3. For each SPI transfer, the data bits are written to
the DATA pin with the least significant bit (LSB) first. All serial data are sampled at the rising edge of the
CLK signal. Once all the data bits have been sampled, ENB transitions from logic-high to logic low to
complete the SPI sequence. All 8 bits must be received before any data latch can occur. Any excess CLK
and DATA transitions will be ignored after the height rising clock edge has occurred. For any data
sequence longer than 8 bits, only the first 8 bits will get loaded into the shift register and the rest of the bits
will be disregarded.
Table 3. Bit allocation
LSB
MSB
DATA
MODES
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
Mode 1
Mode 2
Mode 3
gain 1
gain 2
gain 3
gain 4
gain 5
Table 4. Output mode selection: G from -34.5dB to +12dB (by steps of 1.5dB)
1)
Output
Mode #
DATA 2
DATA 1
DATA 0
SPKERout1
Rout
Lout
0
1
2
3
4
5
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
SD
6dBxP
SD
Gx(R+L)
SD
Gx(R+L)
SD
SD
0dBxP
SD
GxR
SD
SD
SD
0dBxP
SD
GxL
SD
6
7
1
1
1
1
0
1
+6dBxP
SD
6dBxP
GxR+0dBxP
GxR+0dBxP
GxL+0dBxP
GxL+0dBxP
SD = Shutdown Mode, P = Phone in Input, R = Rin input and L = Lin input
3/28
TS4851
SPI Bus Interface
Table 5. Volume control settings
K : Gain (dB)
DATA 7
DATA 6
DATA 5
DATA 4
DATA 3
-34.5
-33.0
-31.5
-30.0
-28.5
-27.0
-25.5
-24.0
-22.5
-21.0
-19.5
-18.0
-16.5
-15.0
-13.5
-12.0
-10.5
-9.0
-7.5
-6.0
-4.5
-3.0
-1.5
0.0
1.5
3.0
4.5
6
7.5
9
10.5
12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4/28
SPI Bus Interface
TS4851
Figure 2: SPI timing diagram
5/28
TS4851
Absolute Maximum Ratings
3 Absolute Maximum Ratings
Table 6. Key parameters and their absolute maximum ratings
Symbol
VCC
Parameter
Value
Unit
6
V
Toper
Supply voltage1
Operating Free Air Temperature Range
-40 to + 85
°C
Tstg
Storage Temperature
-65 to +150
°C
Tj
Rthja
Pd
ESD
ESD
Maximum Junction Temperature
2
Flip Chip Thermal Resistance Junction to Ambient
Power Dissipation
Human Body Model
Machine Model
Latch-up Immunity
Lead Temperature (soldering, 10sec)
Lead Temperature (soldering, 10sec) for Lead-Free version
1)
All voltages values are measured with respect to the ground pin.
2)
Device is protected in case of over temperature by a thermal shutdown active @ 150°C
150
°C
200
°C/W
Internally Limited
2
100
200
250
260
kV
V
mA
°C
Value
Unit
V
V
Table 7. Operating conditions
Symbol
1)
6/28
Parameter
VCC
Vphin
Supply Voltage
Maximum Phone In Input Voltage
3 to 5.5
GND to VCC
VRin/VLin
Maximum Rin & Lin Input Voltage
GND to VCC
V
TSD
Rthja
Thermal Shut Down Temperature
150
90
°C
°C/W
Flip Chip Thermal Resistance Junction to Ambient1
Device is protected in case of over temperature by a thermal shutdown active @ 150°C
Electrical Characteristics
TS4851
4 Electrical Characteristics
Table 8. Electrical characteristics at VCC = +5V, GND = 0V, Tamb = 25°C (unless otherwise
specified)
Symbol
ICC
ISTANDBY
Voo
Vil
Vih
Po
THD + N
SNR
PSRR
G
Zin
Zin
tes
teh
tel
tds
tdh
tcs
tch
tcl
fclk
1)
Parameter
Supply Current
Output Mode 7, Vin = 0V, no load
All other output modes, Vin = 0V, no load
Standby Current
Output Mode 0
Output Offset Voltage (differential)
Vin = 0V
“Logic low” input Voltage
“Logic high” input Voltage
Output Power
SPKERout, RL = 8Ω, THD = 1%, F = 1kHz
Rout & Lout, RL = 32Ω, THD = 0.5%, F = 1kHz
Total Harmonic Distortion + Noise
Rout & Lout, Po = 80mW, F = 1kHz, RL = 32Ω
SPKERout, Po = 800mW, F = 1kHz, RL = 8Ω
Rout & Lout, Po = 50mW, 20Hz < F < 20kHz, RL = 32Ω
SPKERout, Po = 40mW, 20Hz < F < 20kHz, RL = 8Ω
Signal To Noise Ratio (A-Weighted)
Power Supply Rejection Ratio1
Vripple = 200mV Vpp, F = 217Hz, Input(s) Terminated 10Ω
Ouput Mode 1
Ouput Mode 2
Ouput Mode 3 (G=+12dB)
Ouput Mode 4 (G=+12dB)
Ouput Mode 5 (G=+12dB)
Ouput Mode 6, 7 (G=+12dB)
Digital Gain Range - Rin & Lin
no load
Digital gain stepsize
Stepsize
G ≥ -22.5dB
G < -22.5dB
Phone In Gain, no load
BTL gain from Phone In to SPKERout
BTL gain from Phone In to Rout & Lout
Phone In Input Impedance
Rin & Lin Input Impedance (all gain setting)
Enable Stepup Time - ENB
Enable Hold Time - ENB
Enable Low Time - ENB
Data Setup Time- DATA
Data Hold Time - DATA
Clock Setup time - CLK
Clock Logic High Time - CLK
Clock Logic Low Time - CLK
Clock Frequency - CLK
Min.
Typ.
Max.
8
4.5
11
6.5
0.1
2
5
50
0.4
5
Unit
mA
µA
mV
0
1.4
800
80
V
V
mW
1000
120
%
0.5
1
0.5
1
90
dB
dB
70
70
55
57
52
56
dB
-34.5
+12
1.5
-0.5
-1
dB
dB
+0.5
+1
dB
15
37.5
20
20
30
20
20
20
50
50
DC
6
0
20
50
25
62.5
10
kΩ
kΩ
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Dynamic measurements [20 x log(rms(Vout)/rms(Vripple)]. Vripple is the superimposed sinus signal to Vcc @ F = 217Hz
7/28
TS4851
Electrical Characteristics
Table 9. Electrical characteristics at VCC = +3V, GND = 0V, Tamb = 25°C (unless otherwise
specified)
Symbol
ICC
ISTANDBY
Voo
Vil
Vih
Po
THD + N
SNR
PSRR1
G
Parameter
Supply Current
Output Mode 7, Vin = 0V,no load
All other output modes, Vin = 0V,no load
Standby Current
Output Mode 0
Output Offset Voltage (differential)
Vin = 0V
“Logic low” input Voltage
“Logic high” input Voltage
Output Power
SPKERout, RL = 8Ω, THD = 1%, F = 1kHz
Rout & Lout, RL = 32Ω, THD = 0.5%, F = 1kHz
Total Harmonic Distortion + Noise
Rout & Lout, Po = 20mW, F = 1kHz, RL = 32Ω
SPKERout, Po = 300mW, F = 1kHz, RL = 8Ω
Rout & Lout, Po = 15mW, 20Hz < F < 20kHz, RL = 32Ω
SPKERout, Po = 250mW, 20Hz < F < 20kHz, RL = 8Ω
Signal To Noise Ratio (A-Weighted)
Typ.
Max.
7.5
4.5
10
6.5
0.1
2
5
50
0.4
5
Power Supply Rejection
Vripple = 200mV Vpp, F = 217Hz, Input(s) Terminated 10Ω
Ouput Mode 1
Ouput Mode 2
Ouput Mode 3 (G=+12dB)
Ouput Mode 4 (G=+12dB)
Ouput Mode 5 (G=+12dB)
Ouput Mode 6, 7 (G=+12dB)
Digital Gain Range - Rin & Lin
no load
Digital gain stepsize
Stepsize error
G ≥ -22.5dB
G < -22.5dB
Phone In Gain, no load
BTL gain from Phone In to SPKERout
BTL gain from Phone In to Rout & Lout
Phone In Input Impedance 1
Zin
Rin & Lin Input Impedance (All Gain Setting) 1
Enable Stepup Time - ENB
Enable Hold Time - ENB
Enable Low Time - ENB
Data Setup Time- DATA
Data Hold Time - DATA
Clock Setup time - CLK
Clock Logic High Time - CLK
Clock Logic Low Time - CLK
Clock Frequency - CLK
µA
mV
0
1.4
300
20
V
V
mW
340
30
%
0.5
1
0.5
1
86
dB
dB
65
70
54
54
51
53
dB
-34.5
1.5
-0.5
-1
+12
dB
dB
+0.5
+1
dB
15
6
0
20
25
kΩ
37.5
50
62.5
kΩ
10
ns
ns
ns
ns
ns
ns
ns
ns
MHz
20
20
30
20
20
20
50
50
DC
1)
All PSRR data limits are guaranted by evaluation desgin test.
2)
Dynamic measurements [20 x log(rms(Vout)/rms(Vripple)]. Vripple is the superimposed sinus signal to Vcc @ F = 217Hz
8/28
Unit
mA
Ratio2
Zin
tes
teh
tel
tds
tdh
tcs
tch
tcl
fclk
Min.
Electrical Characteristics
TS4851
Table 10. Index of graphics
Description
THD + N vs. Output Power
THD + N vs. Frequency
Output Power vs. Power Supply Voltage
PSRR vs. Frequency
Frequency Response
Signal to Noise Ratio vs. Power Supply Voltage
Crosstalk vs. Frequency
-3 dB Lower Cut Off Frequency vs. Input Capacitor
Current Consumption vs. Power Supply Voltage
Power Dissipation vs. Output Power
Power Derating Curves
-3 dB Lower Cut Off Frequency vs. Gain Setting
Figure
Page
Figures 3 to 12
Figures 13 to 22
Figures 23 to 30
Figures 31 to 40
Figures 41 to 44
Figures 45 to 48
Figures 49 to 50
Figures 51 to 52
Figure 53
Figures 54 to 57
Figure 58
Figure 59
page 10 to page 11
page 11 to page 13
page 13 to page 14
page 14 to page 16
page 16
page 17
page 18
page 18
page 18
page 18 to page 19
page 19
page 19
Note: In the graphs that follow, the abbreviations Spkout = Speaker Output, and HDout = Headphone Output are used.
All measurements made with Cin = 220nF, Cb = Cs = 1µF except in PSRR condition where Cs = 0.
9/28
TS4851
Electrical Characteristics
Figure 3: Spkout THD+N vs. output power
(output modes 1, 7)
Figure 6: HDout THD+N vs. output power
(output mode 2)
10
10
RL = 4Ω
Output mode 1, 7
BW < 125 kHz
Tamb = 25°C
Vcc=5V
F=20kHz
Vcc=3V
F=20kHz
1
THD + N (%)
THD + N (%)
1
0.1
RL = 16Ω
Output mode 2
BW < 125 kHz
Tamb = 25°C
Vcc=5V
F=20kHz
Vcc=3V
F=20kHz
0.1
Vcc=3V
F=1kHz
Vcc=3V
F=1kHz
0.01
1E-3
0.01
Vcc=5V
F=1kHz
0.1
Vcc=5V
F=1kHz
0.01
1
1E-3
0.01
Output power (W)
Figure 4: Spkout THD+N vs. output power
(output modes 1, 7)
Figure 7: HDout THD+N vs. output power
(output mode 2)
10
10
RL = 8Ω
Output mode 1, 7
BW < 125 kHz
Tamb = 25°C
Vcc=5V
F=20kHz
Vcc=3V
F=20kHz
1
THD + N (%)
THD + N (%)
1
0.1
Output power (W)
0.1
RL = 32Ω
Output mode 2
BW < 125 kHz
Tamb = 25°C
Vcc=5V
F=20kHz
Vcc=3V
F=20kHz
0.1
Vcc=3V
F=1kHz
Vcc=3V
F=1kHz
0.01
1E-3
0.01
Vcc=5V
F=1kHz
0.1
Vcc=5V
F=1kHz
0.01
1
1E-3
0.01
Output power (W)
Figure 5: Spkout THD+N vs. output power
(output modes 1, 7)
Figure 8: Spkout THD+N vs. output power
(output mode 3, G=+12dB)
10
10
RL = 16Ω
Output mode 1, 7
BW < 125 kHz
Tamb = 25°C
Vcc=3V
F=20kHz
0.1
Vcc=3V
F=1kHz
Vcc=5V
F=1kHz
0.01
1E-3
0.01
0.1
Output power (W)
10/28
RL = 4Ω
Out. mode 3; G = +12dB
BW < 125 kHz
Tamb = 25°C
Vcc=5V
F=20kHz
THD + N (%)
THD + N (%)
1
0.1
Output power (W)
1
Vcc=5V
F=20kHz
Vcc=3V
F=20kHz
1
0.1
1E-3
Vcc=3V
F=1kHz
Vcc=5V
F=1kHz
0.01
0.1
Output power (W)
1
Electrical Characteristics
TS4851
Figure 9: Spkout THD+N vs. output power
(output mode 3, G=+12dB)
Figure 12: HDout THD+N vs. output power
(output mode 4, G=+12dB)
10
10
Vcc=5V
F=20kHz
Vcc=3V
F=20kHz
1
1
THD + N (%)
THD + N (%)
RL = 8Ω
Out. mode 3; G = +12dB
BW < 125 kHz
Tamb = 25°C
RL = 32Ω
Output mode 4
G = +12dB
BW < 125 kHz
Tamb = 25°C
0.1
Vcc=5V
F=1kHz
Vcc=5V
F=1kHz
Vcc=3V
F=1kHz
1E-3
0.01
0.1
0.01
1E-3
1
0.01
Output power (W)
Figure 13: Spkout THD+N vs. frequency
(output modes 1, 7)
10
10
RL = 16Ω
Output mode 3
G = +12dB
BW < 125 kHz
Tamb = 25°C
0.1
Output power (W)
Figure 10: Spkout THD+N vs. output power
(output mode 3, G=+12dB)
Vcc=5V
F=20kHz
Vcc=3V
F=20kHz
RL = 4Ω
Output mode 1, 7
BW < 125kHz
Tamb = 25°C
1
THD + N (%)
THD + N (%)
Vcc=3V
F=20kHz
Vcc=3V
F=1kHz
0.1
1
Vcc=5V
F=20kHz
Vcc=3V
F=1kHz
0.1
Vcc=3V
P=400mW
Vcc=5V
P=1.1W
0.1
Vcc=5V
F=1kHz
0.01
1E-3
0.01
0.1
0.01
1
100
Output power (W)
Figure 11: HDout THD+N vs. output power
(output mode 4, G=+12dB)
10
RL = 16Ω
Output mode 4
G = +12dB
BW < 125 kHz
Tamb = 25°C
RL = 8Ω
Output mode 1, 7
BW < 125kHz
Tamb = 25°C
Vcc=5V
F=20kHz
Vcc=3V
F=20kHz
1
THD + N (%)
THD + N (%)
10000
Figure 14: Spkout THD+N vs. frequency
(output modes 1, 7)
10
1
1000
Frequency (Hz)
0.1
Vcc=3V
P=320mW
Vcc=5V
P=800mW
0.1
Vcc=3V
F=1kHz
Vcc=5V
F=1kHz
0.01
1E-3
0.01
Output power (W)
0.1
0.01
100
1000
10000
Frequency (Hz)
11/28
TS4851
Electrical Characteristics
Figure 15: Spkout THD+N vs. frequency
(output modes 1, 7)
10
Figure 18: Spkout THD+N vs.frequency
(output mode 3, G = +12 dB)
10
RL = 16Ω
Output mode 1, 7
BW < 125kHz
Tamb = 25°C
RL = 4Ω
Output mode 3
G = +12dB
BW < 125kHz
Tamb = 25°C
Vcc=3V
P=150mW
Vcc=5V
P=550mW
THD + N (%)
THD + N (%)
1
0.1
Vcc=5V
P=1.1W
1
Vcc=3V
P=400mW
0.1
0.01
100
1000
10000
100
Figure 16: HDout THD+N vs. frequency
(output mode 2)
10000
Figure 19: Spkout THD+N vs. frequency
(output mode 3, G = +12 dB)
10
10
RL = 16Ω
Output mode 2
BW < 125kHz
Tamb = 25°C
RL = 8Ω
Output mode 3
G = +12dB
BW < 125kHz
Tamb = 25°C
Vcc=3V
P=40mW
THD + N (%)
1
THD + N (%)
1000
Frequency (Hz)
Frequency (Hz)
Vcc=5V
P=220mW
0.1
1
Vcc=3V
P=320mW
Vcc=5V
P=800mW
0.1
0.01
100
1000
10000
100
Frequency (Hz)
Figure 17: HDout THD+N vs. frequency
(output mode 2)
10
RL = 32Ω
Output mode 2
BW < 125kHz
Tamb = 25°C
RL = 16Ω
Output mode 3
G = +12dB
BW < 125kHz
1 Tamb = 25°C
Vcc=3V
P=20mW
THD + N (%)
THD + N (%)
1
Vcc=5V
P=140mW
0.1
100
1000
Frequency (Hz)
12/28
10000
Figure 20: Spkout THD+N vs. frequency
(output mode 3, G = +12 dB)
10
0.01
1000
Frequency (Hz)
10000
0.1
0.01
Vcc=3V
P=180mW
Vcc=5V
P=550mW
100
1000
Frequency (Hz)
10000
Electrical Characteristics
TS4851
Figure 24: Speaker output power vs. power
supply voltage (output mode 1, 7)
Figure 21: HDout THD+N vs. frequency
(output mode 4, G = +12 dB)
2.4
THD + N (%)
RL = 16Ω
Output mode 4
G = +12dB
BW < 125kHz
1 Tamb = 25°C
Output power at 10% THD + N (W)
10
Vcc=3V
P=40mW
Vcc=5V
P=220mW
0.1
0.01
100
1000
F = 1kHz
Output mode 1, 7
2.0 BW < 125kHz
Tamb = 25°C
4Ω
1.6
8Ω
1.2
16Ω
0.8
32Ω
0.4
0.0
3.0
10000
3.5
Frequency (Hz)
4.5
Output power at 1% THD + N (W)
0.35
RL = 32Ω
Output mode 4
G = +12dB
BW < 125kHz
1 Tamb = 25°C
Vcc=3V
P=20mW
Vcc=5V
P=140mW
0.1
0.01
100
1000
0.30
0.25
F = 1kHz
Output mode 2
BW < 125kHz
Tamb = 25°C
32Ω
0.20
0.15
64Ω
0.10
0.05
0.00
3.0
10000
16Ω
3.5
4.0
Frequency (Hz)
4.5
5.0
5.5
Vcc (V)
Figure 23: Speaker output power vs. power
supply voltage (output mode 1, 7)
Figure 26: Headphone output power vs. load
resistor (output mode 2)
0.40
2.0
F = 1kHz
Output mode 1, 7
BW < 125kHz
Tamb = 25°C
F = 1kHz
Output power at 10% THD + N (W)
Output power at 1% THD + N (W)
5.5
Figure 25: Headphone output power vs. load
resistor (output mode 2)
10
1.6
5.0
Vcc (V)
Figure 22: HDout THD+N vs. frequency
(output mode 4, G = +12 dB)
THD + N (%)
4.0
4Ω
1.2
8Ω
16Ω
0.8
32Ω
0.4
0.0
3.0
3.5
4.0
4.5
Vcc (V)
5.0
5.5
0.35 Output mode 2
0.30
16Ω
BW < 125kHz
Tamb = 25°C
32Ω
0.25
0.20
64Ω
0.15
0.10
0.05
0.00
3.0
3.5
4.0
4.5
5.0
5.5
Vcc (V)
13/28
TS4851
Electrical Characteristics
Figure 27: Speaker output power vs. power
supply voltage (output mode 3)
Figure 30: Headphone output power vs. load
resistance (output mode 2)
0.40
2.0
Output power at 1% THD + N (W)
Output power at 10% THD + N (W)
F = 1kHz
F = 1kHz
Output mode 3
1.6 BW < 125kHz
Tamb = 25°C
4Ω
1.2
8Ω
16Ω
0.8
32Ω
0.4
0.0
3.0
3.5
4.0
4.5
5.0
0.35 Output mode 4
32Ω
0.25
0.20
0.15
0.10
64Ω
0.05
0.00
3.0
5.5
16Ω
BW < 125kHz
0.30 Tamb = 25°C
3.5
4.0
Vcc (V)
Figure 28: Speaker output power vs. power
supply voltage (output mode 3)
Output power at 10% THD + N (W)
5.5
0
F = 1kHz
Output mode 3
BW < 125kHz
Tamb = 25°C
Output mode 1, 7
-10 RL = 8Ω
Vripple = 0.2Vpp
-20
Tamb = 25°C
-30
4Ω
1.6
PSRR (dB)
8Ω
1.2
16Ω
0.8
32Ω
-40
Vcc=3V
-50
Vcc=5V
-60
-70
0.4
-80
0.0
3.0
3.5
4.0
4.5
5.0
-90
5.5
100
Vcc (V)
Figure 29: Headphone output power vs. load
resistor (output mode 4)
0.25
16Ω
-10
-20
32Ω
0.20
0.15
0.10
-30
-40
Vcc = 3V & 5V
-50
-60
-70
3.5
4.0
4.5
Vcc (V)
14/28
Output mode 2
RL = 32Ω
Vripple = 0.2Vpp
Tamb = 25°C
64Ω
0.05
0.00
3.0
100000
0
F = 1kHz
Output mode 4
BW < 125kHz
Tamb = 25°C
PSRR (dB)
0.30
1000
10000
Frequency (Hz)
Figure 32: HDout PSRR vs. frequency
(output mode 2, input grounded)
0.35
Output power at 1% THD + N (W)
5.0
Figure 31: Spkout PSRR vs. frequency
(output modes 1, 7, input grounded)
2.4
2.0
4.5
Vcc (V)
5.0
5.5
-80
100
1000
10000
Frequency (Hz)
100000
Electrical Characteristics
TS4851
Figure 33: Spkout PSRR vs. frequency
(output mode 3, inputs grounded)
Figure 36: HDout PSRR vs. frequency
(output mode 4, inputs grounded)
0
0
Output mode 4
-10 Vcc = +3V
RL = 32 Ω
-20 Vripple=0.2Vpp
Tamb = 25°C
-20
G=+12dB
-30
G=+6dB
-40
G=+9dB
-50
Output mode 3
Vcc = +5V
RL = 8Ω
Vripple = 0.2Vpp
Tamb = 25 °
-60
-70
G=-12dB
-80
G=-34.5dB
-90
G=0dB
PSRR (Hz)
PSRR (dB)
-10
1000
10000
Frequency (Hz)
-30
G=0dB
G=-34.5dB
G=+12dB
-20
G=+6dB
G=+9dB
100
1000
10000
Frequency (Hz)
G=-12dB
G=0dB
G=-34.5dB
100
1000
10000
Frequency (Hz)
100000
Figure 38: Spkout PSRR vs. frequency
(output mode 5, inputs grounded)
0
Output mode 4
Vcc = +5V
RL = 32Ω
Vripple=0.2Vpp
Tamb = 25°C
-10
G=+12dB
-20
G=+6dB
PSRR (Hz)
PSRR (dB)
G=+12dB
G=+9dB
-40
-70
100000
0
G=+9dB
-40
G=-12dB
-50
G=0dB
-60
-70
-80
-30
G=0dB
Figure 35: HDout PSRR vs. frequency
(output mode 4, inputs grounded)
-30
100000
G=+6dB
-60
G=-12dB
-70
Output mode 5
Vcc = +5V
RL = 8Ω
Vripple=0.2Vpp
Tamb = 25°C
-50
G=-34.5dB
-60
-20
1000
10000
Frequency (Hz)
Figure 37: Spkout PSRR vs. frequency
(output mode 5, inputs grounded)
-10
-50
-10
100
0
Output mode 3
Vcc = +3V
RL = 8Ω
Vripple=0.2Vpp
Tamb = 25°C
-40
-80
G=-12dB
-60
PSRR (Hz)
PSRR (dB)
-20
-40
-50
0
-10
G=+9dB
100000
Figure 34: Spkout PSRR vs. frequency
(output mode 3, inputs grounded)
G=+12dB
-30
-70
100
G=+6dB
1000
10000
Frequency (Hz)
-30
100000
G=+6dB
G=+12dB
G=+9dB
-40
G=-12dB
G=0dB
-50
G=-34.5dB
-60
G=-34.5dB
100
Output mode 5
Vcc = +3V
RL = 8Ω
Vripple=0.2Vpp
Tamb = 25°C
-70
100
1000
10000
Frequency (Hz)
100000
15/28
TS4851
Electrical Characteristics
Figure 39: HDout PSRR vs. frequency (output
modes 6, 7, inputs grounded)
Figure 42: HDout frequency response
(output mode 2)
0
Output mode 6, 7
-10 Vcc = +5V
RL = 32Ω
-20 Vripple=0.2Vpp
Tamb = 25°C
-30
G=+6dB
G=+12dB
G=+9dB
-40
Vcc=3V
Vcc=5V
-2
Output level (dB)
PSRR (Hz)
0
G=-12dB
-50
-4
Output mode 2
RL = 32Ω
Cin = 220 nF
BW < 125 kHz
Tamb = 25°C
G=0dB
-6
-60
G=-34.5dB
-70
100
1000
10000
100000
20
100
Frequency (Hz)
Figure 40: HDout PSRR vs. freq., (output
modes 6, 7, inputs grounded)
12
-20
-30
G=+6dB
10
G=+12dB
8
Output level (dB)
Output mode 6, 7
Vcc = +3V
RL = 32Ω
Vripple=0.2Vpp
Tamb = 25°C
-10
G=+9dB
G=-12dB
-40
-50
Vcc=5V
Vcc=3V
6
Output mode 3
RL = 8Ω
G = +12dB
Cin = 220 nF
BW < 125 kHz
Tamb = 25°C
4
G=0dB
2
-60
G=-34.5dB
-70
100
1000
10000
Frequency (Hz)
0
20
100000
10000
12
10
2
Output mode 1, 7
RL = 8Ω
Cin = 220 nF
BW < 125 kHz
Tamb = 25°C
0
100
1000
Frequency (Hz)
10000
Output level (dB)
Vcc=3V
Vcc=5V
4
Output level (dB)
1000
Figure 44: HDout frequency response
(output mode 4)
6
20
100
Frequency (Hz)
Figure 41: Spkout frequency response
(output mode 1, 7)
16/28
10000
Figure 43: Spkout frequency response
(output mode 3)
0
PSRR (Hz)
1000
Frequency (Hz)
Vcc=5V
Vcc=3V
8
6
Output mode 4
RL = 32Ω
G = +12dB
Cin = 220 nF
BW < 125 kHz
Tamb = 25°C
4
2
0
20
100
1000
Frequency (Hz)
10000
Electrical Characteristics
TS4851
Figure 45: Spkout SNR vs. power supply
voltage, unweighted filter,
BW = 20 Hz to 20 kHz
Figure 47: HDout SNR vs. power supply
voltage, unweighted filter,
BW = 20 Hz to 20 kHz
100
100
Vcc=3V
Vcc=5V
RL = 8Ω
Unweighted filter (20Hz to 20kHz)
THD + N < 0.7%
Tamb = 25°C
96
94
SNR (dB)
92
90
96
94
92
88
86
84
G=+12dB
82
Vcc=3V
Vcc=5V
RL = 32Ω
Unweighted filter (20Hz to 20kHz)
THD + N < 0.7%
Tamb = 25°C
98
SNR (dB)
98
90
88
86
84
82
80
80
78
78
76
G=+12dB
76
1
2
3
4
5
6
7
1
2
3
Output mode
Figure 46: Spkout SNR vs. power supply
voltage, weighted filter A,
BW = 20 Hz to 20 kHz
104
SNR (dB)
98
96
100
98
94
92
6
7
Vcc=3V
Vcc=5V
RL = 32Ω
Weighted filter type A
THD + N < 0.7%
Tamb = 25°C
102
SNR (dB)
100
5
Figure 48: HDout SNR vs. power supply
voltage, weighted filter A,
BW = 20 Hz to 20 kHz
104
Vcc=3V
Vcc=5V
RL = 8Ω
Weighted filter type A
THD + N < 0.7%
Tamb = 25°C
102
4
Output mode
G=+12dB
96
94
92
90
90
88
88
G=+12dB
86
86
1
2
3
4
Output mode
5
6
7
1
2
3
4
5
6
7
Output mode
17/28
TS4851
Electrical Characteristics
Figure 52: -3 dB lower cut off frequency vs.
input capacitance
Figure 49: Crosstalk vs. frequency
(output mode 4)
Output mode 4
Vcc = 5V
-20 RL = 32Ω
G = +12dB
Pout = 100mW
BW < 125kHz
-40
Tamb = 25°C
Lower -3dB Cut Off Frequency (Hz)
Crosstalk Level (dB)
0
Lout -> Rout
Rout -> Lout
-60
-80
20
100
1000
Rin & Lin Inputs
All gain setting
Tamb=25°C
10
Typical Input
Impedance
Minimum Input
Impedance
Maximum Input
Impedance
1
0.1
10000
1
Input Capacitor (µF)
Frequency (Hz)
Figure 53: Current consumption vs.
power supply voltage
Figure 50: Crosstalk vs. frequency
(output mode 4)
10
No loads
9 Tamb = 25°C
Output mode 4
Vcc = 3V
-20 RL = 32Ω
G = +12dB
Pout = 20mW
BW < 125kHz
-40
Tamb = 25°C
Mode 7
8
7
Mode 2, 4, 6
6
Icc (mA)
Crosstalk Level (dB)
0
Lout -> Rout
Rout -> Lout
-60
5
Reset state
4
3
Mode 1, 3, 5
2
-80
1
100
1000
0
10000
0
1
2
Frequency (Hz)
Figure 51: -3 dB lower cut off frequency vs.
input capacitor
Power Dissipation (W)
Lower -3dB Cut Off Frequency (Hz)
5
1.4
Phone In Input
Tamb=25°C
Typical Input
Impedance
Minimum Input
Impedance
Maximum Input
Impedance
0.1
Vcc=5V
1.2 F=1kHz
THD+N<1%
RL=4Ω
1.0
0.8
0.6
RL=8Ω
0.4
0.2
RL=16Ω
1
Input Capacitor ( F)
18/28
4
Figure 54: Power dissipation vs. output power
(speaker output)
100
10
3
Vcc (V)
0.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Output Power (W)
1.4
1.6
Electrical Characteristics
TS4851
Figure 55: Power dissipation vs. output power
(speaker output)
Figure 58: Power derating curves
0.5
Power Dissipation (W)
Lower -3dB Cut Off Frequency (Hz)
100
Vcc=3V
F=1kHz
0.4 THD+N<1%
RL=4Ω
0.3
0.2
RL=8Ω
0.1
RL=16Ω
0.0
0.0
0.1
0.2
0.3
0.4
Rin & Lin Inputs
Input Impedance is Nominal
Tamb=25°C
Cin=220nF
10
Cin=1µF
1
-34.5
0.5
Vcc=5V
F=1kHz
THD+N<1%
0.3
RL=16Ω
RL=32Ω
0.05
0.10
0.15
0.20
Output Power (W)
1.4
1.2
Heat sink surface = 125mm
2
1.0
0.8
0.6
0.4
No Heat sink
0.2
0.0
0.25
0
25
50
75
100
125
150
Ambiant Temperature ( C)
Figure 57: Power dissipation vs. output power
(headphone output one channel)
120
Power Dissipation (mW)
12
Figure 59: -3 dB lower cut off frequency vs. gain
setting (output modes 3, 4, 5, 6, 7)
Flip-Chip Package Power Dissipation (W)
Power Dissipation (W)
0.4
0.0
0.00
0
Gain Setting (dB)
Figure 56: Power dissipation vs. output power
(headphone output, one channel)
0.1
Cin=470nF
-20
Output Power (W)
0.2
Cin=100nF
Vcc=3V
F=1kHz
100 THD+N<1%
Table 11. Output noise (all inputs grounded)
Outp
ut
Mode
Unweighted
Filter from 3V
to 5V
Weighted Filter
(A) from 3V to
5V
1
23µVrms
20µVrms
2
20µVrms
17µVrms
3
70µVrms
60µVrms
4
53µVrms
45µVrms
5
79µVrms
67µVrms
6
60µVrms
51µVrms
RL=16Ω
80
60
40
RL=32Ω
20
0
0
10
20
30
40
50
Output Power (mW)
60
70
19/28
TS4851
Application Information
5 Application Information
5.1 BTL configuration principles
The TS4851 integrates 3 monolithic power amplifier having BTL output. BTL (Bridge Tied Load) means
that each end of the load is connected to two single-ended output amplifiers. Thus, we have:
Single ended output 1 = Vout1 = Vout (V)
Single ended output 2 = Vout2 = -Vout (V)
and
Vout1 - Vout2 = 2Vout (V)
The output power is:
Pout =
( 2 Vout RMS ) 2
(W )
RL
For the same power supply voltage, the output power in BTL configuration is four times higher than the
output power in single ended configuration.
5.2 Power dissipation and efficiency
Hypotheses:
l Voltage and current in the load are sinusoidal (Vout and Iout).
l Supply voltage is a pure DC source (Vcc).
Regarding the load we have:
V O UT = V PEAK sin ωt (V)
and
V OU T
I OU T = ----------------- (A)
RL
and
VPEAK 2
P O U T = ---------------------- (W)
2R L
Then, the average current delivered by the supply voltage is:
I CC
AVG
VPEA K
= 2 -------------------- (A)
πR L
The power delivered by the supply voltage is:
Psupply = Vcc IccAVG (W)
Then, the power dissipated by each amplifier is
Pdiss = Psupply - Pout (W)
Pdiss =
20/28
2 2 VCC
π RL
POUT − POUT
(W )
Application Information
TS4851
and the maximum value is obtained when:
∂Pdiss
---------------------- = 0
∂P OU T
and its value is:
Pdiss max =
2 Vcc 2
π 2RL
(W)
Note: This maximum value is depends only on power supply voltage and load values.
The efficiency is the ratio between the output power and the power supply:
P O UT
πV P E A K
η = ------------------------ = ----------------------Psup ply
4V C C
The maximum theoretical value is reached when Vpeak = Vcc, so:
π
----- = 78.5%
4
The TS4851 has three independent power amplifiers. Each amplifier produces heat due to its power
dissipation. Therefore, the maximum die temperature is the sum of each amplifier’s maximum power
dissipation. It is calculated as follows:
l Pdiss speaker = Power dissipation due to the speaker power amplifier.
l Pdiss head = Power dissipation due to the Headphone power amplifier
l Total Pdiss = P diss speaker + Pdiss head1 + Pdiss head2 (W)
In most cases, Pdiss head1 = Pdiss head2, giving:
Total Pdiss = P diss speaker + 2Pdiss head (W)
TotalP diss =
POUT HEAD ⎤
2 2 VCC ⎡ POUT SPEAKER
+2
⎢
⎥
π
R L HEAD ⎥⎦
⎣⎢ R L SPEAKER
− POUT SPEAKER + 2 POUT HEAD
(W )
[
]
The following graph (Figure 60) shows an example of the previous formula, with Vcc set to +5V,
Rload speaker set to 8Ω and Rload headphone set to 16Ω.
Figure 60: Example of total power dissipation vs. speaker and headphone output power
21/28
TS4851
Application Information
5.3 Low frequency response
In low frequency region, the effect of Cin starts. Cin with Zin forms a high pass filter with a -3dB cut off
frequency.
FCL =
1
(Hz )
2 π Zin Cin
Zin is the input impedance of the corresponding input:
•
20kΩ for Phone In IHF input
•
50kΩ for the 3 other inputs
Note: For all inputs, the impedance value remains constant for all gain settings. This means that the lower cut-off
frequency doesn’t change with gain setting. Note also that 20kΩ and 50kΩ are typical values and there are
tolerances around these values (see Electrical Characteristics on page 7).
In Figures 39 to 41, you could easily establish the Cin value for a -3dB cut-off frequency required.
5.4 Decoupling of the circuit
Two capacitors are needed to bypass properly the TS4851, a power supply bypass capacitor Cs and a
bias voltage bypass capacitor Cb.
Cs has especially an influence on the THD+N in high frequency (above 7kHz) and indirectly on the power
supply disturbances.
With 1µF, you could expect similar THD+N performances like shown in the datasheet.
If Cs is lower than 1µF, THD+N increases in high frequency and disturbances on the power supply rail are
less filtered.
To the contrary, if Cs is higher than 1µF, those disturbances on the power supply rail are more filtered.
Cb has an influence on THD+N in lower frequency, but its value is critical on the final result of PSRR with
input grounded in lower frequency:
•
If Cb is lower than 1µF, THD+N increases at lower frequencies and the PSRR worsens upwards.
•
If Cb is higher than 1µF, the benefit on THD+N and PSRR in the lower frequency range is small.
5.5 Startup time
When the TS4851 is controlled to switch from the full standby mode (output mode 0) to another output
mode, a delay is necessary to stabilize the DC bias. This delay depends on the Cb value and can be
calculated by the following formulas.
Typical startup time = 0.0175 x Cb (s)
Max. startup time = 0.025 x Cb (s)
(Cb is in µF in these formulas)
These formulas assume that the Cb voltage is equal to 0V. If the Cb voltage is not equal to 0V, the startup
time will be always lower.
The startup time is the delay between the negative edge of Enable input (see Description of SPI operation
on page 3) and the power ON of the output amplifiers.
Note: When the TS4851 is set in full standby mode, Cb is discharged through an internal switch.. The time to reach 0V
of Cb voltage is about ms.
22/28
Application Information
TS4851
5.6 Pop and Click performance
The TS4851 has internal Pop and Click reduction circuitry. The performance of this circuitry is closely
linked with the value of the input capacitor Cin and the bias voltage bypass capacitor Cb.
The value of Cin is due to the lower cut-off frequency value requested. The value of Cb is due to THD+N
and PSRR requested always in lower frequency.
The TS4851 is optimized to have a low pop and click in the typical schematic configuration (see page 2).
Note: The value of Cs is not an important consideration as regards pop and click.
5.7 Notes on PSRR measurement
What is the PSRR?
The PSRR is the Power Supply Rejection Ratio. The PSRR of a device, is the ratio between a power
supply disturbance and the result on the output. We can say that the PSRR is the ability of a device to
minimize the impact of power supply disturbances to the output.
How we measure the PSRR?
The PSSR was measured according to the schematic shown in Figure 61.
Figure 61: PSRR measurement schematic
Principles of operation
•
The DC voltage supply (Vcc) is fixed.
•
The AC sinusoidal ripple voltage (Vripple) is fixed.
•
No bypass capacitor Cs is used.
The PSRR value for each frequency is:
⎡ RMS
PSRR = 20 × Log ⎢
⎣⎢ RMS
⎤
⎥
⎥
) ⎦
( Output )
( Vripple
( dB )
RMS is a rms selective measurement.
5.8 Power-On Reset
When Power is applied to Vdd, an internal Power On Reset holds the TS4851 in a reset state until the
Supply Voltage reached its nominal value.
The Power On reset has a typical threshold at 1.8V.
23/28
TS4851
Package Information
6 Package Information
Flip-chip - 18 bumps: TS4851JT
Pin out (top view)
7
R
OUT-
6
5
3
VCC
L
IN
PHONE
IN
BYPASS
A
DATA
NC
VCC
SPKR
OUT +
2
1
L
OUT +
R
OUT +
R
IN
4
L
OUT -
GND
ENB
SPKR
OUT -
GND
B
C
CLK
D
E
Note: The solder bumps are on the underside.
Marking (top view):
The following markings are present on the topside of the flip-chip:
l The ST logo.
l The part number: A51.
l A 3-digit date code: YWW.
l A dot marking the location of Pin1A.
E
A51
YWW
24/28
Symbol for
Lead-Free
Package Information
TS4851
TS4851 Footprint recommendation
866µm
Φ=250µm
75µm Min
100µm max.
433µm
Track
Φ=400µm
250µm
150µm min.
Non Solder mask opening
Pad in Cu 18µm thickness with Flash NiAu (6µm, 0.15µm)
Package mechanical data
Symmetry axis
2440um
Die size: 2170µm x 2440µm ±30µm
Die height (including bumps): 600µm ±30µm
2170um
335um 500um
750um
Symmetry axis
Bumps diameter: 315µm ±50µm
Bumps height: 250µm ±40µm
Pitch: 500µm ±10µm
866um
354um
866um
600um
25/28
TS4851
Daisy Chain Samples
7 Daisy Chain Samples
A daisy chain sample is a “dummy” silicon chip that can be used to test your flip-chip soldering process
and connection continuity. The daisy chain sample features paired connections between bumps, as
shown in the schematic below. On your PCB layout, you should design the bump connections such that
they are complementary to the above schema (meaning that different pairs of bumps are connected on
the PCB side). In this way, by simply connecting an ohmmeter between pin 1A and pin 5A, you can test
the continuity of your soldering process.
The order code for daisy chain samples is given below.
Figure 62: Daisy chain sample mechanical data
2.44 mm
7
R
OUT-
6
5
3
R
IN
VCC
L
IN
2.17 mm
NC
BYPASS
ENB
SPKR
OUT -
SPKR
OUT +
A
DATA
VCC
PHONE
IN
2
1
L
OUT +
R
OUT +
4
L
OUT -
GND
GND
B
C
CLK
D
E
Order code for daisy chain samples
Package
Part Number
Temperature Range
Marking
J
TSDC02IJT
26/28
-40, +85°C
•
DC2
Tape & Reel Specification
TS4851
8 Tape & Reel Specification
Figure 63: Top view of tape and reel
1
A
1
A
User direction of feed
Device orientation
The devices are oriented in the carrier pocket with pin number 1A adjacent to the sprocket holes.
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TS4851
Revision History
9 Revision History
Date
Revision
Description of Changes
01 July 2002
1
First Release
01 April 2003
2
Curves inserted in the document
01 April 2004
3
Curves updated in the document
01 Jan. 2005
4
Leadfree codification added in the document
01 March 2005
5
Realignment of curve data in the document
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