STMICROELECTRONICS VIPER100ASP-E

VIPer100A-E
VIPer100ASP-E
SMPS PRIMARY I.C.
General Features
In
VDSS
Type
RDS(on)
10
VIPer100A-E/ASP-E
700V
2.8 Ω
3A
1
■
ADJUSTABLE SWITCHING FREQUENCY UP
TO 200 kHz
■
CURRENT MODE CONTROL
■
SOFT START AND SHUTDOWN CONTROL
■
AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
“BLUE ANGEL” NORM (<1w TOTAL POWER
CONSUMPTION)
POWERSO-10TM
PENTAWATT HV
PENTAWATT HV (022Y)
■
INTERNALLY TRIMMED ZENER
REFERENCE
■
UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
■
INTEGRATED START-UP SUPPLY
■
OVER-TEMPERATURE PROTECTION
■
LOW STAND-BY CURRENT
■
ADJUSTABLE CURRENT LIMITATION
Description
VIPer100A-E/ASP-E, made using VIPower M0
Technology, combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized, high voltage, Vertical Power MOSFET
(700V/ 3A).
Typical applications cover offline power supplies
with a secondary power capability of 50W in wide
range condition and 100W in single range or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50% less components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the ability to operate in stand-by mode
without extra components.
Block Diagram
DRAIN
OSC
ON/OFF
OSCILLATOR
SECURITY
LATCH
UVLO
LOGIC
VDD
R/S
FF
Q
S
PWM
LATCH
S
R1 FF Q
R2 R3
OVERTEMP.
DETECTOR
0.5 V
+
_
1.7 µ s
DELAY
250 ns
BLANKING
4.5 V
FC00231
+
COMP
September 2005
1 V/A
CURRENT
AMPLIFIER
ERROR
_ AMPLIFIER
13 V
0.5V
_
+ +
_
SOURCE
Rev 1
1/31
www.st.com
31
VIPer100A-E/ASP-E
Contents
1
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
Drain Pin (Integrated Power MOSFET Drain): . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2
Source Pin: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3
VDD Pin (Power Supply): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4
Compensation Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5
OSC Pin (Oscillator Frequency): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Typical Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Operation Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/31
5.1
Current Mode Topology: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.2
Stand-by Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.3
High Voltage Start-up Current Suorce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4
Transconductance Error Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.5
External Clock Synchronization: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.6
Primary Peak Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.7
Over-Temperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.8
Operation Pictures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VIPer100A-E/ASP-E
6
Electrical Over Stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1
7
Electrical Over Stress Ruggedness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9
Order Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/31
VIPer100A-E/ASP-E
1 Electrical Data
1
Electrical Data
1.1
Maximum Rating
Table 1.
Absolute Maximum Rating
Symbol
VDS
ID
Parameter
Continuous Drain-Source Voltage (TJ = 25 to 125°C)
Maximum Current
Value
Unit
–0.3 to 700
V
Internally limited
A
0 to 15
V
VDD
Supply Voltage
VOSC
Voltage Range Input
0 to VDD
V
VCOMP
Voltage Range Input
0 to 5
V
ICOMP
Maximum Continuous Current
±2
mA
VESD
Electrostatic Discharge (R =1.5kΩ; C=100pF)
4000
V
ID(AR)
Avalanche Drain-Source Current, Repetitive or Not Repetitive
(Tc=100°C; Pulse width limited by TJ max; δ < 1%)
1.4
A
Power Dissipation at Tc = 25ºC
82
W
Internally limited
°C
-65 to 150
°C
Ptot
Tj
Tstg
4/31
Junction Operating Temperature
Storage Temperature
VIPer100A-E/ASP-E
1.2
1 Electrical Data
Electrical Characteristics
TJ = 25°C; V DD = 13V, unless otherwise specified
Table 2.
Power Section
Symbol
Parameter
BVDS
Drain-Source Voltage
IDSS
Off-State Drain
Current
Test Conditions
ID = 1mA; VCOMP = 0V
Min
Typ
Max
700
Unit
V
VCOMP = 0V; T j = 125°C
VDS = 700V
2.0
mA
2.8
5.0
Ω
Static Drain-Source
On Resistance
ID = 2A; Tj = 100°C
tf
Fall Time
ID = 0.2A; VIN =300V (1)Figure 7
100
ns
tr
Rise Time
ID = 0.4A; VIN = 300V (1)Figure 7
50
ns
Output Capacitance
VDS = 25V
150
pF
RDS(on)
Coss
ID = 2A
1
(1) On Inductive Load, Clamped.
Table 3.
Symbol
IDDch
Supply Section
Parameter
Start-Up Charging Current
Test Conditions
Min
VDD = 5V; V DS = 35V
Typ
Max
-2
Unit
mA
(see Figure 6)(see Figure 11)
IDD0
Operating Supply Current
VDD = 12V; FSW = 0kHz
12
16
mA
(see Figure 6)
IDD1
Operating Supply Current
VDD = 12V; Fsw = 100kHz
15.5
mA
VDD = 12V; Fsw = 200kHz
19
mA
VDDoff
Undervoltage Shutdown
(see Figure 6)
VDDon
Undervoltage Reset
(see Figure 6)
VDDhyst
Hysteresis Start-up
(see Figure 6)
Table 4.
Symbol
FSW
7.5
8
9
V
11
12
V
2.4
3
V
Min
Typ
Max
Unit
90
100
110
KHz
Oscillator Section
Parameter
Oscillator Frequency Total
Variation
Test Conditions‘
RT=8.2KΩ; CT=2.4nF
VDD=9 to 15V;
with RT± 1%; CT± 5%
(see Figure 10)(see Figure 14)
VOSCIH
Oscillator Peak Voltage
7.1
V
VOSCIL
Oscillator Valley Voltage
3.7
V
5/31
VIPer100A-E/ASP-E
1 Electrical Data
Table 5.
Symbol
Error Amplifier Section
Parameter
Test Conditions‘
VDDREG
VDD Regulation Point
ICOMP=0mA (see Figure 5)
∆VDDreg
Total Variation
Tj=0 to 100°C
GBW
Unity Gain Bandwidth
From Input =VDD to
Min
Typ
Max
Unit
12.6
13
13.4
V
2
%
150
KHz
dB
Output = VCOMP
COMP pin is open
(see Figure 15)
AVOL
Open Loop Voltage Gain
COMP pin is open
(see Figure 15)
45
52
Gm
DC Transconductance
VCOMP=2.5V(see Figure 5)
1.1
1.5
VCOMPLO
Output Low Level
ICOMP=-400µA; V DD=14V
0.2
V
VCOMPHI
Output High Level
ICOMP=400µA; VDD=12V
4.5
V
ICOMPLO
Output Low Current Capability VCOMP=2.5V; VDD=14V
-600
µA
ICOMPHI
Output High Current
Capability
600
µA
Table 6.
Symbol
HID
VCOMPoff
IDpeak
VCOMP=2.5V; VDD=12V
mA/V
PWM Comparator Section
Parameter
Test Conditions‘
∆VCOMP / ∆IDPEAK
VCOMP = 1 to 3 V
VCOMP Offset
IDPEAK = 10mA
Peak Current Limitation
VDD = 12V; COMP pin open
Min
Typ
Max
Unit
0.7
1
1.3
V/A
0.5
3
4
V
5.3
A
td
Current Sense Delay to Turn- ID = 1A
Off
250
tb
Blanking Time
250
360
ns
Minimum On Time
350
1200
ns
Typ
Max
Unit
ton(min)
Table 7.
Symbol
VCOMPth
Parameter
Test Conditions‘
Min
(see Figure 8)
0.5
Disable Set Up Time
(see Figure 8)
1.7
Ttsd
Thermal Shutdown
Temperature
(see Figure 8)
Thyst
Thermal Shutdown Hysteresis (see Figure 8)
tDISsu
ns
Shutdown and Overtemperature Section
Restart Threshold
6/31
1.9
140
V
5
µs
170
°C
40
°C
VIPer100A-E/ASP-E
2
2 Thermal Data
Thermal Data
Table 8.
Symbol
Thermal data
Parameter
PENTAWATT HV
Unit
RthJC
Thermal Resistance Junction-case
Max
1.4
°C/W
RthJA
Thermal Resistance Ambient-case
Max
60
°C/W
7/31
3 Pin Description
3
Pin Description
3.1
Drain Pin (Integrated Power MOSFET Drain):
VIPer100A-E/ASP-E
Integrated Power MOSFET drain pin. It provides internal bias current during start-up via an
integrated high voltage current source which is switched off during normal operation. The
device is able to handle an unclamped current during its normal operation, assuring self
protection against voltage surges, PCB stray inductance, and allowing a snubberless operation
for low output power.
3.2
Source Pin:
Power MOSFET source pin. Primary side circuit common ground connection.
3.3
VDD Pin (Power Supply):
This pin provides two functions :
3.4
●
It corresponds to the low voltage supply of the control part of the circuit. If VDD goes below
8V, the start-up current source is activated and the output power MOSFET is switched off
until the VDD voltage reaches 11V. During this phase, the internal current consumption is
reduced, the VDD pin is sourcing a current of about 2mA and the COMP pin is shorted to
ground. After that, the current source is shut down, and the device tries to start up by
switching again.
●
This pin is also connected to the error amplifier, in order to allow primary as well as
secondary regulation configurations. In case of primary regulation, an internal 13V
trimmed reference voltage is used to maintain VDD at 13V. For secondary regulation, a
voltage between 8.5V and 12.5V will be put on VDD pin by transformer design, in order to
stuck the output of the transconductance amplifier to the high state. The COMP pin
behaves as a constant current source, and can easily be connected to the output of an
optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the
error amplifier through the VDD voltage, which cannot overpass 13V. The output voltage
will be somewhat higher than the nominal one, but still under control.
Compensation Pin
This pin provides two functions :
8/31
●
It is the output of the error transconductance amplifier, and allows for the connection of a
compensation network to provide the desired transfer function of the regulation loop. Its
bandwidth can be easily adjusted to the needed value with usual components value. As
stated above, secondary regulation configurations are also implemented through the
COMP pin.
●
When the COMP voltage is going below 0.5V, the shut-down of the circuit occurs, with a
zero duty cycle for the power MOSFET. This feature can be used to switch off the
converter, and is automatically activated by the regulation loop (no matter what the
configuration is) to provide a burst mode operation in case of negligible output power or
open load condition.
VIPer100A-E/ASP-E
3.5
3 Pin Description
OSC Pin (Oscillator Frequency):
An Rt-Ct network must be connected on that to define the switching frequency. Note that
despite the connection of Rt to VDD, no significant frequency change occurs for VDD varying
from 8V to 15V. It provides also a synchronisation capability, when connected to an external
frequency source.
Figure 1.
Connection Diagrams (Top View)
PENTAWATT HV
Figure 2.
PowerSO-10TM
PENTAWATT HV (022Y)
Current and Voltage Convention
IDD
ID
VDD
IOSC
DRAIN
OSC
13V
+
COMP SOURCE
VDD
VDS
ICOMP
VOSC
VCOMP
FC00020
9/31
VIPer100A-E/ASP-E
4 Typical Circuit
4
Typical Circuit
Figure 3.
Offline Power Supply With Auxiliary Supply Feedback
F1
BR1
TR2
C1
TR1
D2
AC IN
L2
+Vcc
D1
R9
C2
C7
C9
R1
C3
GND
D3
C10
R7
C4
R2
VDD
DRAIN
-
U1
OSC
VIPer100
+
13V
COMP SOURCE
C5
C6
C11
R3
FC00081
Figure 4.
Offline Power Supply With Optocoupler Feedback
F1
BR1
TR2
C1
TR1
D2
AC IN
L2
+Vcc
D1
R9
C2
C7
C9
R1
C3
GND
D3
C10
R7
C4
R2
VDD
DRAIN
-
U1
OSC
13V
VIPer100
+
COMP SOURCE
C5
C11
C6
R3
R6
ISO1
R4
C8
U2
R5
FC00091
10/31
VIPer100A-E/ASP-E
5
Operation Description
5.1
Current Mode Topology:
5 Operation Description
The current mode control method, like the one integrated in the VIPer100A-E/ASP-E, uses two
control loops - an inner current control loop and an outer loop for voltage control. When the
Power MOSFET output transistor is on, the inductor current (primary side of the transformer) is
monitored with a SenseFET technique and converted into a voltage VS proportional to this
current. When VS reaches VCOMP (the amplified output voltage error) the power switch is
switched off. Thus, the outer voltage control loop defines the level at which the inner loop
regulates peak current through the power switch and the primary winding of the transformer.
Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input
voltage feedforward characteristic of the current mode control. This results in improved line
regulation, instantaneous correction to line changes, and better stability for the voltage
regulation loop.
Current mode topology also ensures good limitation in case there is a short circuit. During the
first phase the output current increases slowly following the dynamic of the regulation loop.
Then it reaches the maximum limitation current internally set and finally stops because the
power supply on VDD is no longer correct. For specific applications the maximum peak current
internally set can be overridden by externally limiting the voltage excursion on the COMP pin.
An integrated blanking filter inhibits the PWM comparator output for a short time after the
integrated Power MOSFET is switched on. This function prevents anomalous or premature
termination of the switching pulse in case there are current spikes caused by primary side
capacitance or secondary side rectifier reverse recovery time.
5.2
Stand-by Mode
Stand-by operation in nearly open load conditions automatically leads to a burst mode
operation allowing voltage regulation on the secondary side. The transition from normal
operation to burst mode operation happens for a power PSTBY given by :
Where:
1
2
F
P STBY = --- L P I STBY SW
2
LP is the primary inductance of the transformer. FSW is the normal switching frequency.
ISTBY is the minimum controllable current, corresponding to the minimum on time that the
device is able to provide in normal operation. This current can be computed as :
( t b + t d )V IN
I STBY = ----------------------------Lp
tb + td is the sum of the blanking time and of the propagation time of the internal current sense
and comparator, and represents roughly the minimum on time of the device. Note: that PSTBY
may be affected by the efficiency of the converter at low load, and must include the power
drawn on the primary auxiliary voltage.
11/31
5 Operation Description
VIPer100A-E/ASP-E
As soon as the power goes below this limit, the auxiliary secondary voltage starts to increase
above the 13V regulation level, forcing the output voltage of the transconductance amplifier to
low state (VCOMP < VCOMPth). This situation leads to the shutdown mode where the power
switch is maintained in the Off state, resulting in missing cycles and zero duty cycle. As soon as
VDD gets back to the regulation level and the VCOMPth threshold is reached, the device
operates again. The above cycle repeats indefinitely, providing a burst mode of which the
effective duty cycle is much lower than the minimum one when in normal operation. The
equivalent switching frequency is also lower than the normal one, leading to a reduced
consumption on the input main supply lines. This mode of operation allows the VIPer100A-E/
ASP-E to meet the new German "Blue Angel" Norm with less than 1W total power consumption
for the system when working in stand-by mode. The output voltage remains regulated around
the normal level, with a low frequency ripple corresponding to the burst mode. The amplitude of
this ripple is low, because of the output capacitors and low output current drawn in such
conditions.The normal operation resumes automatically when the power gets back to higher
levels than PSTBY.
5.3
High Voltage Start-up Current Source
An integrated high voltage current source provides a bias current from the DRAIN pin during
the start-up phase. This current is partially absorbed by internal control circuits which are
placed into a standby mode with reduced consumption and also provided to the external
capacitor connected to the VDD pin. As soon as the voltage on this pin reaches the high voltage
threshold VDDon of the UVLO logic, the device becomes active mode and starts switching. The
start-up current generator is switched off, and the converter should normally provide the
needed current on the VDD pin through the auxiliary winding of the transformer, as shown on
(see Figure 11).
In case there are abnormal conditions where the auxiliary winding is unable to provide the low
voltage supply current to the VDD pin (i.e. short circuit on the output of the converter), the
external capacitor discharges to the low threshold voltage VDDoff of the UVLO logic, and the
device goes back to the inactive state where the internal circuits are in standby mode and the
start-up current source is activated. The converter enters a endless start-up cycle, with a startup duty cycle defined by the ratio of charging current towards discharging when the device tries
to start. This ratio is fixed by design to 2A to 15A, which gives a 12% start-up duty cycle while
the power dissipation at start-up is approximately 0.6W, for a 230Vrms input voltage.
This low value start-up duty cycle prevents the application of stress to the output rectifiers as
well as the transformer when a short circuit occurs.
The external capacitor CVDD on the VDD pin must be sized according to the time needed by the
converter to start up, when the device starts switching. This time tSS depends on many
parameters, among which transformer design, output capacitors, soft start feature, and
compensation network implemented on the COMP pin. The following formula can be used for
defining the minimum capacitor needed:
where:
I t
DD SS
C VD D > -------------------V DD hyst
IDD is the consumption current on the VDD pin when switching. Refer to specified I DD1 and IDD2
values.
tSS is the start up time of the converter when the device begins to switch. Worst case is
generally at full load.
12/31
VIPer100A-E/ASP-E
5 Operation Description
VDDhyst is the voltage hysteresis of the UVLO logic (refer to the minimum specified value).
The soft start feature can be implemented on the COMP pin through a simple capacitor which
will be also used as the compensation network. In this case, the regulation loop bandwidth is
rather low, because of the large value of this capacitor. In case a large regulation loop
bandwidth is mandatory, the schematics of (see Figure 17) can be used. It mixes a high
performance compensation network together with a separate high value soft start capacitor.
Both soft start time and regulation loop bandwidth can be adjusted separately.
If the device is intentionally shut down by tying the COMP pin to ground, the device is also
performing start-up cycles, and the VDD voltage is oscillating between VDDon and VDDoff.
This voltage can be used for supplying external functions, provided that their consumption does
not exceed 0.5mA. (see Figure 18) shows a typical application of this function, with a latched
shutdown. Once the "Shutdown" signal has been activated, the device remains in the Off state
until the input voltage is removed.
5.4
Transconductance Error Amplifier
The VIPer100A-E/ASP-E includes a transconductance error amplifier. Transconductance Gm is
the change in output current (ICOMP) versus change in input voltage (VDD). Thus:
∂l COMP
G m = ------------------∂V DD
The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as:
V
V
∂ CO MP
1
∂ COMP
- = -------- × ------------------------Z CO MP = -------------------I
G
∂V DD
m
∂ COMP
This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP:
AVOL = Gm x ZCOMP
where Gm value for VIPer100A-E/ASP-E is 1.5 mA/V typically.
Gm is defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances.
An impedance Z can be connected between the COMP pin and ground in order to define the
transfer function F of the error amplifier more accurately, according to the following equation
(very similar to the one above):
F(S) = Gm x Z(S)
The error amplifier frequency response is reported in Figure 10. for different values of a simple
resistance connected on the COMP pin. The unloaded transconductance error amplifier shows
an internal ZCOMP of about 330KΩ. More complex impedance can be connected on the COMP
pin to achieve different compensation level. A capacitor will provide an integrator function, thus
eliminating the DC static error, and a resistance in series leads to a flat gain at higher
frequency, insuring a correct phase margin. This configuration is illustrated in Figure 20
As shown in Figure 19 an additional noise filtering capacitor of 2.2nF is generally needed to
avoid any high frequency interference.
Is also possible to implement a slope compensation when working in continuous mode with
duty cycle higher than 50%. Figure 21 shows such a configuration. Note: R1 and C2 build the
classical compensation network, and Q1 is injecting the slope compensation with the correct
polarity from the oscillator sawtooth.
13/31
5 Operation Description
5.5
VIPer100A-E/ASP-E
External Clock Synchronization:
The OSC pin provides a synchronisation capability when connected to an external frequency
source. Figure 21 shows one possible schematic to be adapted, depending the specific needs.
If the proposed schematic is used, the pulse duration must be kept at a low value (500ns is
sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through
the optotransistor.
5.6
Primary Peak Current Limitation
The primary IDPEAK current and, consequently, the output power can be limited using the
simple circuit shown in Figure 22 . The circuit based on Q1, R1 and R2 clamps the voltage on
the COMP pin in order to limit the primary peak current of the device to a value:
V COMP – 0.5
I D PEAK = -------------------------------H ID
where:
R1 + R 2
V COMP = 0.6 × ------------------R2
The suggested value for R1+R2 is in the range of 220KΩ.
5.7
Over-Temperature Protection
Over-temperature protection is based on chip temperature sensing. The minimum junction
temperature at which over-temperature cut-out occurs is 140ºC, while the typical value is
170ºC. The device is automatically restarted when the junction temperature decreases to the
restart temperature threshold that is typically 40ºC below the shutdown value (see Figure 13)
14/31
VIPer100A-E/ASP-E
5.8
5 Operation Description
Operation Pictures
Figure 5.
VDD Regulation Point
ICOMP
Figure 6.
Undervoltage Lockout
IDD
Slope =
Gmin mA/V
ICOMPHI
IDD0
VDD
0
VDDhyst
ICOMPLO
VDDoff
VD S= 35 V
Fsw = 0
VDDon VDD
IDDch
VDDreg
FC00170
FC00150
Figure 7.
Transition Time
Figure 8.
Shutdown Action
VOSC
ID
t
VCOMP
tDISsu
10% Ipeak
t
VDS
VCOMPth
90% VD
t
ID
10% VD
t
tf
tr
t
FC00160
ENABLE
ENABLE
DISABLE
FC00060
Figure 9.
Breakdown Voltage vs. Temperature Figure 10. Typical Frequency Variation
FC00190
FC00180
1.15
(%)
BVDSS
1
0
(Normalized)
1.1
-1
-2
1.05
-3
1
0.95
-4
-5
0
20
40 60 80 100 120
Temperature (°C)
0
20
40 60 80 100 120 140
Temperature (°C)
15/31
VIPer100A-E/ASP-E
5 Operation Description
Figure 11. Behaviour of the high voltage current source at start-up
VDD
2 mA
VDDon
VDDoff
3 mA
VDD
15 mA
DRAIN
1 mA 15 mA
CVDD
Ref.
t
Auxiliary primary
winding
UNDERVOLTAGE
LOCK OUT LOGIC
VIPer100
SOURCE
Start up duty cycle ~ 12%
FC00100
Figure 12. Start-Up Waveforms
16/31
VIPer100A-E/ASP-E
5 Operation Description
Figure 13. Over-temperature Protection
T
T ts c J
T t s d -T h y s t
Vdd
V dd on
V dd off
Id
V
co m p
0000 00 0 0 0 0 0 0 00000000000000000000000000 00 00
0000 0 0 0 0
00 0 00 0 00 00 00 00 00 00 0 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0000
000000
00 0
00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t
00 00 0 0 0 0 0 0 0 0 0 0 0 0 0
0000000000000000
00000000 00 00 00 00 00 00 00 00 00 00 000000 00 0 0 0 00 00 00 00 00 00 000000 00 0 0 0
00
00 00 00 00 0 0 00 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 00 00 00 00 00 00 00 00 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0t
00 00 00 00 00 00 00 00 00 00 00 00 00 0 0
00 00 00 00 00
0
0
00 00 00 00 00 00 00 00 00 00 00 00 00
0 0000000000000000000000000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 00 00 00 00 0 0 0 0 0 t
00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
00 0 0 0 0 0 0 0 0 0 0 0 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 0 0
00
00 0 0 0 0 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 t
SC 1 0 1 9 1
17/31
VIPer100A-E/ASP-E
5 Operation Description
Figure 14. Oscillator
For R t > 1.2kΩ and Ct ≤ 40KHz
VDD
Rt
O SC
550
2.3
F SW = ----------- ⋅ ⎛ 1 – --------------------⎞
R t – 150⎠
RtCt ⎝
Ct
~360Ω
CLK
FC 00050
Ct
Forbidden area
880
Ct(nF) =
22nF
Fsw(kHz)
15nF
Forbidden area
40kHz
Fsw
Oscillator frequency vs Rt and Ct
FC00030
1,000
Ct = 1.5 nF
500
Frequency (kHz)
Ct = 2.7 nF
300
Ct = 4.7 nF
200
Ct = 10 nF
100
50
30
1
2
3
5
Rt (kΩ)
18/31
10
20
30
50
VIPer100A-E/ASP-E
5 Operation Description
Figure 15. Error Amplifier frequency Response
FC00200
60
RCOMP = +∞
Voltage Gain (dB)
RCOMP = 270k
40
RCOMP = 82k
RCOMP = 27k
20
RCOMP = 12k
0
(20)
0.001
0.01
0.1
1
10
Frequency (kHz)
100
1,000
Figure 16. Error Amplifier Phase Response
FC00210
200
RCOMP = +∞
150
RCOMP = 270k
Phase (°)
RCOMP = 82k
RCOMP = 27k
100
RCOMP = 12k
50
0
(50)
0.001
0.01
0.1
1
10
Frequency (kHz)
100
1,000
19/31
VIPer100A-E/ASP-E
5 Operation Description
Figure 17. Mixed Soft Start and Compensation Figure 18. Latched Shut Down
D2
U1
VIPER100
VDD
U1
VIPER100
D3
R1
DRAIN
VDD
OSC
13V
COMP
DRAIN
Q2
R3
+
-
OSC
SOURCE
+
13V
D1
COMP SOURCE
AUXILIARY
WINDING
R3
R2
R1
C4
R2
+ C3
R4
Shutdown
+ C2
C1
D1
Q1
FC00131
FC00110
Figure 19. Typical Compensation Network
Figure 20. Slope Compensation
U1
VIPER100
VDD
R2
DRAIN
R1
U1
V IP E R 1 0 0
-
OSC
13V
VDD
+
COMP
D R A IN
-
OSC
SOURCE
+
1 3V
C OM P
C2
SO U R C E
C2
R1
Q1
C3
C1
C1
R3
F C00141
FC00121
Figure 21. External Clock Synchronization
Figure 22. Current Limitation Circuit Example
U1
V IP E R 1 0 0
U1
VIPER100
VDD
VDD
DRAIN
O SC
13V
-
D R A IN
+
OSC
13V
COMP
+
COMP
SO URCE
SOURCE
10 kΩ
R1
Q1
R2
FC00220
FC 00240
20/31
VIPer100A-E/ASP-E
6 Electrical Over Stress
6
Electrical Over Stress
6.1
Electrical Over Stress Ruggedness
The VIPer may be submitted to electrical over-stress, caused by violent input voltage surges or
lightning. Following the Layout Considerations is sufficient to prevent catastrophic damages
most of the time. However in some cases, the voltage surges coupled through the transformer
auxiliary winding can exceed the VDD pin absolute maximum rating voltage value. Such events
may trigger the VDD internal protection circuitry which could be damaged by the strong
discharge current of the VDD bulk capacitor. The simple RC filter shown in Figure 23 can be
implemented to improve the application immunity to such surges.
Figure 23. Input Voltage Surges Protection
R1
D1
(Optional)
R2
39R
Auxilliary winding
C1
Bulk capacitor
VDD
C2
22nF
DRAIN
OSC
13V
VIPerXX0
+
COMP SOURCE
21/31
VIPer100A-E/ASP-E
7 Layout
7
Layout
7.1
Layout Considerations
Some simple rules insure a correct running of switching power supplies. They may be
classified into two categories:
–
Minimizing power loops: The switched power current must be carefully analysed and
the corresponding paths must be as small an inner loop area as possible. This avoids
radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a
better efficiency by eliminating parasitic inductances, especially on secondary side.
–
Using different tracks for low level and power signals: Interference due to mixing of
signal and power may result in instabilities and/or anomalous behavior of the device
in case of violent power surge (Input overvoltages, output short circuits...).
In case of VIPer, these rules apply as shown on (see Figure 24).
–
Loops C1-T1-U1, C5-D2-T1, and C7-D1-T1 must be minimized.
–
C6 must be as close as possible to T1.
–
Signal components C2, ISO1, C3, and C4 are using a dedicated track connected
directly to the power source of the device.
Figure 24. Recommended Layout
T1
D1
C7
D2
R1
VDD
DRAIN
-
C1
OSC
13V
From input
diodes bridge
C5
+
COMP
SOURCE
U1
VIPerXX0
R2
C6
C2
C3
ISO1
C4
FC00500
22/31
To secondary
filtering and load
VIPer100A-E/ASP-E
8
8 Package Mechanical Data
Package Mechanical Data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second Level Interconnect is marked on the package and on the inner box label, in compliance
with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are
available at: www.st.com.
23/31
VIPer100A-E/ASP-E
8 Package Mechanical Data
Pentawatt HV Mechanical Data
mm.
inch
Dim
Min.
Typ.
Maw.
Min.
Typ.
A
4.30
4.80
0.169
0.189
C
1.17
1.37
0.046
0.054
D
2.40
2.80
0.094
0.11
E
0.35
0.55
0.014
0.022
F
0.60
0.80
0.024
0.031
G1
4.91
5.21
0.193
0.205
G2
7.49
7.80
0.295
0.307
H1
9.30
9.70
0.366
0.382
H2
10.40
0.409
H3
10.05
10.40
L
15.60
17.30
6.14
0.681
L1
14.60
15.22
0.575
0.599
L2
21.20
21.85
0.835
0.860
L3
22.20
22.82
0.874
0.898
L5
2.60
3
0.102
0.118
L6
15.10
15.80
0.594
0.622
L7
6
6.60
0.236
0.260
M
2.50
3.10
0.098
0.122
M1
4.50
5.60
0.177
0.220
R
0.50
Diam
0.396
0.409
0.02
90°
V4
3.65
3.85
0.144
0.152
P023H3
24/31
Max.
VIPer100A-E/ASP-E
8 Package Mechanical Data
Pentawatt HV 022Y ( Vertical High Pitch ) Mechanical Data
mm.
inch
Dim
Min.
Typ.
Maw.
Min.
Typ.
Max.
A
4.30
4.80
0.169
0.189
C
1.17
1.37
0.046
0.054
D
2.40
2.80
0.094
0.110
E
0.35
0.55
0.014
0.022
F
0.60
0.80
0.024
0.031
G1
4.91
5.21
0.193
0.205
G2
7.49
7.80
0.295
0.307
H1
9.30
9.70
0.366
0.382
H2
10.40
0.409
H3
10.05
10.40
0.396
0.409
L
16.42
17.42
0.646
0.686
L1
14.60
15.22
0.575
0.599
L3
20.52
21.52
0.808
0.847
L5
2.60
3.00
0.102
0.118
L6
15.10
15.80
0.594
0.622
L7
6.00
6.60
0.236
0.260
M
2.50
3.10
0.098
0.122
M1
5.00
5.70
0.197
0.224
R
0.50
V4
90°
Diam
0.02
0.020
90°
3.65
3.85
0.144
0.154
L
L1
E
A
M
M1
C
D
R
Resin between
leads
L6
L7
V4
H2
H3
H1
G1
G2
F
DIA
L5
L3
25/31
VIPer100A-E/ASP-E
8 Package Mechanical Data
Figure 25. Pentawatt HV Tube Shipment ( no suffix )
Base Q.ty
50
Bulk Q.ty
1000
Tube length ( ± 0.5 )
532
A
18
B
33.1
C ( ± 0.1)
1
All dimensions are in mm.
26/31
VIPer100A-E/ASP-E
8 Package Mechanical Data
PowerSO-10 MECHANICAL DATA
mm
DIM.
MIN.
inch
MAX.
MIN.
A
3.35
TYP.
3.65
0.132
0.144
A1
0.00
0.10
0.000
0.004
B
0.40
0.60
0.016
0.024
C
0.35
0.55
0.013
0.022
D
9.40
9.60
0.370
0.378
D1
7.40
7.60
0.291
e
1.27
TYP.
MAX.
0.300
0.050
E
9.30
9.50
0.366
0.374
E1
7.20
7.40
0.283
0.291
E2
7.20
7.60
0.283
0.300
E3
6.10
6.35
0.240
0.250
E4
5.90
6.10
0.232
0.240
F
1.25
1.35
0.049
h
0.50
0.053
0.002
H
13.80
14.40
0.543
0.567
L
1.20
1.80
0.047
0.071
q
1.70
0.067
0o
α
8o
B
0.10 A B
10
=
E4
=
=
=
E1
=
E3
=
E2
=
E
=
=
=
H
6
=
=
1
5
B
e
0.25
SEATING
PLANE
DETAIL "A"
A
C
M
Q
D
h
= D1 =
=
=
SEATING
PLANE
A
F
A1
A1
L
DETAIL "A"
α
0068039-C
27/31
VIPer100A-E/ASP-E
8 Package Mechanical Data
PowerSO-10™ SUGGESTED PAD LAYOUT
TUBE SHIPMENT (no suffix)
14.6 - 14.9
CASABLANCA
B
10.8 - 11
MUAR
C
6.30
C
A
A
0.67 - 0.73
1
9.5
2
3
4
5
10
9
B
0.54 - 0.6
All dimensions are in mm.
8
7
1.27
Base Q.ty Bulk Q.ty Tube length (± 0.5)
6
Casablanca
Muar
50
50
1000
1000
532
532
A
B
C (± 0.1)
10.4 16.4
4.9 17.2
TAPE AND REEL SHIPMENT (suffix “13TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
600
600
330
1.5
13
20.2
24.4
60
30.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
24
4
24
1.5
1.5
11.5
6.5
2
All dimensions are in mm.
End
Start
Top
No components
Components
No components
cover
tape
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
28/31
500mm min
0.8
0.8
VIPer100A-E/ASP-E
9
9 Order Codes
Order Codes
PENTAWATT HV
PENTAWATT HV (022Y)
PowerSO-10
VIPer100A-E
VIPer100A-22-E
VIPer100ASP-E
29/31
VIPer100A-E/ASP-E
10 Revision history
10
Revision history
Date
Revision
23-Sep-2005
1
30/31
Changes
Initial release.
VIPer100A-E/ASP-E
10 Revision history
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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31/31