STMICROELECTRONICS VN5160S-E

VN5160S-E
Single channel high side driver for automotive applications
Features
Max supply voltage
VCC
Operating voltage range
VCC 4.5 to 36V
Max on-state resistance (per ch.)
RON
160 mΩ
Current limitation (typ)
ILIMH
5.4 A
Off state supply current
IS
41V
2
SO-8
µA(1)
– Reverse battery protection (see Figure 28)
– Electrostatic discharge protection
(1) Typical value with all loads connected
■
Main
– Inrush current active management by
power limitation
– Very low stand-by current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
european directive
Application
■
Description
■
Diagnostic Functions
– Open drain status output
– On state open load detection
– Off state open load detection
– Thermal shutdown indication
■
Protection
– Undervoltage shut-down
– Overvoltage clamp
– Output stuck to Vcc detection
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Thermal shut down
Table 1.
All types of resistive, inductive and capacitive
loads
The VN5160S-E is a monolithic device made
using STMicroelectronics VIPower M0-5
technology. It is intended for driving resistive or
inductive loads with one side connected to
ground. Active VCC voltage clamp protects the
device against low energy spikes.The device
detects open load condition both in on and off
state, when STAT_DIS is left open or driven low.
Output shorted to VCC is detected in the off
state.When STAT_DIS is driven high, STATUS is
in a high impedance condition. Output current
limitation protects the device in overload
condition. In case of long duration overload, the
device limits the dissipated power to safe level up
to thermal shut-down intervention. Thermal shutdown with automatic restart allows the device to
recover normal operation as soon as fault
condition disappears.
Device summary
Order codes
Package
SO-8
December 2007
Tube
Tape and Reel
VN5160S-E
VN5160STR-E
Rev 3
1/31
www.st.com
31
Contents
VN5160S-E
Contents
1
Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
4
6
2/31
3.1.1
Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 20
3.1.2
Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 21
3.2
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4
Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
5
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20
SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VN5160S-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pins function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status pin (VSD=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Openload detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
List of figures
VN5160S-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
4/31
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output voltage drop lmitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Status low-output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
On-state resistance Vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
On-state resistance Vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Openload On-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Openload Off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ILIM Vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
High-level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Low-level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Maximum turn Off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 24
SO-8 Thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Thermal fitting model of a single channel HSD in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VN5160S-E
1
Block diagram and pins description
Block diagram and pins description
Figure 1.
Block diagram
VCC
VCC
CLAMP
UNDERVOLTAGE
PwCLAMP
GND
DRIVER
ILIM
INPUT
VDSLIM
LOGIC
STATUS
OPENLOAD ON
OPENLOAD OFF
STAT_DIS
OVERTEMP.
PwrLIM
Table 2.
Pins function
Name
VCC
OUTPUT
GND
INPUT
STATUS
STAT_DIS
Function
Battery connection.
Power output.
Ground connection. Must be reverse battery protected by an external
diode/resistor network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
Open drain digital diagnostic pin.
Active high CMOS compatible pin, to disable the STATUS pin.
5/31
Block diagram and pins description
Figure 2.
VN5160S-E
Configuration diagram (top view)
VCC
OUTPUT
OUTPUT
VCC
5
6
7
8
4
3
2
1
STAT_DIS
STATUS
INPUT
GND
SO-8
Table 3.
Suggested connections for unused and N.C. pins
Connection / Pin
Status
N.C.
Output
Input
STAT_DIS
Floating
X
X
X
X
X
To ground
N.R.(1)
X
N.R.
Through 10KΩ
resistor
Through 10KΩ
resistor
(1) Not recommended.
6/31
VN5160S-E
2
Electrical specifications
Electrical specifications
Figure 3.
Current and voltage conventions
IS
VCC
ISD
IOUT
STAT_DIS
VSD
VCC
VF
OUTPUT
IIN
VOUT
ISTAT
INPUT
STATUS
VINn
VSTAT
GND
IGND
Note:
VF = VOUT - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in this section for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality documents.
Table 4.
Absolute maximum ratings
Symbol
Value
Unit
DC supply voltage
41
V
- VCC
Reverse DC supply voltage
0.3
V
- IGND
DC reverse ground pin current
200
mA
Internally
limited
A
6
A
VCC
IOUT
- IOUT
Parameter
DC output current
Reverse DC output current
IIN
DC input current
+10 / -1
mA
ISTAT
DC status current
+10 / -1
mA
+10 / -1
mA
34
mJ
ISTAT_DIS DC status disable current
EMAX
Maximum switching energy (single pulse)
(L= 12mH; RL= 0Ω; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.) )
7/31
Electrical specifications
Table 4.
Parameter
Value
Unit
VESD
Electrostatic discharge (Human Body Model: R=1.5KΩ; C=100pF)
– INPUT
4000
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Junction operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
Tstg
Thermal data
Table 5.
Symbol
8/31
Absolute maximum ratings (continued)
Symbol
Tj
2.2
VN5160S-E
Thermal data
Parameter
Rthj-pins
Thermal resistance junction-pins (MAX)
Rthj-amb
Thermal resistance junction-ambient (MAX)
Value
Unit
30
°C/W
See Figure 32
°C/W
VN5160S-E
2.3
Electrical specifications
Electrical characteristics
Values specified in this section are for 8V<VCC<36V; Tj=125°C, unless otherwise stated.
Table 6.
Power section
Symbol
Parameter
VCC
Operating supply voltage
VUSD
VUSDhyst
Test conditions
Min.
Typ.
Max.
Unit
4.5
13
36
V
Undervoltage shutdown
3.5
4.5
V
Undervoltage shutdown
hysteresis
0.5
RON(1)
On state resistance
IOUT=1A; Tj=25°C
IOUT=1A; Tj=150°C
IOUT=1A; VCC=5V; Tj=25°C
Vclamp
Clamp voltage
IS= 20mA
Supply current
Off State; VCC=13V;
VIN=VOUT=0V; Tj=25°C;
On State; VCC=13V; VIN=5V;
IOUT=0A
IS
IL(off1)
Off state output
current(2)
VF
VIN=VOUT=0V; VCC=13V;
Tj=125°C
VIN= 0V; VOUT= 4V
IL(off2)
Output - VCC diode
voltage
41
V
160
320
210
mΩ
mΩ
mΩ
46
52
V
2(2)
5(1)(2)
µA
1.9
3.5
mA
0
5
µA
-75
0
-IOUT= 2A; Tj= 150°C
0.7
V
(1) Guaranteed by design/characterization
(2) PowerMOS leakage included
Table 7.
Symbol
Switching (VCC = 13V; Tj = 25°C)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
td(on)
Turn-on delay time
RL= 13Ω (see Figure 6)
10
µs
td(off)
Turn-off delay time
RL= 13Ω (see Figure 6)
15
µs
dVOUT/dt(on) Turn-on voltage slope
RL= 13Ω
See Figure 21
V/ µs
dVOUT/dt(off) Turn-off voltage slope
RL= 13Ω
See Figure 22
V/ µs
WON
Switching energy
losses during twon
RL= 13Ω (see Figure 6)
0.04
mJ
WOFF
Switching energy
losses during twoff
RL= 13Ω (see Figure 6)
0.04
mJ
9/31
Electrical specifications
Table 8.
Symbol
VN5160S-E
Status pin (VSD=0)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
0.5
V
VSTAT
Status low output voltage ISTAT= 1.6 mA, VSD= 0V
ILSTAT
Status leakage current
Normal operation or VSD= 5V,
VSTAT= 5V
10
µA
CSTAT
Status pin input
capacitance
Normal operation or VSD=5V,
VSTAT= 5V
100
pF
VSCL
Status clamp voltage
ISTAT= 1mA
ISTAT= - 1mA
7
V
V
Table 9.
Symbol
Parameter
Test conditions
DC short circuit current
VCC= 13V
5V<VCC<36V
IlimL(2)
Short circuit current during
thermal cycling
VCC= 13V; TR<Tj<TTSD
TTSD(3)
Shutdown temperature
TR(3)
Reset temperature
TRS(3)
Thermal reset of STATUS
THYST
Thermal hysteresis (TTSD-TR)
Status delay in overload
conditions
Output voltage drop limitation
Min.
Typ.
Max.
Unit
3.8
5.4
7.5
7.5
A
A
2
150
175
A
200
TRS + 1 TRS + 5
°C
7
Tj>TTSD
IOUT= 0.03A
(see Figure 5)
°C
°C
135
VDEMAG Turn-Off output voltage clamp IOUT=150mA; VIN=0
VON
-0.7
Protection (1)
IlimH(2)
tSDL
5.5
°C
20
µs
VCC-41 VCC-46 VCC-52
V
25
mV
(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
(2) Guaranteed by design/characterization.
(3) Only the block functionality is guaranteed. The threshold values are guaranteed by design/characterization
on final product.
10/31
VN5160S-E
Electrical specifications
Table 10.
Symbol
Openload detection
Parameter
Test conditions
Min.
Typ.
Max.
Unit
10
See
Figure 19
40
mA
200
µs
IOL
Openload On state
detection threshold
VIN = 5V, 8V<VCC<18V
tDOL(on)
Openload On state
detection delay
IOUT = 0A, VCC=13V
(see Figure 4)
tPOL
Delay between INPUT falling
edge and STATUS rising
IOUT = 0A (see Figure 4)
edge in openload condition
VOL
Openload Off state voltage
detection threshold
VIN = 0V, 8V<VCC<16V
tDSTKON
Output short circuit to Vcc
detection delay at turn Off
(see Figure 4)
Table 11.
Symbol
500
1000
µs
2
See
Figure 20
4
V
tPOL
µs
180
Logic input
Parameter
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
Test conditions
VIN= 0.9V
Typ.
Max.
Unit
0.9
V
1
µA
2.1
V
10
0.25
IIN= 1mA
IIN= -1mA
Input clamp voltage
VSDL
STAT_DIS low level voltage
ISDL
Low level STAT_DIS current
VSDH
STAT_DIS high level voltage
ISDH
High level STAT_DIS current VCSD= 2.1V
VCSD= 0.9V
VSD(hyst) STAT_DIS hysteresis voltage
STAT_DIS clamp voltage
Min.
VIN= 2.1V
VICL
VSDCL
200
V
5.5
7
V
V
0.9
V
-0.7
1
µA
2.1
V
10
0.25
ISD= 1mA
ISD= -1mA
µA
µA
V
5.5
7
-0.7
V
V
11/31
Electrical specifications
Figure 4.
VN5160S-E
Status timings
OPEN LOAD STATUS TIMING (with external pull-up)
OPEN LOAD STATUS TIMING (without external pull-up)
IOUT < IOL
VIN
IOUT < IOL
VIN
VOUT > VOL
VOUT < VOL
VSTAT
VSTAT
tDOL(on)
tDOL(on)
tPOL
OVER TEMP STATUS TIMING
OUTPUT STUCK TO Vcc
Tj > TTSD
IOUT > IOL
VIN
VOUT > VOL
VIN
VSTAT
VSTAT
tDOL(on)
Figure 5.
tSDL
tDSTKON
tSDL
Output voltage drop lmitation
Vcc-Vout
Tj=150oC
Tj=25oC
Tj=-40oC
Von
Von/Ron(T)
12/31
Iout
VN5160S-E
Electrical specifications
Table 12.
Truth table
Conditions
INPUT
OUTPUT
STATUS (VSD=0V)(1)
Normal operation
L
H
L
H
H
H
Current limitation
L
H
L
X
H
H
Overtemperature
L
H
L
L
H
L
Undervoltage
L
H
L
L
X
X
Output voltage > VOL
L
H
H
H
L(2)
H
Output current < IOL
L
H
L
H
H(3)
L
(1) If the VSD is high, the STATUS pin is in a high impedance.
(2) The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge.
(3) The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
Figure 6.
Switching characteristics
VOUT
tWon
tWoff
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
tr
10%
tf
t
INPUT
td(on)
td(off)
t
13/31
Electrical specifications
Table 13.
VN5160S-E
Electrical transient requirements
ISO 7637-2:
2004(E)
Test levels
Test pulse
III
IV
Number of
pulses or
test times
1
-75V
-100V
5000 pulses
0.5 s
5s
2 ms, 10 Ω
2a
+37V
+50V
5000 pulses
0.2 s
5s
50 µs, 2 Ω
3a
-100V
-150V
1h
90 ms
100 ms
0.1 µs, 50 Ω
3b
+75V
+100V
1h
90 ms
100 ms
0.1 µs, 50 Ω
4
-6V
-7V
1 pulse
100 ms,
0.01Ω
5b(2)
+65V
+87V
1 pulse
400 ms, 2 Ω
Burst cycle/pulse
repetition time
Delays and
Impedance
Test level results(1)
ISO 7637-2:
2004(E)
Test pulse
III
IV
1
C
C
2a
C
C
3a
C
C
3b
C
C
4
C
C
5b(2)
C
C
(1) The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
(2) Valid in case of external load dump clamp: 40V maximum referred to ground.
14/31
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
VN5160S-E
Electrical specifications
Figure 7.
Waveforms
NORMAL OPERATION
INPUT
STAT_DIS
LOAD CURRENT
STATUS
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUT
STAT_DIS
LOAD CURRENT
undefined
STATUS
OPEN LOAD with external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
VOL
VOUT>VOL
STATUS
OPEN LOAD without external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
IOUT<IOL
tPOL
LOAD CURRENT
STATUS
RESISTIVE SHORT TO Vcc, NORMAL LOAD
INPUT
STAT_DIS
IOUT>IOL
LOAD VOLTAGE
VOUT>VOL
VOL
STATUS
tDSTKON
OVERLOAD OPERATION
Tj
TR TTSD
TRS
INPUT
STAT_DIS
ILIMH
ILIML
LOAD CURRENT
STATUS
current power
limitationlimitation
thermal cycling
SHORTED LOAD
NORMAL LOAD
15/31
Electrical specifications
VN5160S-E
2.4
Electrical characteristics curves
Figure 8.
Off state output current
Figure 9.
Input clamp voltage
Vicl (V)
Iloff1 (uA)
8
0.1
7.75
0.09
Off state
Vcc=13V
Vin=Vout=0V
0.08
0.07
Iin=1mA
7.5
7.25
0.06
7
0.05
6.75
0.04
0.03
6.5
0.02
6.25
0.01
6
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
Figure 10. High level input current
50
75
100
125
150
175
100
125
150
175
Tc (°C )
Tc (°C )
Figure 11. Input high level
Iih (uA)
Vih (V)
4
5
4.5
3.5
Vin=2.1V
4
3
3.5
2.5
3
2
2.5
2
1.5
1.5
1
1
0.5
0.5
0
0
-50
-25
0
25
50
75
Tc (°C )
16/31
100
125
150
175
-50
-25
0
25
50
75
Tc (°C )
VN5160S-E
Electrical specifications
Figure 12. Input low level
Figure 13. Input hysteresis voltage
Vil (V)
Vihyst (V)
4
2
3.5
1.75
3
1.5
2.5
1.25
2
1
1.5
0.75
1
0.5
0.5
0.25
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C )
50
75
100
125
150
175
150
175
Tc (°C )
Figure 14. Status low-output voltage
Figure 15. Status leakage current
Ilstat (uA)
Vstat (V)
0.06
0.9
0.8
0.055
Istat=1.6mA
Vstat=5V
0.7
0.05
0.6
0.045
0.5
0.4
0.04
0.3
0.035
0.2
0.03
0.1
0.025
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
Tc (°C )
Tc (°C )
Figure 16. Status clamp voltage
Figure 17. On-state resistance Vs Tcase
Ron (mOhm)
Vscl (V)
250
9
225
8.5
Istat=1mA
8
Iout=1A
Vcc=13V
200
7.5
175
7
150
6.5
125
6
100
5.5
75
5
50
4.5
25
0
4
-50
-25
0
25
50
75
Tc (°C )
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
17/31
Electrical specifications
VN5160S-E
Figure 18. On-state resistance Vs VCC
Figure 19. Openload On-state detection
threshold
dVout/dt(off) (V/ms)
Iol (mA)
1000
100
900
90
800
80
700
Vin=5V
70
Vcc=13V
Ri=13Ohm
600
60
500
50
400
40
300
30
200
20
100
10
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C )
50
75
100
125
150
175
150
175
150
175
Tc (°C )
Figure 20. Openload Off-state voltage
detection threshold
Figure 21. Turn-On voltage slope
dVout/dt(on) (V/ms)
(dVout/dt)on
Vol (V)
1000
5
900
4.5
Vin=0V
4
Vcc=13V
Ri=
RI=6.5Ohm
13Ohm
800
3.5
700
3
600
2.5
500
2
400
1.5
300
1
200
0.5
100
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
Tc (°C )
Tc (°C )
Figure 22. Turn-Off voltage slope
Figure 23. ILIM Vs Tcase
(dVout/dt)off (V/ms)
Ilimh (A)
1000
16
900
14
Vcc=13V
RI=13Ohm
800
Vcc=13V
12
700
10
600
8
500
400
6
300
4
200
2
100
0
0
-50
-25
0
25
50
75
Tc (°C )
18/31
100
125
150
175
-50
-25
0
25
50
75
Tc (°C )
100
125
VN5160S-E
Electrical specifications
Figure 24. Undervoltage shutdown
Figure 25. STAT_DIS clamp voltage
Vusd (V)
Vsdcl (V)
16
8
14
7.5
12
7
10
6.5
8
6
6
5.5
4
5
2
4.5
Isd=1mA
0
4
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C )
50
75
100
125
150
175
Tc (°C )
Figure 26. High-level STAT_DIS voltage
Figure 27. Low-level STAT_DIS voltage
Vsdh (V)
Vsdl (V)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
-50
-25
0
25
50
75
Tc (°C )
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
19/31
Application Information
3
VN5160S-E
Application Information
Figure 28. Application schematic
+5V
+5V
VCC
Rprot
STAT_DIS
Dld
Rprot
INPUT
Rprot
STATUS
µC
OUTPUT
GND
VGND
RGND
DGND
3.1
GND protection network against reverse battery
3.1.1
Solution 1: resistor in the ground line (RGND only)
This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1.
RGND ≤600mV / (IS(on)max)
2.
RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/ RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum On-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
20/31
VN5160S-E
3.1.2
Application Information
Solution 2: a diode (DGND) in the ground line
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈ 600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3
MCU I/Os protection
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-VCCpeak/Ilatchup ≤Rprot ≤(VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤Rprot ≤180kΩ.
Recommended Rprot values is 10kΩ.
3.4
Open load detection in Off state
Off state open load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the
microprocessor.
The external resistor has to be selected according to the following requirements:
1.
no false open load indication when load is connected: in this case we have to avoid
VOUT to be higher than VOlmin; this results in the following condition
VOUT= (VPU/(RL+RPU))RL<VOlmin.
2.
no misdetection when load is disconnected: in this case the Vout has to be higher than
VOLmax; this results in the following condition RPU<(VPU–VOLmax)/IL(off2).
Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in
standby.
21/31
Application Information
VN5160S-E
The values of VOLmin, VOLmax and IL(off2) are available in the Electrical characteristics
section.
Figure 29. Open load detection in Off state
V batt.
VPU
VCC
RPU
INPUT
DRIVER
+
LOGIC
IL(off2)
OUT
+
R
STATUS
VOL
GROUND
22/31
RL
VN5160S-E
3.5
Application Information
Maximum demagnetization energy (VCC = 13.5V)
Figure 30. Maximum turn Off current versus inductance
10
A
B
C
I (A)
1
0,1
0,1
1
L (mH)
10
100
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with RL =0 Ω.In case of repetitive pulses, Tjstart (at beginning of each
demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.
23/31
Package and PCB thermal data
VN5160S-E
4
Package and PCB thermal data
4.1
SO-8 thermal data
Figure 31. SO-8 PC board
Note:
Layout condition of Rth and Zth measurements (PCB: FR4 area= 4.8mm x 4.8mm, PCB
thickness=2mm, Cu thickness= 35µm, Copper areas: from minimum pad lay-out to 2cm2).
Figure 32. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(°C/W)
110
100
90
80
70
60
0
0.5
1
1.5
PCB Cu heatsink area (cm^2)
24/31
2
2.5
VN5160S-E
Package and PCB thermal data
Figure 33. SO-8 Thermal impedance junction ambient single pulse
ZTH (°C/W)
1000
Footprint
100
2 cm2
10
1
0.1
0.0001
0.001
0.01
0.1
1
Time (s)
10
100
1000
Equation 1: pulse calculation formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ)
where δ = tP/T
Figure 34. Thermal fitting model of a single channel HSD in SO-8(a)
(a )The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
25/31
Package and PCB thermal data
Table 14.
26/31
VN5160S-E
Thermal parameter
Area/island (cm2)
Footprint
R1 (°C/W)
1.2
R2 (°C/W)
6
R3 (°C/W)
3.5
R4 (°C/W)
21
R5 (°C/W)
16
R6 (°C/W)
58
C1 (W.s/°C)
0.0008
C2 (W.s/°C)
0.0016
C3 (W.s/°C)
0.0075
C4 (W.s/°C)
0.045
C5 (W.s/°C)
0.35
C6 (W.s/°C)
1.05
2
28
2
VN5160S-E
Package and packing information
5
Package and packing information
5.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
Package mechanical data
Figure 35. SO-8 package dimensions
27/31
Package and packing information
Table 15.
VN5160S-E
SO-8 mechanical data
Millimeter
Dim.
Min.
Typ.
A
a1
1.75
0.1
0.25
a2
1.65
a3
0.65
0.85
b
0.35
0.48
b1
0.19
0.25
C
0.25
0.5
c1
45 (typ.)
D
4.8
5
E
5.8
6.2
e
1.27
e3
3.81
F
3.8
4
L
0.4
1.27
M
0.6
S
L1
28/31
Max.
8 (max.)
0.8
1.2
VN5160S-E
5.3
Package and packing information
Packing information
Figure 36. SO-8 tube shipment (no suffix)
B
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
A
100
2000
532
3.2
6
0.6
All dimensions are in mm.
Figure 37. SO-8 tape and reel shipment (suffix “TR”)
Reel dimensions
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
All dimensions are in mm.
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (+ 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
All dimensions are in mm.
End
Start
Top
cover
tape
No components
Components
No components
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
29/31
Revision history
6
VN5160S-E
Revision history
Table 16.
Document revision history
Date
Revision
Feb-2007
1
Initial release.
May-2007
2
Document rewritten, restructured and put in corporate technical
literature template.
3
Table 4: Absolute maximum ratings: changed EMAX value from
14 to 34 mJ.
Table 13: Electrical transient requirements : updated test level
values III and IV for test pulse 5b and notes.
Added Section 3.5: Maximum demagnetization energy (VCC =
13.5V) .
Figure 34: Thermal fitting model of a single channel HSD in SO8 : added note.
17-Dec-2007
30/31
Changes
VN5160S-E
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2007 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
31/31