VNQ5050K-E QUAD CHANNEL HIGH SIDE DRIVER FOR AUTOMOTIVE APPLICATIONS ADVANCE DATA Table 1. General Features TYPE VNQ5050K-E Figure 1. Package VCC RDS(on) Iout 41V 50mΩ (*) 12A (*) Per channel OUTPUT CURRENT: 12A 3.0 V CMOS COMPATIBLE INPUT ■ STATUS DISABLE ■ ON STATE OPEN LOAD DETECTION ■ OFF STATE OPEN LOAD DETECTION ■ OUTPUT STUCK TO VCC DETECTION ■ OPEN DRAIN STATUS OUTPUT ■ UNDERVOLTAGE SHUT-DOWN ■ ■ PowerSSO-24 OVERVOLTAGE CLAMP ■ THERMAL SHUT DOWN ■ CURRENT AND POWER LIMITATION ■ VERY LOW STAND-BY CURRENT ■ PROTECTION AGAINST LOSS OF GROUND AND LOSS OF VCC ■ VERY LOW ELECTROMAGNETIC SUSCEPTIBILITY ■ OPTIMIZED ELECTROMAGNETIC EMISSION ■ REVERSE BATTERY PROTECTION (**) ■ IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE ■ The device detects open load condition both in on and off state, when STAT_DIS is left open or driven low. Output shorted to VCC is detected in the off state. When STAT_DIS is driven high, the STATUS pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long duration overload, the device limits the dissipated power to safe level up to thermal shut-down intervention. . Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears. DESCRIPTION The VNQ5050K-E is a monolithic device made using STMicroelectronics VIPower technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Table 2. Order Codes Package Tube Tape and Reel PowerSSO-24 VNQ5050K-E VNQ5050KTR-E Note: (**) See application schematic at page 9. Rev. 2 March 2005 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/13 VNQ5050K-E Figure 2. Block Diagram VCC OUTPUT1 GND VCC CLAMP UNDERVOLTAGE INPUT1 CLAMP 1 CONTROL & PROTECTION STATUS2 EQUIVALENT TO CHANNEL1 DRIVER 1 STAT_DIS VCC INPUT2 STATUS1 OUTPUT2 LOGIC INPUT2 OVERTEMP. 1 CURRENT LIMITER 1 VCC INPUT3 CONTROL & PROTECTION STATUS3 EQUIVALENT TO CHANNEL1 STATUS2 OPENLOAD ON 1 OUTPUT3 INPUT3 STATUS3 OPENLOAD OFF 1 INPUT4 VCC INPUT4 CONTROL & PROTECTION STATUS4 EQUIVALENT TO CHANNEL1 PWRLIM 1 OUTPUT4 STATUS4 Table 3. Pin Function Name VCC OUTPUTn Function Battery connection Power output GND Ground connection. Must be reverse battery protected by an external diode/resistor network INPUTn Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state STATUSn Open drain digital diagnostic pin STAT_DIS Active high CMOS compatible pin, to disable the STATUS pin Figure 3. Current and Voltage Conventions IS VCC ISD VFn (*) IOUTn STAT_DIS OUTPUTn VSD VOUTn IINn ISTATn INPUTn STATUSn VINn VSTATn GND IGND (*) VFn = VCC - VOUTn during reverse battery condition 2/13 VCC VNQ5050K-E Figure 4. Configuration Diagram (Top View) & Suggested Connections For Unused and n.c. Pins VCC GND INPUT1 STATUS1 INPUT2 STATUS2 INPUT3 STATUS3 INPUT4 STATUS4 STAT_DIS VCC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT4 OUTPUT4 OUTPUT4 TAB = VCC Connection / Pin Status Floating X To Ground N.C. X X Output X Input X Through 10KΩ resistor Table 4. Absolute Maximum Ratings Symbol VCC Parameter DC Supply Voltage Value Unit 41 V - VCC Reverse DC Supply Voltage - 0.3 V - IGND DC Reverse Ground Pin Current - 200 mA Internally Limited A - 15 A DC Input Current +10/-1 mA ISTAT DC Status Current +10/-1 mA VESD Electrostatic discharge (R=1.5kΩ; C=100pF) 2000 V IOUT - IOUT IIN Tj Tstg DC Output Current Reverse DC Output Current Junction Operating Temperature -40 to 150 °C Storage Temperature - 55 to 150 °C Value 1.7 52 (1) Unit °C/W °C/W Table 5. Thermal Data Symbol Rthj-case Rthj-amb Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Note: 1. When mounted on a standard single-sided FR-4 board with 1 cm2 of Cu (at least 35µm thick) connected to TAB. 3/13 VNQ5050K-E ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C< Tj <150°C, unless otherwise specified) Table 6. Power Section Symbol Parameter VCC Operating supply voltage VUSD Test Conditions Min. Typ. Max. Unit 4.5 13 36 V Undervoltage shut-down 3 4.5 V VUSDhyst Undervoltage shut-down hysteresis 0.5 RON (**) On state resistance IOUT=2A; Tj=25°C 50 mΩ IOUT=2A; Tj=150°C IOUT=2A; VCC=5V; Tj=25°C 100 mΩ 65 mΩ 46 52 V 2 (2) 5 (2) µA 8 14 mA Vclamp Clamp Voltage IS=20 mA IS Supply current Off State; VCC=13V; VIN=VOUT=0V; Tj=25°C 41 On State; VIN=5V; VCC=13V; IOUT=0A IL(off1) (**) Off state output current IL(off2) (**) Off state output current V VIN=VOUT=0V; VCC=13V; Tj=25°C 0 3 µA VIN=VOUT=0V; VCC=13V; Tj=125°C 0 5 µA -75 0 µA VIN=0V; VOUT= 4V Note: (**) Per each channel. Note: 2. PowerMOS leakage included. Table 7. Switching (VCC=13V) Symbol Parameter td(on) Turn-on Delay Time td(off) Test Conditions RL=6.5Ω Min. Typ. 15 Max. Unit µs Turn-off Delay Time RL=6.5Ω 40 µs dVOUT/dt(on) Turn-on Voltage Slope RL=6.5Ω 0.3 V/µs dVOUT/dt(off) Turn-off Voltage Slope RL=6.5Ω 0.35 V/µs WON Switching energy losses at turn-on RL=6.5Ω TBD mJ WOFF Switching energy losses at turn-off RL=6.5Ω TBD mJ 4/13 VNQ5050K-E ELECTRICAL CHARACTERISTICS (continued) Table 8. Status Pin (VSD=0) Symbol VSTAT ILSTAT CSTAT VSCL Parameter Test Conditions Status Low Output Voltage ISTAT= 1.6 mA, VSD=0V Normal Operation or VSD=5V, Status Leakage Current VSTAT= 5V Status Pin Input Normal Operation or VSD=5V, Capacitance VSTAT= 5V ISTAT= 1mA Status Clamp Voltage ISTAT= - 1mA Min Typ 5.5 Max 0.5 Unit V 10 µA 100 pF TBD -0.7 V V Table 9. Protections (see note 3) Symbol Parameter Test Conditions IlimH DC Short circuit current IlimL Short circuit current ing thermal cycling TTSD Shutdown temperature dur- TR Reset temperature TRS Thermal reset of STATUS THYST tSDL VDEMAG VON VCC=13V Min. Typ. Max. Unit 12 18 24 A 24 A 5V<VCC<36V VCC=13V 7 TR<Tj<TTSD 150 200 TRS + 1 TRS + 5 °C 7 Tj>TTSD °C 20 Turn-off output voltage clamp IOUT=2A; VIN=0; L=6mH Output voltage drop IOUT=0.1A (see fig. 6) limitation Tj= -40°C...+150°C VCC-41 °C °C 135 Thermal hysteresis (TTSD-TR) Status Delay in Overload Conditions 175 A VCC-46 VCC-52 25 µs V mV Note: 3. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles Table 10. Openload Detection Symbol IOL tDOL(on) tPOL VOL tDSTKON Parameter Openload ON State Detection Threshold Openload ON State Detection Delay Delay between INPUT falling edge and STATUS rising edge in Openload condition Openload OFF State Voltage Detection Threshold Output Short Circuit to Vcc Detection Delay at Turn Off Test Conditions VIN = 5V , 8V<Vcc<18V Min Typ Max Unit 10 40 70 mA 200 µs IOUT = 0A, VCC=13V IOUT = 0A VIN = 0V, 8V<VCC<16V 200 500 1000 µs 2 3 4 V tPOL µs 180 5/13 VNQ5050K-E Figure 5. OPEN LOAD STATUS TIMING (without external pull-up) IOUT < IOL VIN OPEN LOAD STATUS TIMING (with external pull-up) IOUT < IOL VIN VOUT > VOL VOUT < VOL VSTAT VSTAT tDOL(on) tDOL(on) tPOL OVER TEMP STATUS TIMING OUTPUT STUCK TO Vcc Tj > TTSD IOUT > IOL VIN VOUT > VOL VIN VSTAT VSTAT tDOL(on) tSDL tDSTKON Figure 6. Vcc-Vout Tj=150oC Tj=25oC Tj=-40oC Von Von/Ron(T) 6/13 Iout tSDL VNQ5050K-E ELECTRICAL CHARACTERISTICS (continued) Table 11. Logic Input Symbol Parameter VIL Input Low Level IIL Low Level Input Current VIH Input High Level IIH High Level Input Current VI(hyst) Input Hysteresis Voltage VICL Input Clamp Voltage VSDL STAT_DIS low level voltage ISDL Low level STAT_DIS current VSDH STAT_DIS high level voltage ISDH High level STAT_DIS current VSD(hyst) STAT_DIS hysteresis voltage VSDCL STAT_DIS clamp voltage Test Conditions Min. VIN = 0.9V Typ. Max. Unit 0.9 V µA 1 2.1 V VIN = 2.1V 10 0.25 V 5.5 IIN = 1mA IIN = -1mA TBD -0.7 µA 2.1 V 10 0.25 µA V 5.5 ISD=-1mA V 1 VSD=2.1V ISD=1mA V V 0.9 VSD=0.9V µA TBD -0.7 V V Table 12. Truth Table CONDITIONS Normal Operation Current Limitation Overtemperature Undervoltage Output Voltage > VOL Output Current < IOL INPUTn OUTPUTn STATUSn (VSD=0V) (1) L H L H L H L H L H L H L H L X L L L L H H L H H H H H H L X X L(2) H H(3) L Note: 1. If the VSD is high, the STATUS pin is in a high impedance. 2. The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge. 3. The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge. 7/13 VNQ5050K-E Figure 7. Switching Characteristics VOUT 90% 80% dVOUT/dt(off) dVOUT/dt(on) 10% tr tf t INPUT td(on) td(off) t Table 13. Electrical Transient Requirements ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E 8/13 I II TEST LEVELS III -25 V +25 V -25 V +25 V -4 V +26.5 V -50 V +50 V -50 V +50 V -5 V +46.5 V -75 V +75 V -100 V +75 V -6 V +66.5 V I C C C C C C TEST LEVELS RESULTS II III C C C C C C C C C C E E IV -100 V +100 V -150 V +100 V -7 V +86.5 V Delays and Impedance 2 ms 10 Ω 0.2 ms 10 Ω 0.1 µs 50 Ω 0.1 µs 50 Ω 100 ms, 0.01 Ω 400 ms, 2 Ω IV C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. VNQ5050K-E Figure 8. Application Schematic +5V +5V VCC Rprot STAT_DIS Dld Rprot INPUTn Rprot STATUSn µC OUTPUTn GND RGND VGND DGND Note: Channels 2, 3 and 4 have the same internal circuit as channel 1. GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND ≤ 600mV / (IS(on)max). 2) RGND ≥ (−VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. LOAD DUMP PROTECTION Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. µC I/Os PROTECTION: If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the µC I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os. -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V 5kΩ ≤ Rprot ≤ 65kΩ. Recommended Rprot value is 10kΩ. 9/13 VNQ5050K-E Figure 9. Waveforms NORMAL OPERATION INPUT STAT_DIS LOAD CURRENT STATUS UNDERVOLTAGE VUSDhyst VCC VUSD INPUT STAT_DIS LOAD CURRENT undefined STATUS OPEN LOAD with external pull-up INPUT STAT_DIS VOUT >VOL LOAD VOLTAGE VOL STATUS OPEN LOAD without external pull-up INPUT STAT_DIS LOAD VOLTAGE IOUT<IOL LOAD CURRENT tPOL STATUS RESISTIVE SHORT TO Vcc, NORMAL LOAD INPUT STAT_DIS IOUT>IOL LOAD VOLTAGE VOUT >VOL VOL STATUS tDSTKON OVERLOAD OPERATION Tj TTSD TR TRS INPUT STAT_DIS ILIMH ILIML LOAD CURRENT STATUS current power limitation limitation thermal cycling SHORTED LOAD 10/13 NORMAL LOAD VNQ5050K-E PACKAGE MECHANICAL Table 14. PowerSSO-24™ Mechanical Data Symbol millimeters Min Typ Max A 1.9 2.22 A2 1.9 2.15 a1 0 0.07 b 0.34 c 0.23 0.32 D 10.2 10.4 E 7.4 7.6 0.4 e 0.8 e3 8.8 0.46 G 0.1 G1 0.06 H 10.1 h L 10.5 0.4 0.55 N 0.85 10º X 3.9 4.3 Y 6.1 6.5 Figure 10. PowerSSO-24™ Package Dimensions 11/13 VNQ5050K-E REVISION HISTORY Table 1. Revision History 12/13 Date Revision Description of Changes Oct. 2004 1 - First issue. Mar. 2005 2 - Minor changes VNQ5050K-E Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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