STMICROELECTRONICS VNQ830-E

VNQ830-E
QUAD CHANNEL HIGH SIDE DRIVER
Table 1. General Features
Type
VNQ830-E
Figure 1. Package
RDS(on)
Iout
VCC
60mΩ (*)
6A (*)
36V
(*) Per each channel
CMOS COMPATIBLE INPUTS
OPEN DRAIN STATUS OUTPUTS
■ ON STATE OPEN LOAD DETECTION
■ OFF STATE OPEN LOAD DETECTION
■ SHORTED LOAD PROTECTION
■ UNDERVOLTAGE AND OVERVOLTAGE
SHUTDOWN
■ LOSS OF GROUND PROTECTION
■ VERY LOW STAND-BY CURRENT
■
■
SO-28 (DOUBLE ISLAND)
REVERSE BATTERY PROTECTION (**)
■ IN COMPLIANCE WITH THE 2002/95/EC
EUROPEAN DIRECTIVE
■
DESCRIPTION
The VNQ830-E is a quad HSD formed by
assembling two VND830-E chips in the same SO28 package. The VNQ830-E is a monolithic device
made by using| STMicroelectronics VIPower M0-3
Technology. The VNQ830-E is intended for driving
any type of multiple loads with one side connected
to ground. Active V CC pin voltage clamp protects
the device against low energy spikes (see
ISO7637 transient compatibility table).
Active current limitation combined with thermal
shutdown and automatic restart protects the
device against overload.
The device detects open load condition both in on
and off state. Output shorted to V CC is detected in
the off state. Device automatically turns off in case
of ground pin disconnection.
Table 2. Order Codes
Package
SO-28
Tube
VNQ830-E
Tape and Reel
VNQ830TR-E
Note: (**) See application schematic at page 10
Rev. 2
November 2004
1/21
VNQ830-E
Figure 2. Block Diagram
VCC1,2
Vcc
OVERVOLTAGE
CLAMP
UNDERVOLTAGE
GND1,2
CLAMP 1
OUTPUT1
INPUT1
DRIVER 1
CLAMP 2
STATUS1
CURRENT LIMITER 1
LOGIC
DRIVER 2
OUTPUT2
OVERTEMP. 1
OPENLOAD ON 1
CURRENT LIMITER 2
INPUT2
OPENLOAD OFF 1
OPENLOAD ON 2
STATUS2
OPENLOAD OFF 2
OVERTEMP. 2
VCC3,4
Vcc
CLAMP
OVERVOLTAGE
UNDERVOLTAGE
GND3,4
CLAMP 3
OUTPUT3
INPUT3
DRIVER 3
CLAMP 4
STATUS3
CURRENT LIMITER 3
OVERTEMP. 3
LOGIC
DRIVER 4
OUTPUT4
OPENLOAD ON 3
CURRENT LIMITER 4
INPUT4
OPENLOAD OFF 3
OPENLOAD ON 4
STATUS4
OPENLOAD OFF 4
OVERTEMP. 4
2/21
VNQ830-E
Table 3. Absolute Maximum Ratings
Symbol
VCC
Parameter
Value
Unit
41
V
DC Supply Voltage
- VCC
Reverse DC Supply Voltage
- 0.3
V
- IGND
DC Reverse Ground Pin Current
- 200
mA
Internally Limited
A
-6
A
DC Input Current
+/- 10
mA
DC Status Current
+/- 10
mA
4000
V
4000
V
5000
V
5000
V
(L=2.5mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC;
IL=9A)
140
mJ
Power dissipation (per island) at Tlead=25°C
6.25
W
Internally Limited
°C
- 55 to 150
°C
IOUT
- IOUT
IIN
ISTAT
DC Output Current
Reverse DC Output Current
Electrostatic Discharge (Human
R=1.5KΩ; C=100pF)
VESD
Body
Model:
- INPUT
- STATUS
- OUTPUT
- VCC
Maximum Switching Energy
EMAX
Ptot
Tj
Tstg
Junction Operating Temperature
Storage Temperature
Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins
VCC1,2
1
28
VCC1,2
GND 1,2
OUTPUT1
INPUT1
OUTPUT1
STATUS1
OUTPUT1
STATUS2
OUTPUT2
INPUT2
OUTPUT2
VCC1,2
OUTPUT2
VCC3,4
OUTPUT3
GND 3,4
OUTPUT3
INPUT3
OUTPUT3
STATUS3
OUTPUT4
STATUS4
OUTPUT4
INPUT4
OUTPUT4
VCC3,4
Connection / Pin Status
Floating
X
To Ground
14
N.C.
X
X
15
Output
X
VCC3,4
Input
X
Through 10KΩ resistor
3/21
VNQ830-E
Figure 4. Current and Voltage Conventions
IS3,4
IS1,2
VCC3,4
VCC3,4
VCC1,2
VF1 (*)
VCC1,2
IIN1
ISTAT1
VIN1
IIN2
VSTAT1
ISTAT2
VIN2
IIN3
VSTAT2
ISTAT3
VIN3
VSTAT3
IIN4
VIN4 ISTAT4
VSTAT4
INPUT1
IOUT1
STATUS1
OUTPUT1
VOUT1
IOUT2
INPUT2
OUTPUT2
STATUS2
VOUT2
IOUT3
INPUT3
OUTPUT3
STATUS3
IOUT4
INPUT4
OUTPUT4
STATUS4
GND3,4
VOUT3
VOUT4
GND1,2
IGND3,4
IGND1,2
(*) VFn = VCCn - VOUTn during reverse battery condition
Table 4. Thermal Data (Per island)
Symbol
Parameter
Rthj-lead
Thermal Resistance Junction-lead per chip
Rthj-amb
Thermal Resistance Junction-ambient (one chip ON)
Rthj-amb
Thermal Resistance Junction-ambient (two chips ON)
60 (1)
1
46 ( )
Value
Unit
20
°C/W
44 (2)
°C/W
31 (2)
°C/W
Note: 1. When mounted on a standard single-sided FR-4 board with 0.5cm 2 of Cu (at least 35µm thick) connected to all V CC pins. Horizontal
mounting and no artificial air flow
Note: 2. When mounted on a standard single-sided FR-4 board with 6cm 2 of Cu (at least 35µm thick) connected to all VCC pins. Horizontal
mounting and no artificial air flow
4/21
VNQ830-E
ELECTRICAL CHARACTERISTICS
(8V<VCC<36V; -40°C< Tj <150°C, unless otherwise specified)
(Per each channel)
Table 5. Power Output
Symbol
Parameter
VCC (**)
Min.
Typ.
Max.
Unit
Operating Supply Voltage
5.5
13
36
V
VUSD (**)
Undervoltage Shut-down
3
4
5.5
V
VOV (**)
Overvoltage Shut-down
36
Ron
On State Resistance
Test Conditions
IOUT=2A; Tj=25°C
65
mΩ
IOUT=2A; VCC>8V
130
mΩ
12
40
µA
12
25
µA
5
7
mA
0
50
µA
-75
0
µA
Off State; VCC=13V; VIN=VOUT=0V
IS (**)
Supply Current
V
Off State; VCC=13V; VIN=VOUT=0V;
Tj =25°C
On State; VCC=13V; VIN=5V; IOUT=0A
IL(off1)
Off State Output Current
VIN=VOUT=0V
IL(off2)
Off State Output Current
VIN=0V; VOUT =3.5V
IL(off3)
Off State Output Current
VIN=VOUT=0V; VCC=13V; Tj =125°C
5
µA
IL(off4)
Off State Output Current
VIN=VOUT=0V; VCC=13V; Tj =25°C
3
µA
Note: (**) Per island
Table 6. Protection (Per each channel) (See note 1)
Symbol
Parameter
TTSD
Min.
Typ.
Max.
Unit
Shut-down Temperature
150
175
200
°C
TR
Reset Temperature
135
Thyst
Thermal Hysteresis
7
tSDL
Status Delay in Overload
Conditions
Ilim
Current limitation
Vdemag
Turn-off Output Clamp
Voltage
Test Conditions
°C
15
Tj>TTSD
6
9
5.5V<VCC<36V
IOUT =2A; L=6mH
°C
20
µs
15
A
15
A
VCC-41 VCC-48 VCC-55
V
Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be
used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration
and number of activation cycles
Table 7. VCC - Output Diode (Per each channel)
Symbol
VF
Parameter
Forward on Voltage
Test Conditions
-IOUT=1.2A; Tj=150°C
Min
Typ
Max
0.6
Unit
V
5/21
VNQ830-E
ELECTRICAL CHARACTERISTICS (continued)
Table 8. Status Pin (Per each channel)
Symbol
Parameter
Test Conditions
VSTAT Status Low Output Voltage ISTAT =1.6mA
ILSTAT Status Leakage Current
Normal Operation; VSTAT=5V
Status Pin Input
Normal Operation; VSTAT=5V
CSTAT
Capacitance
ISTAT =1mA
VSCL
Status Clamp Voltage
ISTAT =-1mA
Min
6
Typ
6.8
Max
0.5
10
Unit
V
µA
100
pF
8
V
-0.7
V
Table 9. Switching (Per each channel) (VCC=13V)
Symbol
Parameter
td(on)
Turn-on Delay Time
td(off)
Turn-off Delay Time
dVOUT /dt(on) Turn-on Voltage Slope
dVOUT /dt(off) Turn-off Voltage Slope
Test Conditions
RL=6.5Ω from VIN rising edge to
VOUT =1.3V
RL=6.5Ω from VIN falling edge to
VOUT =11.7V
Min
RL=6.5Ω from VOUT=1.3V to
VOUT =10.4V
RL=6.5Ω from VOUT=11.7V to
VOUT =1.3V
Typ
Max
Unit
30
µs
30
µs
See
relative
V/µs
diagram
See
relative
V/µs
diagram
Table 10. Openload Detection (Per each channel)
Symbol
IOL
tDOL(on)
VOL
tDOL(off)
Parameter
Openload ON State
Detection Threshold
Openload ON State
Detection Delay
Openload OFF State
Voltage Detection
Threshold
Openload Detection Delay
at Turn Off
Test Conditions
VIN=5V
Min
Typ
Max
Unit
50
100
200
mA
200
µs
3.5
V
1000
µs
Max
1.25
Unit
V
µA
V
µA
V
V
IOUT=0A
VIN=0V
1.5
2.5
Table 11. Logic Input (Per each channel)
Symbol
VIL
IIL
VIH
IIH
VI(hyst)
VICL
6/21
Parameter
Test Conditions
Input Low Level
Low Level Input Current VIN=1.25V
Input High Level
High Level Input Current VIN=3.25V
Input Hysteresis Voltage
IIN=1mA
Input Clamp Voltage
IIN=-1mA
Min
Typ
1
3.25
10
0.5
6
6.8
-0.7
8
V
VNQ830-E
Table 12. Truth Table
CONDITIONS
INPUT
OUTPUT
SENSE
Normal Operation
L
H
L
H
H
H
Current Limitation
L
H
H
L
X
X
H
(Tj < TTSD) H
(Tj > TTSD) L
Overtemperature
L
H
L
L
H
L
Undervoltage
L
H
L
L
X
X
Overvoltage
L
H
L
L
H
H
Output Voltage > VOL
L
H
H
H
L
H
Output Current < IOL
L
H
L
H
H
L
Figure 5.
OPEN LOAD STATUS TIMING (with external pull-up)
VOUT > VOL
OVER TEMP STATUS TIMING
IOUT < IOL
Tj > TTSD
VINn
VINn
VSTATn
VSTATn
tSDL
tDOL(off)
tSDL
tDOL(on)
7/21
VNQ830-E
Figure 6. Switching time Waveforms
VOUTn
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
t
VINn
td(on)
td(off)
t
Table 13. Electrical Transient Requirements On V CC Pin
ISO T/R 7637/1
Test Pulse
I
II
TEST LEVELS
III
IV
1
2
3a
3b
4
5
-25 V
+25 V
-25 V
+25 V
-4 V
+26.5 V
-50 V
+50 V
-50 V
+50 V
-5 V
+46.5 V
-75 V
+75 V
-100 V
+75 V
-6 V
+66.5 V
-100 V
+100 V
-150 V
+100 V
-7 V
+86.5 V
ISO T/R 7637/1
Test Pulse
1
2
3a
3b
4
5
CLASS
C
E
8/21
I
C
C
C
C
C
C
TEST LEVELS RESULTS
II
III
C
C
C
C
C
C
C
C
C
C
E
E
Delays and
Impedance
2 ms 10 Ω
0.2 ms 10 Ω
0.1 µs 50 Ω
0.1 µs 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
IV
C
C
C
C
C
E
CONTENTS
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device is not performed as designed after exposure and cannot be
returned to proper operation without replacing the device.
VNQ830-E
Figure 7. Waveforms
NORMAL OPERATION
INPUTn
LOAD VOLTAGEn
STATUSn
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUTn
LOAD VOLTAGEn
STATUS
undefined
OVERVOLTAGE
VCC<VOV
VCC>VOV
VCC
INPUTn
LOAD VOLTAGEn
STATUSn
OPEN LOAD with external pull-up
INPUTn
VOUT>VOL
LOAD VOLTAGEn
VOL
STATUSn
OPEN LOAD without external pull-up
INPUTn
LOAD VOLTAGEn
STATUSn
Tj
TTSD
TR
OVERTEMPERATURE
INPUTn
LOAD CURRENTn
STATUSn
9/21
VNQ830-E
Figure 8. Application Schematic
+5V +5V
+5V
VCC1,2
VCC3,4
Rprot
STATUS1
Rprot
INPUT1
Dld
Rprot
STATUS2
Rprot
INPUT2
Rprot
STATUS3
µC
OUTPUT1
OUTPUT2
OUTPUT3
Rprot
INPUT3
Rprot
STATUS4
OUTPUT4
Rprot
INPUT4
GND1,2
GND3,4
RGND
VGND
+5V +5V
DGND
Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2.
GND PROTECTION
REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This
can be used with any type of load.
The following is an indication on how to dimension the
RGND resistor.
1) RGND ≤ 600mV / 2(IS(on)max).
2) RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can
be found in the absolute maximum rating section of the
device’s datasheet.
Power Dissipation in RGND (when VCC<0: during reverse
battery situations) is:
10/21
PD= (-VCC)2/RGND
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
calculated with formula (1) where IS(on)max becomes the
sum of the maximum on-state currents of the different
devices.
Please note that if the microprocessor ground is not
common with the device ground then the RGND will
produce a shift (IS(on)max * RGND) in the input thresholds
and the status output values. This shift will vary
depending on how many devices are ON in the case of
several high side drivers sharing the same RGND.
If the calculated power dissipation leads to a large
resistor or several devices have to share the same
resistor then the ST suggests to utilize Solution 2.
VNQ830-E
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ.
Recommended Rprot value is 10kΩ.
Solution 2: A diode (DGND) in the ground line.
A resistor (RGND=1kΩ) should be inserted in parallel to
DGND if the device will be driving an inductive load.
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
the ground network will produce a shift (j600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
Series resistor in INPUT and STATUS lines are also
required to prevent that, during battery voltage transient,
the current exceeds the Absolute Maximum Rating.
Safest configuration for unused INPUT and STATUS pin
is to leave them unconnected.
OPEN LOAD DETECTION IN OFF STATE
Off state open load detection requires an external pull-up
resistor (RPU) connected between OUTPUT pin and a
positive supply voltage (VPU) like the +5V line used to
supply the microprocessor.
The external resistor has to be selected according to the
following requirements:
1) no false open load indication when load is connected:
in this case we have to avoid VOUT to be higher than
VOlmin; this results in the following condition
VOUT=(VPU/(RL+RPU))RL<VOlmin.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds VCC max DC rating.
The same applies if the device will be subject to
transients on the VCC line that are greater than the ones
shown in the ISO T/R 7637/1 table.
2) no misdetection when load is disconnected: in this
case the VOUT has to be higher than VOLmax; this
results in the following condition RPU<(VPU–VOLmax)/
IL(off2).
Because Is(OFF) may significantly increase if Vout is
pulled high (up to several mA), the pull-up resistor RPU
should be connected to a supply that is switched OFF
when the module is in standby.
The values of VOLmin, VOLmax and IL(off2) are available in
the Electrical Characteristics section.
.µC I/Os PROTECTION:
If a ground protection network is used and negative
transients are present on the VCC line, the control pins will
be pulled negative. ST suggests to insert a resistor (Rprot)
in line to prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the
leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up
limit of µC I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
Figure 9. Open Load detection in off state
V batt.
VPU
VCC
RPU
INPUT
DRIVER
+
LOGIC
IL(off2)
OUT
+
R
STATUS
VOL
RL
GROUND
11/21
VNQ830-E
Figure 13. High Level Input Current
Figure 10. Off State Output Current
IL(off1) (uA)
Iih (uA)
2.5
5
2.25
4.5
Off state
Vcc=36V
Vin=Vout=0V
2
1.75
Vin=3.25V
4
3.5
1.5
3
1.25
2.5
1
2
0.75
1.5
0.5
1
0.25
0.5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
125
150
175
125
150
175
Tc (°C)
Figure 14. Status Leakage Current
Figure 11. Input Clamp Voltage
Vicl (V)
Ilstat (uA)
8
0.05
7.8
Iin=1mA
7.6
0.04
7.4
Vstat=5V
7.2
0.03
7
6.8
0.02
6.6
6.4
0.01
6.2
6
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
Tc (°C)
Figure 12. Status Low Output Voltage
Figure 15. Status Clamp Voltage
Vstat (V)
Vscl (V)
0.8
8
7.8
0.7
Istat=1mA
Istat=1.6mA
7.6
0.6
7.4
0.5
7.2
0.4
7
6.8
0.3
6.6
0.2
6.4
0.1
6.2
0
6
-50
-25
0
25
50
75
Tc (°C)
12/21
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
100
VNQ830-E
Figure 16. Overvoltage Shutdown
Figure 19. ILIM Vs Tcase
Vov (V)
Ilim (A)
50
20
48
18
46
16
44
14
42
12
40
10
38
8
36
6
34
4
32
2
Vcc=13V
30
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
100
125
150
175
150
175
Figure 20. Turn-off Voltage Slope
dVout/dt(on) (V/ms)
dVout/dt(off) (V/ms)
800
600
550
Vcc=13V
Rl=6.5Ohm
600
75
Tc (°C)
Figure 17. Turn-on Voltage Slope
700
50
Vcc=13V
Ri=6.5Ohm
500
500
450
400
400
300
350
200
300
100
250
0
200
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (ºC)
50
75
Figure 18. On State Resistance Vs Tcase
Ron (mOhm)
160
120
Tc=150°C
110
Iout=2A
Vcc=8V; 13V & 36V
120
125
Figure 21. On State Resistance Vs VCC
Ron (mOhm)
140
100
Tc (°C)
100
90
80
100
70
80
60
Tc=25°C
50
60
40
40
Tc= - 40°C
30
20
20
Iout=2A
10
0
0
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
5
10
15
20
25
30
35
40
Vcc (V)
13/21
VNQ830-E
Figure 22. Input High Level
Figure 25. Input Low Level
Vih (V)
Vil (V)
3.6
2.6
3.4
2.4
3.2
2.2
3
2
2.8
1.8
2.6
1.6
2.4
1.4
2.2
1.2
2
1
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
75
100
125
150
175
Tc (°C)
Figure 23. Openload On State Detection
Threshold
Figure 26. Openload Off State Detection
Threshold
Vol (V)
Iol (mA)
5
150
4.5
140
Vin=0V
Vcc=13V
Vin=5V
130
4
120
3.5
110
3
100
2.5
90
2
80
1.5
70
1
60
0.5
0
50
-50
-25
0
25
50
75
100
125
150
175
Figure 24. Input Hysteresis Voltage
Vhyst (V)
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
-50
-25
0
25
50
75
Tc (°C)
-50
-25
0
25
50
75
Tc (°C)
Tc (°C)
14/21
50
100
125
150
175
100
125
150
175
VNQ830-E
Figure 27. Maximum turn off current versus load inductance
ILM AX (A)
100
10
A
B
C
1
0.1
1
10
100
L(mH)
A = Single Pulse at TJstart=150ºC
B= Repetitive pulse at T Jstart=100ºC
C= Repetitive Pulse at T Jstart=125ºC
Conditions:
VCC=13.5V
Values are generated with R L=0Ω
In case of repetitive pulses, Tjstart (at beginning of
each demagnetization) of every pulse must not
exceed the temperature specified above for
curves B and C.
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
15/21
VNQ830-E
SO-28 Double Island Thermal Data
Figure 28. Double Island PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
Cu thickness=35µm, Copper areas: 0.5cm2, 3cm2, 6cm2).
Table 14. Thermal Calculation According To The Pcb Heatsink Area
Chip 1
ON
OFF
ON
ON
Chip 2
OFF
ON
ON
ON
Tjchip1
RthA x Pdchip1 + Tamb
RthC x Pdchip2 + Tamb
RthB x (Pdchip1 + Pdchip2) + Tamb
(RthA x Pdchip1) + RthC x Pdchip2 + Tamb
RthA = Thermal resistance Junction to Ambient with one
chip ON
RthB = Thermal resistance Junction to Ambient with both
chips ON and Pdchip1=Pdchip2
RthC = Mutual thermal resistance
Tjchip2
Note
RthC x Pdchip1 + Tamb
RthA x Pdchip2 + Tamb
RthB x (Pdchip1 + Pdchip2) + Tamb
Pdchip1=Pdchip2
(RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1≠Pdchip2
Figure 29. Rthj-amb Vs. PCB Copper Area In
Open Box Free Air Condition
RTHj_am b
(°C/W)
70
RthA
60
RthB
50
40
RthC
30
20
10
0
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1
2
3
4
5
PCB Cu heatsink area (cm ^2)/island
6
7
VNQ830-E
Figure 30. SO-28 Thermal Impedance Junction Ambient Single Pulse
One channel ON
ZT H (°C/W)
1000
Two channels ON
on same chip
100
Footprint
6 cm2
10
1
0.1
0.0001
0.001
0.01
0.1
1
Time (s)
Figure 31. Thermal fitting model of a double
channel HSD in SO-28
Tj_1
C2
C3
C4
C5
C6
R1
R2
R3
R4
R5
R6
C13
R13
C14
R14
Pd2
R17
Tj_3
R18
C7
C8
C9
R7
R8
R9
C10
C11
C12
Pd3
Tj_4
1000
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
δ = tp ⁄ T
Table 15. Thermal Parameter
Pd1
Tj_2
100
Pulse calculation formula
where
C1
10
C15
R15
R10
C16
R16
Pd4
T_amb
R11
R12
Area/island (cm2)
R1=R7=R13=R15 (°C/W)
R2=R8=R14=R16 (°C/W)
R3=R9 (°C/W)
R4=R10 (°C/W)
R5=R11 (°C/W)
R6=R12 (°C/W)
C1=C7=C13=C15 (W.s/°C)
C2=C8=C14=C16 (W.s/°C)
C3=C9 (W.s/°C)
C4=C10 (W.s/°C)
C5=C11 (W.s/°C)
C6=C12 (W.s/°C)
R17=R18 (°C/W)
0.5
0.05
0.3
3.4
11
15
30
0.001
5.00E-03
1.00E-02
0.2
1.5
5
150
6
13
8
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VNQ830-E
PACKAGE MECHANICAL
Table 16. SO-28 Mechanical Data
Symbol
A
a1
b
b1
C
c1
D
E
e
e3
F
L
S
millimeters
Min
Max
2.65
0.30
0.49
0.32
0.10
0.35
0.23
0.50
45° (typ.)
17.7
10.00
18.1
10.65
1.27
16.51
7.40
0.40
Figure 32. SO-28 Package Dimensions
18/21
Typ
7.60
1.27
8° (max.)
VNQ830-E
Figure 33. SO-28 Tube Shipment (No Suffix)
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
B
28
700
532
3.5
13.8
0.6
All dimensions are in mm.
A
Figure 34. Tape And Reel Shipment (Suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
16.4
60
22.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
16
4
12
1.5
1.5
7.5
6.5
2
End
All dimensions are in mm.
Start
Top
No components
Components
No components
cover
tape
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
19/21
VNQ830-E
REVISION HISTORY
Date
Nov. 2004
20/21
Revision
Description of Changes
2
- RDS(on) value correction: 60mΩ instead of 65mΩ
VNQ830-E
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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