TI ISO1176DW

ISO1176
www.ti.com.................................................................................................................................................. SLLS897C – MARCH 2008 – REVISED OCTOBER 2008
ISOLATED RS-485 PROFIBUS TRANSCEIVER
•
•
•
FEATURES
1
•
•
•
•
•
•
4000-VPEAK Isolation
Bus-Pin ESD Protection
– 16 kV HBM Between Bus Pins and GND2
– 6 kV HBM Between Bus Pins and GND1
Meets or Exceeds the Requirements of
EN 50170 and TIA/EIA-485
Signaling Rates up to 40 Mbps
Differential Output Exceeds 2.1 V (54 Ω Load)
Low Bus Capacitance – 10 pF (MAX)
50 kV/µs Typical Transient Immunity
Failsafe Receiver for Bus Open, Short, Idle
3.3-V Inputs are 5-V Tolerant
APPLICATIONS
•
•
•
•
•
•
Profibus
Factory Automation
Networked Sensors
Motor/Motion Control
HVA and Building Automation Networks
Networked Security Stations
DESCRIPTION
The ISO1176 is an isolated differential line transceiver designed for use in PROFIBUS applications. The device
is ideal for long transmission lines since the ground loop is broken to provide for operation with a much larger
common mode voltage range. The symmetrical isolation barrier of each device is tested to provide 2500 Vrms of
isolation between the line transceiver and the logic level interface.
The galvanically isolated differential bus transceiver is an integrated circuit designed for bi-directional data
communication on multipoint bus-transmission lines. The transceiver combines a galvanically isolated differential
line driver and differential input line receiver. The driver has an active-high enable with isolated enable-state
output on the ISODE pin (pin 10) to facilitate direction control. The driver differential outputs and the receiver
differential inputs connect internally to form a differential input/output (I/O) bus port that is designed to offer
minimum loading to the bus allowing up to 160 nodes.
The PV pin (pin 7) is provided as a full-chip enable option. All device outputs become high impedance when a
logic low is applied to the PV pin. For more information, see the function tables in the device information section.
Any cabled I/O can be subjected to electrical noise transients from various sources. These noise transients can
cause damage to the transceiver and/or near-by sensitive circuitry if they are of sufficient magnitude and
duration. The ISO1176 can significantly reduce the risk of data corruption and damage to expensive control
circuits.
The device is characterized for operation over the ambient temperature range of –40°C to 85°C.
DW PACKAGE
(TOP VIEW)
1
16
VCC2
GND 1
2
15
ISO1176
function diagram
R
3
14
GND 2
NC
RE
4
13
B
DE
D
5
12
6
11
A
NC
PV
PV
7
10
ISODE
DE
GND 1
8
9
GND 2
R
RE
D
3
4
6
7
5
GALVANIC ISOLATION
VCC1
13
12
10
B
A
ISODE
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
ISO1176
SLLS897C – MARCH 2008 – REVISED OCTOBER 2008.................................................................................................................................................. www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted (1)
VALUE
UNIT
–0.5 to 7
V
VCC1,
VCC2
Supply voltage (2)
VO
Voltage at any bus I/O terminal
–9 to 14
V
VI
Voltage input at any D, DE or RE terminal
–0.5 to 7
V
IO
Receiver output current
±10
mA
Human Body
Model
ESD
TJ
(1)
(2)
Electrostatic
discharge
JEDEC Standard 22, Test Method A114-C.01
Bus pins to GND1
±6
Bus pins to GND2
±16
All pins
±4
kV
Charged Device
Model
JEDEC Standard 22, Test Method C101
All pins
±1
Machine model
ANSI/ESDS5.2-1996
All pins
±200
V
170
°C
Maximum junction temperature
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
All voltage values except differential I/O bus voltages are with respect to the referenced network ground terminal and are peak voltage
values.
RECOMMENDED OPERATING CONDITIONS
MIN
VCC
VCM
TYP
MAX
Logic side supply voltage, VCC1 (with respect to GND1)
3.15
5.5
Bus side supply voltage, VCC2 (with respect to GND2)
4.75
5.25
Voltage at either bus I/O terminal
VIH
High-level input voltage
VIL
Low-level input voltage
VID
Differential input voltage
IO
Output current
TJ
Operating junction temperature
A, B
PV, RE
D, DE
–7
12
2
VCC1
UNIT
V
V
V
0.7 VCC1
PV, RE
0
0.8
D, DE
V
0.3 VCC1
A with respect to B
–12
12
Driver
–70
70
–8
8
–40
150
Receiver
V
mA
°C
SUPPLY CURRENT
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
3V
ICC1
Logic side RMS supply current
5.5 V
ICC2
2
Bus side RMS supply current
5.25 V
TYP
MAX
DE at 0 V
MIN
4
6
DE at VCC1, 2 Mbps
5
DE at VCC1, 25 Mbps
6
DE at 0 V
7
DE at VCC1, 2 Mbps
8
DE at VCC1, 25 Mbps
11
DE at 0 V
15
DE at VCC1, 2 Mbps, 54 Ω load
70
DE at VCC1, 25 Mbps, 54 Ω load
75
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UNIT
mA
10
mA
18
mA
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ISODE-PIN ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
MIN
TYP
IOH = –8 mA
TEST CONDITIONS
VCC2 – 0.8
4.6
IOH = –20 µA
VCC2 – 0.1
5
MAX
UNIT
V
IOL = 8 mA
0.2
0.4
IOL = 20 µA
0
0.1
V
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VOD
Open-circuit differential output voltage
|VA – VB|, Figure 1
1.5
|VOD(SS)|
Steady-state differential output voltage
magnitude
See Figure 2 and Figure 6
2.1
Common-mode loading with Vtest from –7
V to 12 V, See Figure 3
2.1
|ΔVOD(SS)|
Change in steady-state differential output
voltage between logic states
VOC(SS)
Steady-state common-mode output voltage
ΔVOC(SS)
Change in steady-state common-mode output
RL = 54 Ω, See Figure 4 and Figure 5
voltage
VOC(PP)
Peak-to-peak common-mode output voltage
VOD(RING)
Differential output voltage over and under
shoot
See Figure 6 and Figure 10
VI(HYS)
Input voltage hysteresis
See Figure 7
RL = 54 Ω, See Figure 4 andFigure 5
IO(OFF)
Output current with power off
VCC ≤ 2.5 V
IOZ
High impedance state output current
DE at 0 V
IOS(P)
Peak short-circuit output current
COD
Differential output capacitance
CMTI
Common-mode transient immunity
(1)
UNIT
VCC2
V
V
–0.2
0.2
2
3
–0.2
0.2
10%
150
D, DE at 0 V or VCC1
Input current
Steady-state short-circuit output current
MAX
V
V
0.5
II
IOS(SS)
TYP
10
120
µA
See Receiver input
current
VOS = –7 V to 12 V
DE at VCC, See
Figure 8 and
Figure 9
mV
–10
PV (1) at 0 V or VCC1
VOD(pp)
–250
VOS = 12 V, D at
GND1
VOS = –7 V, D at
VCC1
250
135
mA
–135
See Receiver CIN
See Figure 20
25
kV/µs
The PV pin has a 50 kΩ pull-up resistor and leakage current depends on supply voltage.
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DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tpLH, tpHL
Propagation delay time
tsk(p)
Pulse skew (|tpHL – tpLH|)
tpLH, tpHL
Propagation delay time
tsk(p)
Pulse skew (|tpHL – tpLH|)
tr
Differential output signal rise time
tf
Differential output signal fall time
tpDE
DE to ISODE prop delay
See Figure 14
tt(MLH), tt(MHL)
Output transition skew
See Figure 11
tp(AZH), tp(BZH)
tp(AZL), tp(BZL)
Propagation delay time, high-impedance-to-active output
tp(AHZ), tp(BHZ)
tp(ALZ), tp(BLZ)
Propagation delay time, active-to- high-impedance output
|tp(AZL) – tp(BZH)|
|tp(AZH) – tp(BZL)|
Enable skew time
t(CFB)
Time from application of short-circuit to current foldback
See Figure 9
t(TSD)
Time from application of short-circuit to thermal shutdown
TA = 25°C, See Figure 9
MIN
VCC1 at 5 V
VCC2 at 5 V
VCC1 at 3.3 V
VCC2 at 5 V
TYP MAX
2
UNIT
35
ns
5
ns
40
ns
2
5
ns
2
3
7.5
ns
2
3
7.5
ns
30
ns
1
ns
80
ns
80
ns
1.5
ns
See Figure 10
CL = 50 pF,
RE at 0 V,
See Figure 12 and
Figure 13
0.55
µs
0.5
µs
100
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIT(+)
Positive-going differential input voltage threshold
VIT(–)
Negative-going differential input voltage threshold
Vhys
Hysteresis voltage (VIT+ – VIT-)
VOH
TEST CONDITIONS
SeeFigure 15
High-level output voltage
VCC1 at 3.3 V and VCC2 at
5V
MIN
IO = –8 mA
IO = 8 mA
–200
TYP
MAX
UNIT
–80
–10
mV
–120
mV
40
mV
VID = 200 mV,
See Figure 15
IOH = –8 mA
VCC1 –0.4
3
IOH = –20 µA
VCC1 –0.1
3.3
V
VOL
Low-level output voltage
VID = –200 mV,
See Figure 15
IOL = 8 mA
0.2
0.4
IOL = 20 µA
0
0.1
VOH
High-level output voltage
VID = 200 mV,
See Figure 15
IOH = –8 mA
VCC1 –0.8
4.6
IOH = –20 µA
VCC1 –0.1
5
Low-level output voltage
VID = –200 mV,
See Figure 15
IOL = 8 mA
IA(OFF)
IB(OFF)
Bus pin input current
VI = –7 V or 12 V,
Other input = 0 V
II
Receiver enable input current
IOZ
High-impedance state output current
RID
VCC1 at 5 V and VCC2 at 5
V
VOL
IA, IB
IOL = –20 µA
V
V
0.2
0.4
0
0.1
V
VCC = 4.75 V or 5.25 V
–160
200
µA
RE = 0 V
–50
50
µA
RE = VCC1
–1
1
Differential input resistance
A, B
48
CID
Differential input capacitance
Test input signal is a 1.5 MHz sine wave with
1 Vpp amplitude , CD is measured across
A and B
7
CMR
Common mode rejection
See Figure 19
4
4
VCC2 = 0 V
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µA
kΩ
10
pF
V
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RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tpLH, tpHL
Propagation delay time
tsk(p)
Pulse skew (|tpHL – tpLH|)
tpLH, tpHL
Propagation delay time
tsk(p)
Pulse skew (|tpHL – tpLH|)
tr
MIN
TYP MAX
50
VCC1 at 5 V, VCC2 at 5 V
2
VCC1 at 3.3 V, VCC2 at 5 V
5
55
See Figure 16
2
5
Output signal rise time
2
4
tf
Output signal fall time
2
4
tpZH
Propagation delay time, high-impedance-to-high-level output
25
Propagation delay time, high-level-to-high-impedance output
DE at VCC1,
See Figure 17
13
tpHZ
13
25
tpZL
Propagation delay time, high-impedance-to-low-level output
25
Propagation delay time, low-level-to-high-impedance output
DE at VCC,
See Figure 18
13
tpLZ
13
25
UNIT
ns
ns
ns
ns
ns
PARAMETER MEASUREMENT INFORMATION
VCC1
IOA
DE
A
0 or
VCC1
I
D
VOD
B
GND 1
VI
IOB
GND 2
VOA
VOB
GND 1
GND 2
Figure 1. Open Circuit Voltage Test Circuit
VCC1
IOA
DE
A
0 or
VCC1
II
D
VOD
B
GND 1
GND 2
54 W
IOB
VI
VOB
GND 1
VOA
GND 2
Figure 2. VOD Test Circuit
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC2
DE
375 W
A
D
0 or 3 V
+
VOD
-
B
60 W
-7 V
to
12 V
375 W
GND 2
Figure 3. Driver VOD with Common-mode Loading Test Circuit
VCC1
RL
2
IOA
DE
A
II
0 or
VCC1
D
VOD
B
GND 1
RL
2
IOB
GND 2
VI
VOB
VOA
VOC
GND 2
GND 1
Figure 4. Driver VOD and VOC Without Common-Mode Loading Test Circuit
VCC1
RL
2
IOA
DE
A
II
Input
Generator PRR = 500 kHz,
50% duty cycle, tr < 6 ns,
tt < 6 ns, ZO = 50 Ω
D
GND 1
VI
VOD
B
GND 2
VOB
GND 1
RL
2
IOB
VOA
A
VA
B
VB
V
OC
VOC(p-p)
VOC
VOC(SS )
GND 2
Figure 5. Steady-State Output Voltage Test Circuit and Voltage Waveforms
6
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PARAMETER MEASUREMENT INFORMATION (continued)
VDO(RING)
VDO(SS)
VOD(pp)
0 V Differential
Figure 6. VOD(RING) Waveform and Definitions
VCC1
IOA
DE
A
II
0 or
VCC1
D
GND 1
VI
VOD
B
GND 2
IOB
VOA
VOB
GND 1
54 W
GND 2
Figure 7. Input Voltage Hysteresis Test Circuit
DE
250
I OS
0.5 W
D
B
I OS
Vos
GND 1
GND 2
GND 2
Output Current - mA
A
120
60
t(CFB)
time
t(TSD)
Figure 8. Driver Short-Circuit Test Circuit and Waveforms (Short Circuit applied at Time t=0)
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PARAMETER MEASUREMENT INFORMATION (continued)
DE
I OS
B
I OS
250
Output Current - mA
A
D
Vos
GND 1
GND 2
GND 2
120
60
t(CFB)
time
t(TSD)
Figure 9. IOS(SS) Steady State Short Circuit Output Current Test Circuit
3V
DE
VCC1
A
VOD
D
Input
Generator
RL = 54 W
±1%
B
VI
CL = 50 pF
± 20%
1.5 V
VI
1.5 V
tPHL
tPLH
50 W
CL Includes Fixture and
Instrumentation Capacitance
GND 1
Generator PRR = 500 kHz, 50 % Duty
Cycle, tr <6 ns, ZO = 50 W
90%
0V
0V
VOD
VOD (H)
90%
10%
tf
tr
10%
VOD (L)
Figure 10. Driver Switching Test Circuit and Waveforms
DE
VCC1
50 %
A
D
Input
Generator
VI
RL = 54 W CL = 50 pF
±20%
±1%
B
50 %
A
VO B
tt(MHL)
tt(MLH)
50 W
GND 1
GND 2 VOA VOB
Generator PRR = 500 kHz, 50% Duty
Cycle, tr <6 ns, tf <6 ns, ZO = 50 W
50 %
50 %
CL Includes Fixture and
Instrumentation Capacitance
Figure 11. Driver Output Transition Skew Test Circuit and Waveforms
RL = 110 W
VCC2
A
B
A
RL = 110 W
DE
0V
50 W
t(ALZ)
t(AZL)
VIN = 0 V D
Signal
Generator
1.5 V
DE
CL = 50 pF
VOA VOB
CL = 50 pF
50 %
t(BZH)
B
VOL +0.5 V
t(BHZ)
50 %
VO -0.5 V
GND 1
GND 2
Generator PRR = 500 kHz, 50% Duty
Cycle, tr <6 ns, tf <6 ns, ZO = 50 W
Figure 12. Driver Enable/Disable Test, D at Logic Low Test Circuit and Waveforms
8
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PARAMETER MEASUREMENT INFORMATION (continued)
RL = 110 W
0V
A
CL = 50 pF
1.5 V
DE
D
VIN = 3 V
t(AZH)
B
RL = 110 W
DE
Signal
Generator
t(AHZ)
A
50 W
t(BZL)
VOA VOB
GND 1
Generator PRR = 500 kHz, 50% Duty
Cycle, tr <6 ns, tf <6 ns, ZO = 50 W
VOH -0.5 V
50%
VCC2
t(BLZ)
B
CL = 50 pF
50%
VOL +0.5 V
GND 2
Figure 13. Driver Enable/Disable Test, D at Logic High Test Circuit and Waveforms
VCC2
VCC1
VIN = VCC1
tPDE_HL
tPDE_LH
CL = 15 pF
± 20%
DE
Signal
Generator
50%
50%
DE
ISODE
D
50%
ISODE
50 W
50%
GND 2
GND 1
Generator PRR = 500 kHz, 50% Duty
Cycle, tr <6 ns, tf <6 ns, ZO = 50 W
Figure 14. DE to ISODE Prop Delay Test Circuit and Waveforms
IO
V ID
VO
Figure 15. Receiver DC Parameter Definitions
Signal
Generator
50 W
Input B
A
PRR = 100 kHz, 50% Duty Cycle,
VID
tr <6 ns, tf <6 ns, ZO = 50 W
B
Signal
Generator
50 W
R
IO
CL= 15 pF
(Includes Probe and
Jig Capacitance)
1.5 V
50%
Input A
0V
tpLH
VO
tpHL
VOH
90%
1.5 V
Output
10%
tr
tf
VOL
Figure 16. Receiver Switching Test Circuit and Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC
D
VCC
DE
A
3V
RE
54 W
B
1.5 V
1.5 V
0V
t pZH
1 kW
R
t pHZ
CL = 15 pF
1.5 V
(Includes Probe and
Jig Capacitance)
RE
Signal
Generator
VO
VOH -0.5 V
0V
R
GND
50 W
PRR = 100 kHz, 50% duty cycle,
tr <6 ns, tf <6 ns, ZO = 50 W
Figure 17. Receiver Enable Test Circuit and Waveforms, Data Output High
0V
VCC
D
DE
A
3V
RE
0V
R
t pZL
1 kW
VCC1
tpLZ
VOH
R
CL = 15 pF
1.5 V
VOL +0.5 V
VOL
(Includes Probe and
Jig Capacitance)
RE
Signal
Generator
1.5 V
1.5 V
54 W
B
50 W
PRR = 100 kHz, 50% duty cycle,
tr <6 ns, tf <6 ns, ZO = 50 W
Figure 18. Receiver Enable Test Circuit and Waveforms, Data Output Low
VINPUT
f = 1 to 50 MHz
Ampl. = ± 5 V
A
100 nF
50 W
470 nF
R
B
RE
50 W
2.2 kW
DE
V
R
Scope
2.2 kW
D
VOFFSET
= -2 V to 7 V
Scope
GND
VCC
100 nF
Figure 19. Common-Mode Rejection Test Circuit
10
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PARAMETER MEASUREMENT INFORMATION (continued)
C = 0.1 mF VCC1
±1%
2V
VCC2
A
DE
GND1
S1
D
C = 0.1 mF ± 1%
54 W
B
VOH or VOL
0.8 V
Success / Fail Criterion:
Stable VOH or VOL Outputs
R
VOH or VOL
1 kW
RE
GND 1
GND 2
CL = 15 pF
(Includes Probe and
Jig Capacitance)
VTEST
Figure 20. Common-Mode Transient Immunity Test Circuit
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TYPICAL CHARACTERISTICS
DIFFERENTIAL OUTPUT VOLTAGE
vs
LOAD CURRENT
RMS SUPPLY CURRENT
vs
SIGNALING RATE
100
5
VCC = 5 V
VCC = 5.25 V
4
100 Ω
50 Ω
VCC = 4.75 V
2.5
2
1.5
1
TA = 25 C
0
50
40
30
5 V VCC1
20
80
Figure 22.
DRIVER OUTPUT TRANSITION SKEW
vs
FREE-AIR TEMPERATURE
DRIVER RISE, FALL TIME
vs
FREE-AIR TEMPERATURE
4
RL = 54 Ω,
CL = 50 pF
3.75
VCC = 4.75 V
0.25
VCC = 5 V
0.2
0.15
VCC = 5.25 V
0.1
0
−40
5
10
15
Signalling Rate - Mbps
Figure 21.
0.05
20
RL = 54 Ω,
CL = 50 pF
VCC = 4.75 V
3.5
3.25
VCC = 5 V
3
VCC = 5.25 V
2.75
2.5
2.25
−15
10
35
60
TA − Free-Air Temperature − °C
85
2
−40
Figure 23.
12
3.3 V VCC1
ICC1
0
Driver Rise, Fall Time − ns
Driver Output Transition Skew − ns
60
0
20
40
60
IL − Load Current − mA
0.35
0.3
70
10
0.5
0
ICC2
80
3.5
3
No Load
TA = 25°C
90
ICC - Supply Current - mA
VOD − Differential Output Voltage − V
4.5
−15
10
35
60
TA − Free-Air Temperature − °C
85
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
DRIVER ENABLE SKEW
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0.7
-99
VCC = 4.75 V
15 pF Load
TA = 25°C
-89
0.6
IO - Output Current - mA
Driver Enable Skew − ns
-79
0.5
0.4
VCC = 5.25 V
VCC = 5 V
0.3
0.2
-69
-59
-49
-39
-29
-19
0.1
0
−40
RL = 110 Ω,
CL = 50 pF
-9
−15
10
35
60
TA − Free-Air Temperature − °C
1
0
85
1
2
3
4
5
VO - Output Voltage - V
Figure 25.
Figure 26.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
110
15 pF Load
TA = 25°C
100
IO - Output Current - mA
90
80
70
60
50
40
30
20
10
0
0
1
2
3
VO - Output Voltage - V
4
5
Figure 27.
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ISO1176
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DEVICE INFORMATION
DW PACKAGE
(TOP VIEW)
VCC1
1
16
VCC2
GND 1
2
15
R
3
14
GND 2
NC
RE
4
13
B
DE
D
5
12
6
11
A
NC
PV
7
10
ISODE
GND 1
8
9
GND 2
PACKAGE PIN FUNCTION DESCRIPTION
NAME
14
PIN NO.
FUNCTION
Vcc1
1
GND1
2, 8
logic side power supply
R
3
receiver output
RE
4
receiver logic-low enable
DE
5
driver logic-high enable input
D
6
driver input
PV
7
ISO1176 chip enable, logic high applied immediately after power-up for device operation.
A logic low 3-states all outputs.
logic side ground, internally connected
GND2
9, 15
ISODE
10
bus side ground, internally connected
nc
11, 14
A
12
non-inverting bus output
B
13
inverting bus output
Vcc2
16
bus side power supply
bus-side driver enable output
not connected internally, may be left floating
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DRIVER FUNCTION TABLE
VCC1
VCC2
POWER
VALID
(PV)
(ISO1176)
INPUT
(D)
ENABLE
INPUT
(DE)
ENABLE
OUTPUT
(ISODE)
OUTPUTS
A
B
PU
PU
H or open
H
H
H
H
L
PU
PU
H or open
L
H
H
L
H
PU
PU
H or open
X
L
L
Z
Z
PU
PU
H or open
X
open
L
Z
Z
PU
PU
H or open
open
H
H
H
L
PD
PU
X
X
X
L
Z
Z
PU
PD
X
X
X
L
Z
Z
PD
PD
X
X
X
L
Z
Z
X
X
L
X
X
L
Z
Z
H = high level, L= low level, X = don’t care, Z = high impedance (off), ? = indeterminate
RECEIVER FUNCTION TABLE
VCC1
VCC2
POWER VALID
(PV) (ISO1176)
DIFFERENTIAL INPUT
VID = (VA – VB)
ENABLE
(RE)
OUTPUT
)
PU
PU
PU
PU
H or open
–0.01 V ≤ VID
L
H
H or open
–0.2 V < VID < –0.01 V
L
PU
?
PU
H or open
VID ≤ –0.2 V
L
L
PU
PU
H or open
X
H
Z
PU
PU
H or open
X
open
Z
PU
PU
H or open
Open circuit
L
H
PU
PU
H or open
Short Circuit
L
H
PU
PU
H or open
Idle (terminated) bus
L
H
PD
PU
X
X
X
Z
PU
PD
H or open
X
L
H
PD
PD
X
X
X
Z
X
X
L
X
X
Z
H = high level, L= low level, X = don’t care, Z = high impedance (off), ? = indeterminate
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EQUIVALENT CIRCUIT SCHEMATICS
D, RE Input
VCC1
DE Input
VCC1
VCC1
VCC1
VCC1
1 MW
500 W
500 W
1 MW
ISODE Output
PV Input
VCC2
VCC1
VCC1
VCC1
50 kW
5.5 W
500 W
11 W
3.3 V R Output
5 V R Output
VCC1
16
VCC1
4W
5.5 W
6.4 W
11 W
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B Input
A Input
VCC2
16 V
VCC2
16 V
18 kW
90 kW
18 kW
90 kW
Input
Input
16 V
16 V 18 kW
18 kW
A and B Outputs
VCC2
16 V
Output
16 V
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A Failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
IS
Safety input, output, or supply current
DW-16
TS
Maximum case temperature
DW-16
MIN
θJA = 212°C/W, VI = 5.5 V, TJ = 170°C,
TA = 25°C
TYP
MAX
UNIT
128
mA
150
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity
Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum
input voltage times the current. The junction temperature is then the ambient temperature plus the power times
the junction-to-air thermal resistance.
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THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Low-K thermal resistance (1)
168
High-K board(1)
96.1
MAX
UNIT
θJA
Junction-to-air
θJB
Junction-to-board thermal resistance
61
°C/W
θJC
Junction-to-case thermal resistance
48
°C/W
PD
Device power dissipation
(1)
Vcc1 = Vcc2 = 5.25 V, TJ = 150°C, CL = 15 pF,
Input a 20 MHz 50% duty cycle square wave
°C/W
220
mW
Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
150
VCC1,2 at 5.5 V
Safety Limiting Current - mA
125
100
75
50
25
0
0
50
100
150
TC - Case Temperature - °C
200
Figure 28. DW-16 θJC Thermal Derating Curve per IEC 60747-5-2
PACKAGE CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
L(I01)
Minimum air gap (Clearance)
Shortest terminal to terminal distance
through air
8.34
mm
L(I02)
Minimum external tracking (Creepage) (1)
Shortest terminal to terminal distance
across the package surface
8.1
mm
CTI
Tracking resistance (Comparative Tracking
Index)
DIN IEC 60112 / VDE 0303 Part 1
≥175
V
Minimum Internal Gap (Internal Clearance)
Distance through the insulation
0.008
mm
Isolation resistance
Input to output, VIO = 500 V, all pins on
each side of the barrier tied together
creating a two-terminal device
RIO
>1012
Ω
CIO
Barrier capacitance Input to output
VI = 0.4 sin (4E6πt)
2
pF
CI
Input capacitance to ground
VI = 0.4 sin (4E6πt)
2
pF
(1)
18
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation
Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
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REGULATORY INFORMATION
VDE
UL
Certified according to IEC 60747-5-2
Recognized under 1577 Component Recognition Program (1)
File Number: 40014131
File Number: E181974
(1)
Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577.
IEC 60554-1 RATINGS TABLE
PARAMETER
TEST CONDITIONS
SPECIFICATION
Basic isolation group
Material group
IIIa
Installation classification
Rated mains voltage < 150 VRMS
I-IV
Rated mains voltage < 300 VRMS
I-III
Rated mains voltage < 400 VRMS
I-II
IEC 60747-5-2 INSULATION CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIORM
Maximum working insulation voltage
VPR
Input to output test voltage
VIOTM
Transient overvoltage
RS
Insulation resistance
TEST CONDITIONS
SPECIFICATION
UNIT
560
V
Method b1, VPR = VIORM × 1.875, 100% Production
test with t = 1 s, Partial discharge <5 pC
1050
V
t = 60 s
4000
V
9
Ω
VIO = 500 V at TS
Pollution degree
>10
2
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APPLICATION INFORMATION
Transient Voltages
Isolating of a circuit insulates it from other circuits and earth, so that noise voltage develops across the insulation
rather than circuit components. The most common noise threat to data-line circuits is voltage surges or electrical
fast transients that occur after installation. The transient ratings of the ISO1176 standard are sufficient for all but
the most severe installations. However, some equipment manufacturers use ESD generators to test equipment
transient susceptibility. This practice can easily exceed insulation ratings. ESD generators simulate static
discharges that may occur during device or equipment handling with low-energy but very high-voltage transients.
Figure 29 models the ISO1176 bus IO connected to a noise generator. CIN and RIN is the device, and any other
stray or added capacitance or resistance across the A or B pin to GND2. CISO and RISO is the capacitance and
resistance between GND1 and GND2 of the ISO1176, plus those of any other insulation (transformer, etc.). Stray
inductance is assumed to be negligible.
From this model, the voltage at the isolated bus return
is
ZISO
v GND2 = v N
ZISO + ZIN
(1)
and will always be less than 16 V from VN. If the
ISO1176 is tested as a stand-alone device,
• RIN= 6 x 104 Ω,
• CIN= 16 x 10–12 F,
• RISO= 109 Ω and
• CISO= 10–12 F.
A or B
CIN
RIN
VN
Bus Return (GND2)
CISO
Notice from Figure 29 that the resistor ratio determines
the voltage ratio at low frequencies, and that the
inverse capacitance ratio determines the voltage ration
at high frequencies. In the stand-alone case and for
low frequencies,
16V
RISO
System Ground (GND1)
9
v GND2
RISO
10
=
= 9
vN
RISO + RIN 10 + 6 x10 4
(2)
, or essentially all of the noise appears across the
barrier.
At very high frequencies,
1
1
v GND2
CISO
=
=
C
1
1
vN
+
ISO
CISO
CIN 1 +
C
IN
=
Figure 29. Device Model For Static Discharge
Testing
1
= 0.94
1+ 1
16
(3)
, and 94% of VN appears across the barrier. As long as
RISO is greater than RIN and CISO is less than CIN, most
of the transient noise appears across the isolation
barrier, as it should.
We do not recommend using ESD generators to test equipment transient susceptibility, or considering product
claims of ESD ratings above the barrier transient ratings of an isolated interface. ESD is best managed through
recessing or covering connector pins in a conductive connector shell, and by proper installer training.
20
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ISO1176DW
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ISO1176DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ISO1176DWR
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ISO1176DWRG4
ACTIVE
SOIC
DW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Oct-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ISO1176DWR
Package Package Pins
Type Drawing
SOIC
DW
16
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.9
10.78
3.0
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Oct-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO1176DWR
SOIC
DW
16
2000
358.0
335.0
35.0
Pack Materials-Page 2
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