U6220B 1.3 GHz PLL for TV- and VCR- Tuner Description The U6220B is a single chip frequency synthesizer with I2C bus and 3-wire bus control (universal bus). This IC contains a high frequency prescaler, a crystal oscillator, a switchable reference divider, 5 open collector switching outputs and an additional mixer switch output for band switching. The U6220B is especially designed for low cost, high performance 2-band and EasyLink tuners (please see application note ANT017 ‘Semiconductors for TV Tuners - The New EasyLink Concept’). Features D 1.3 GHz divide-by-8 prescaler integrated D EasyLink interface to MOSMIC and mixer IC D Universal bus: D 3-wire bus mode: 4 port outputs (open collector) Lock-signal output (open collector) I2C bus or 3-wire bus I2C bus software compatible to U6204B 3-wire bus software compatible to U6359B (18 bit) D I2C bus mode: D Low power consumption (typ. 5 V / 20 mA) D Electrostatic protection according to MIL-STD 883 D SO16 small package 5 port outputs (open collector) 4 addresses selectable at Pin 3 for multituner application Block Diagram AS / ENA 3 SCL 5 SDA 4 Universal bus control ( I2 C–bus or 3–wire bus) Ports 7 bit latch Vs 6 5 bit latch 8 bit latch VHF L/H 8 UHF 9 P6 / Lock 10 FM Trap T1 6 bit latch 11 MS 12 GND 15 OS 15 bit latch T0 14 8 Prescaler RFi 13 5I FPRD 15 bit counter Phase detector RD1 Charge pump 16 VD RD2 1 CRYSTAL VHF 7 2 Oscillator 256 / 512 / 1024 PD FRFD 12426 Figure 1. Block diagram TELEFUNKEN Semiconductors Rev. A2, 23-Sep-96 1 (14) Preliminary Information U6220B Ordering Information Extended Type Number U6220B-APG3 Package SO16 plastic Remarks Taped and reeled Pin Description PD 1 16 VD Q1 2 15 GND 3 14 RFi 4 13 RFi SCL 5 12 Vs VHF 6 11 MS AS/ENA SDA VHF L/H 10 FM Trap 7 UHF 8 9 P6/Lock 12427 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol PD Q1 AS/ ENA SDA SCL VHF VHF L/H UHF P6/ Lock FM Trap MS VS RFi RFi END VD Function Charge pump output Crystal input Address select input Enable input Data input/ output Clock input VHF switch VHF low/ high switch UHF switch Port output (I2C bus mode) Lock output (3-wire bus mode) Channel 6 FM Trap switch Mixer switch output Supply voltage RF input RF input Ground Active filter output Figure 2. Pinning Description The U6220B is a single cip PLL designed for TV and VCR receiver systems. It consists of a divide-by-8 prescaler (up to 1.3 GHz) with an integrated preamplifier, a 15bit programmable divider, a crystal oscillator and a reference divider with three selectable divider ratios ( 256 / 512 / 1024), a phase/frequency detector together with a charge-pump, which drives the tuning amplifier. Only one external transistor is required for varactor line driving. The device can be controlled via a I2C bus format or 3-wire bus format. It detects automatically which bus format has been received, therefore there is no need for a bus selection pin. In I2C B B B bus mode the device has four programmable addresses, programmed by applying a specific input voltage to the address select input, enabling the use of up to four synthesizers in a system. The same pin serves in 3-wire bus mode as the enable signal input. Five open collector outputs for band switching functions are included, four of them are capable of sinking at least 10 mA and the VHF L/H output can sink 30 mA. One of these open collector outputs serves as a lock-signal output in the 3-wire bus mode. The MS output is provided to control directly a mixer-oscillator IC according to the band switching information. 2 (14) Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 23-Sep-96 U6220B Absolute Maximum Ratings All voltages are referred to GND (Pin 15) Parameters Supply voltage RF input voltage Crystal oscillator voltage Charge pump output voltage Active filter output voltage Bus input/ output voltage SDA output current Address select / ENA voltage Mixer switch voltage Port output current Port output current Total port output current Port output voltage Test Conditions / Pins Pin 12 Pins 13 and 14 Pin 2 Pin 1 Pin 16 Pins 4 and 5 Open collector Pin 4 Pin 3 Junction temperature Storage temperature In on state Open collector, Open collector, Open collector, In off state, Pin 11 Pins 6, 8-10 Pin 7 Pins 6 to 10 Pins 6 to 10 Symbol VS RFi Q1 PD VD VSDA,SCL ISDA VAS/ENA Min. –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –1 –0.3 Max. 6 VS + 0.3 VS + 0.3 VS + 0.3 VS + 0.3 6 5 VS + 0.3 Unit V V V V V V mA V MS VHF L/H –0.3 –1 –1 Tjmax Tstg –0.3 –0.3 –40 –40 VS + 0.3 15 40 50 14 6 150 150 V mA mA mA V V °C °C Operating Range All voltages are referred to GND (Pin 15) Parameters Supply voltage Ambient temperature Input frequency Programmable divider Test Conditions / Pins Pin 12 Pins 13 and 14 I2C bus mode 3-wire bus mode Symbol VS Tamb Rfi SF Min. 4.5 –20 80 256 256 Typ. 5 Max. 5.5 85 1300 32767 16383 Unit V °C MHz Value 110 Unit K/W Thermal Resistance Parameters Junction ambient TELEFUNKEN Semiconductors Rev. A2, 23-Sep-96 Symbol RthJA Test conditions Soldered to PCB 3 (14) Preliminary Information U6220B Electrical Characteristics Test conditions (unless otherwise specified): VS = 5 V, Tamb = 25°C Parameters Supply current Test Conditions / Pins VHF, UHF: on VHF L/H, FM Trap: off Pin 12 Symbol IS Min. 15 Typ. 20 Max. 25 Input sensitivity fRFi = 80 - 1000 MHz Pin 13 VRFi 1) 10 315 fRFi = 1300 MHz Pin 13 VRFi 1) 40 315 Crystal oscillator Recommended crystal series 10 200 resistance Crystal oscillator drive level Pin 2 50 Crystal oscillator source –650 Nominal spread 15%, impedance Pin 2 External reference input AC coupled sinewave 2 8 frequency Pin 2 External reference input AC coupled sinewave Vi 1) 70 200 amplitude Pin 2 Switching output / lock output (open collector, VHF (Pin 6), UHF (Pin 8), P6/Lock (Pin 9), FMtrap (Pin 10), Lock condition: LOW) Leakage current VH = 13.5 V IL 10 Saturation voltage IL = 10 mA VSL 2) 0.5 VHF L/H switching output (open collector, VHF L/H (Pin 7)) Leakage current VH = 13.5 V IL 10 2) Saturation voltage IL = 30 mA VSL 0.5 " Unit mA mVrms mVrms W mVrms W MHz mVrms mA V mA V Notes: 1) RMS - voltage calculated from the measured available power om 50 W 2) Tested with one switch active. The collector voltage may not exceed 6 V 4 (14) Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 23-Sep-96 U6220B Electrical Characteristics (continued) Parameters Charge pump output, PD Charge pump current ‘H’ (I2C and 3-wire bus mode) Charge pump current ‘L’ (only I2C bus mode) Charge pump leakage current Charge pump amplifier gain Bus inputs, SDA, SCL Input voltage high Input voltage low Input current high Test Conditions / Pins Symbol 5l = 1, VPD = 1.7 V Min. IPDL Pin 1 T0 = 0, VPD = 1.7 V IPDTRI Pin 1 Pins 1 and 16 Pins 4 and 5 Pin 4 and 5 Vi‘H’ = VS Max. "180 "50 "5 IPDH Pin 1 5l = 1, VPD = 1.7 V Typ. Unit mA nA nA 6400 Vi‘H’ Vi‘L’ Ii‘H’ 3 Ii‘L’ –10 5.5 1.5 10 V V mA Pins 4 and 5 Input current low Vi‘L’ = 0 V mA Pins 4 and 5 Leakage current VS = 0 V IL 10 mA VSDA‘L’ 0.4 V 10 mA mA 1 VS V mA Pins 4 and 5 Output voltage SDA ISDA‘L’ = 3 mA (open collector) Address selection / Enable input, AS / ENA Input current high Vi‘H’ = VS Input current low Vi‘L’ = 0 V Mixer switch output, MS Output voltage VHF IMS = –20 uA Output voltage UHF IMS = –20 uA TELEFUNKEN Semiconductors Rev. A2, 23-Sep-96 Pin 4 Pin 3 Pin 3 Ii‘H’ Ii‘L’ –100 Pin 11 Pin 11 VMS VHF VMS UHF 0 3.5 0.25 VS–0.75 5 (14) Preliminary Information U6220B Functional Description The U6220B is programmed via a 2-wire I2C bus or 3-wire bus depending on the received data format. The three bus inputs Pins 3, 4 and 5 are used as address select, SDA and SCL inputs in I2C bus mode and as ENABLE, DATA and CLOCK inputs in 3-wire bus mode. The data includes the scaling factor SF (15/14bit) and switching output information. In I2C bus mode, there are some additional functions included for testing of the device. Oscillator frequency calculation: fVCO = 8 x SPF x frefOSC / SRF fVCO: Locked frequency of voltage controlled oscillator SPF: Scaling factor of programmable divider (15bit in I2C- or 14bit in 3-wire bus mode) SRF: Scaling factor of reference divider (B256/ B512/ B1024/ in I C bus mode or B512 in 2 3-wire bus mode) frefOSC: Reference oscillator frequency: 3.2/ 4 MHz crystal or external reference frequency This input amplifier together with a divide-by-8 prescaler provides excellent sensitivity (see ‘TYPICAL PRESCALER INPUT SENSITIVITY’. The input impedance is shown in the diagram ‘TYPICAL IMPEDANCE’. When a new divider ratio according to the requested fVCO is entered, the phase detector and charge pump together with the tuning amplifier adjusts the control voltage of the VCO until the output signals of the programmable divider and the reference divider are in frequency locked and phase locked. The reference frequency may be provided by an external source capacitively coupled into Pin 2, or by using an on-board crystal with an 18 pF capacitor in series. The crystal operates in the series resonance mode. In I2C bus mode the reference divider division ratio is selectable to 256/ 512/ 1024 to two bits of the control byte 2. In 3-wire bus mode it is fixed to 512. Therefore, with a 4 MHz crystal and the nominal division ratio of 512 of the reference divider, the comparison frequency is 7.8125 kHz, which gives 62.5 kHz steps for the VCO, or with a 3.2 kHz crystal respectively 6.25 kHz comparison frequency and 50 kHz VCO step size. In addition, there are switching outputs available for band switching and other purposes. B B B B B Application A typical application is shown on page 13. All input/ output interface circuits are shown on page 11. Some special features which are related to test- and alignment procedures for tuner production are explained together within the following bus mode description. I2C Bus Description When the U6220B is controlled via a 2-wire I2C bus format, then data and clock signals are fed into the SDA and SCL lines respectively. The table ‘I2C BUS DATA FORMAT’ describes the format of the data and shows how to select the device address by applying a voltage at Pin 3. When the correct address byte has been received., the SDA line is pulled low by the device during the acknowledge period, and then also during the acknowledge periods, when additional data bytes are programmed. After the address transmission (first byte), data bytes can be sent to the device. There are four data bytes requested to fully program the device. The table ‘I2C BUS PULSE DIAGRAM’ shows some possible data transfer examples. Programmable divider bytes PDB1 and PDB2 are stored in a 15 bit latch and control the division ratio of the 15 bit programmable divider. The control byte CB1 enables the control of the following special functions: – 5l-bit switches between low and high charge pump current – T1-bit enables divider test mode when it is set to logic 1 – T0-bit allows to disable the charge pump when it is set to logic 1 – RD1-bit and RD2-bit allow to select the reference divider factor. – Os-bit disables the charge pump drive amplifier output when it is set to logic 1. The charge pump current can only be controlled in I2C bus mode. In 3-wire bus mode, there is always the high charge pump current active. The OS-bit function disables the complete PLL function. This enables the tuner alignment by supplying the tuning voltage directly through the 33 V supply voltage of the tuner. The control byte CB2 programs the switching outputs VHF, VHF L/H, UHF, P6, FM Trap according the band switching logic table on page 8. 6 (14) Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 23-Sep-96 U6220B I2C Bus Description (continued) Description I2C Bus Data Format MSB 1 0 n7 1 x Address byte Programmable divider, byte 1 Programmable divider, byte 2 Control byte 1 Control byte 2 1 n14 n6 5l P6 0 n13 n5 T1 x 0 n12 n4 T0 P4 0 n11 n3 x x AS1 n10 n2 RD2 P2 AS2 n9 n1 Rd1 P1 0 n8 n0 OS P0 A A A A A A = Acknowledge, X = not used n0...n14: T0, T1: Scaling factor (SF) Testmode selection P0, 1, 2, 4 P6 5I: OS: SF = 16384 x n14 + 8192 x n13 +...+2 x n1 + n0 T1 = 1: divider test mode on T1 = 0: divider test mode off FPRD at Pin 6/ FRFD at Pin 7 T0 = 1: charge pump disable T0 = 0: charge pump enable Band switching according logic table page 8 Port output P6 = 1; open collector active Charge pump current switch 5l = 1: high current 5l = 0: low current Output switch OS = 1: varicap drive disable OS = 0: varicap drive enable RD1, RD2: Reference divider selection RD2 0 0 1 1 RD1 0 1 0 1 Reference divider ratio off 1024 256 512 AS1, AS2: Address selection Pin 3 AS1 0 0 1 1 AS2 1 0 0 1 TELEFUNKEN Semiconductors Rev. A2, 23-Sep-96 Address 1 2 3 4 Dec. value 194 192 196 198 Voltage at Pin 3 open 0 to 10% VS 40 to 60% VS 90 to 100% VS 7 (14) Preliminary Information U6220B I2C Bus Description (continued) Band Switching Logic in I2C Bus Mode (2 mixer EasyLink with MOSMIC gate1 switch off logic) P0 P4 P2 P1 VHF Pin6 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 UHF VHF high VHF low (except channel 6) VHF channel 6 – – – – – UHF Pin 8 on off off VHF L/H Pin 7 off on off MS Pin 11 off on on FM Trap Pin 10 off off off off off on on 0V /A/ 4.BYTE 4V 0V 0V Port VHF switches the VHF MOSMIC (inverse logic) Port VHF L/H switches the VHF switching-diode (high output current output) Port UHF switches the UHF MOSMIC (inverse logic) Port FM Trap switches the FM Trap in channel 6 Port MS switches the MX band switch input (e.g. U2326B) I2C Bus Pulse Diagram ADDRESS BYTE / A / 1.BYTE /A/ 2.BYTE /A/ 3.BYTE /A/ SDA SCL START 1 2 3 4 5 6 7 8 9 1... 8 9 1... 8 9 1... 8 9 1... 8 9 STOP 12428 Data transfer examples START - ADR - PDB1 -PDB2 - CB1 - CB2 - STOP START - ADR - CB1 - CB2 -PDB1 - PDB2 - STOP START - ADR - PDB1 - PDB2 - CB1 - STOP START - ADR - CB1 - CB2 - PDB1 - STOP START - ADR - PDB1 - PSB2 - STOP START - ADR -CB1 - CB2 - STOP START - ADR - CB1 - STOP Description START ADR PDB1 PDB2 CB1 CB2 STOP = Start condition = Address byte = Programmable divider byte 1 = Programmable divider byte 2 = Control byte 1 = Control byte 2 = Stop condition 8 (14) Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 23-Sep-96 U6220B I2C Bus Description (continued) I2C Bus Timing t W STT SDA t S STT t LOW tR t HIGH tF t S STP SCL t H STT t S DAT START CLOCK t H DAT DATACHANGE STOP 12429 Parameter Rise time SDA, SCL Fall time SDA, SCL Clock frequency SCL Clock ‘H’ pulse Clock ‘L’ pulse Hold time start Waiting time start Setup time start Setup time stop Setup time data Hold time data Symbol tR tF FSCL tHIGH tLOW tH STT tW STT tS STT tS STP tS DAT tH DAT Conditions Min. 0 4 4 4 4 4 4 0.3 0 Max. 15 15 100 Unit ms ms kHz ms ms ms ms ms ms ms ms 3-Wire Bus Description When the U6220B is controlled via a 3-wire bus format, then data, clock and enable signals are fed into the SDA, SCL and AS/ENA lines respectively. The diagram ‘3-WIRE BUS PULSE DIAGRAM’ shows the data format. The data consist of a single word, which contains the programmable divider (14bit) and switch information (4 bit). The data is only clocked into the internal data shift register on the negative clock transition during the enable high period. During enable low periods, the clock input is disabled. New data words are only accepted by the internal data latches from the shift register on a negative transition of the enable signal, if exactly eighteen clock pulses were sent during the high period of the enable. The data sequence and the timing is described in the following diagrams. In 3-wire bus mode Pin 9 becomes automatically the TELEFUNKEN Semiconductors Rev. A2, 23-Sep-96 lock-signal output. an improved lock detect circuit generates a flag when the loop has attained lock. ‘In lock’ is indicated by a low impedance state (on) of the open collector output. In 3-wire bus mode, the high charge pump current is always. Only in I2C bus mode can the charge pump current be controlled. The complete PLL function can be disabled by programming a division ratio of zero, which is normally not used. This enables the tuner alignment by supplying the tuning voltage directly through the 33-V supply voltage of the tuner. In 3-wire bus mode the division ratio of the reference divider is fixed to divide by 512. It can be controlled only in I2C bus mode. 9 (14) Preliminary Information U6220B 3-Wire Bus Description (continued) Band Switching Logic in 3-Wire Bus Mode (2-mixer EasyLink with MOSMIC gate 1 switch off logic) B1 B2 B3 B4 VHF Pin 6 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 on off off off UHF VHF high VHF low (except channel 6) VHF channel 6 – – – – – VHF L/H Pin 7 off on off off UHF Pin 8 off on on on FM Trap Pin 10 off off off on MS Pin 11 4V 0V 0V 0V Port VHF switches the VHF-MOSMIC (inverse logic) Port VHF L/H switches the VHF-switching diode (high output current output) Port UHF switches the UHF-MOSMIC (inverse logic) Port FM Trap switches the FM Trap in channel 6 Port MS switches the MX band switch input (e.g. U2326B) 3-Wire Bus Pulse Diagram B1 4 Bit Ports B2 B3 14 Bit scaling factor SF B4 LSB MSB SDA SCL AS / ENA 12430 Figure 3. 3-Wire Bus Timing SDA LSB SCL AS / ENA TL TS TC TH TSL 12431 TT Figure 4. Parameter Setup time Enable hold time Clock width Enable setup time Enable between two transmissions Data hold time Symbol TS TSL TC TL TT TH Conditions Min. 2 2 2 10 10 2 10 (14) Preliminary Information Max. Unit ms ms ms ms ms ms TELEFUNKEN Semiconductors Rev. A2, 23-Sep-96 U6220B Input/ Output Interface Circuits Vs Vs 1.5k 1.5k 1k RFi AS/ENA RFi 12435 12432 Figure 8. Address select/Enable input Vs Figure 5. RF Input MS Vs 12436 Port Figure 9. Mixer switch output Vs 12433 SDA/SCL Figure 6. Ports ACK 12437 Vs Figure 10. SCL and SDA input Vs 60 2k PD Crystal Q1 12434 VD OS 45k Figure 7. Reference oscillator 12438 Figure 11. Loop amplifier TELEFUNKEN Semiconductors Rev. A2, 23-Sep-96 11 (14) Preliminary Information U6220B Typical Prescaler Input Sensitivity Vi (mVrms on 50 W) ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ Ï ÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ Ï ÏÏ ÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏ ÏÏÏÏÏ Ï 1000 100 Operating window 10 1 0,1 0 200 400 600 800 1000 1200 1400 1600 1800 Frequency (MHz) 2000 12439 Figure 12. Typical Input Impedance j 0.5j 2j 0.2j 5j 0 0.2 1 0.5 2 –0.2j 5 100 MHz 500 MHz X X R –5j 1 GHz X X 1.5 GHz –0.5j –j –2j Z0 = 50 W 12440 Figure 13. 12 (14) Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 23-Sep-96 U6220B Application Circuit MOSMIC MX / OSC f IF AGC IF–Section ANT 10k f VCO OSC 4n7 33 V 22 k 4 MHz 18 p 39 n PD 1n 2 1n RFi 13 14 1 22 k 180 n VD U6220B 16 MS 11 6 VHF 8 7 UHF VHF L/H 10 12 Vs 15 GND AS / ENA SCL from/to SDA P6 / Lock 3 5 4 9 mC FM Trap 12441 Figure 14. Package Dimensions Small outline plastic package, 16 pin-SO16 Dimensions in mm 3,85 max 1,4 0,1 min 0,49 0,35 1,27 8,89 TELEFUNKEN Semiconductors Rev. A2, 23-Sep-96 (1,7) (1,45) 9 16 1 5,2 5,0 6,2 6,0 0,25 0,15 9,85 max 8 13 (14) Preliminary Information U6220B Ozone Depleting Substances Policy Statement It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423 14 (14) Preliminary Information TELEFUNKEN Semiconductors Rev. A2, 23-Sep-96