MICROCHIP PIC32MX7XX

PIC32MX5XX/6XX/7XX
Family Data Sheet
High-Performance, USB, CAN and Ethernet
32-Bit Flash Microcontrollers
 2010 Microchip Technology Inc.
Preliminary
DS61156C
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-037-9
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS61156C-page 2
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
High-Performance, USB, CAN and Ethernet
32-Bit Flash Microcontrollers
High-Performance 32-Bit RISC CPU:
Peripheral Features (Continued):
• MIPS32® M4K™ 32-bit core with 5-stage pipeline
• 80 MHz maximum frequency
• 1.56 DMIPS/MHz (Dhrystone 2.1) performance
at zero Wait state Flash access
• Single-cycle multiply and high-performance divide
unit
• MIPS16e™ mode for up to 40% smaller code size
• Two sets of 32 core register files (32-bit) to reduce
interrupt latency
• Prefetch Cache module to speed execution from
Flash
• Internal 8 MHz and 32 kHz oscillators
• Six UART modules with:
- RS-232, RS-485 and LIN 1.2 support
- IrDA® with on-chip hardware encoder and
decoder
• Up to four SPI modules
• Up to five I2C™ modules
• Separate PLLs for CPU and USB clocks
• Parallel Master and Slave Port (PMP/PSP) with
8-bit and 16-bit data, and up to 16 address lines
• Hardware Real-Time Clock/Calendar (RTCC)
• Five 16-bit Timers/Counters (two 16-bit pairs
combine to create two 32-bit timers)
• Five Capture inputs
• Five Compare/PWM outputs
• Five external interrupt pins
• High-speed I/O pins capable of toggling at up to
80 MHz
• High-current sink/source (18 mA/18 mA) on
all I/O pins
• Configurable open-drain output on digital I/O pins
Microcontroller Features:
• Operating voltage range of 2.3V to 3.6V
• 256K to 512K Flash memory (plus an additional
12 KB of Boot Flash)
• 64K to 128K SRAM memory
• Pin-compatible with most PIC24/dsPIC® devices
• Multiple power management modes
• Multiple interrupt vectors with individually
programmable priority
• Fail-Safe Clock Monitor mode
• Configurable Watchdog Timer with on-chip
Low-Power RC oscillator for reliable operation
Peripheral Features:
• Atomic Set, Clear and Invert operation on select
peripheral registers
• 8-channel hardware DMA with automatic data
size detection
• USB 2.0-compliant full-speed device and
On-The-Go (OTG) controller:
- Dedicated DMA channels
• 10/100 Mbps Ethernet MAC with MII and RMII
interface:
- Dedicated DMA channels
• CAN module:
- 2.0B Active with DeviceNet™ addressing
support
- Dedicated DMA channels
• 3 MHz to 25 MHz crystal oscillator
 2010 Microchip Technology Inc.
Debug Features:
• Two programming and debugging Interfaces:
- 2-wire interface with unintrusive access and
real-time data exchange with application
- 4-wire MIPS® standard enhanced JTAG
interface
• Unintrusive hardware-based instruction trace
• IEEE Standard 1149.2 compatible (JTAG)
boundary scan
Analog Features:
• Up to 16-channel, 10-bit Analog-to-Digital
Converter:
- 1 Msps conversion rate
- Conversion available during Sleep and Idle
• Two Analog Comparators
• 5V tolerant input pins (digital pins only)
Preliminary
DS61156C-page 3
PIC32MX5XX/6XX/7XX
Pins
Program Memory (KB)
Data Memory (KB)
USB
Ethernet
CAN
Timers/Capture/Compare
DMA Channels
(Programmable/
Dedicated)
UART(2,3)
SPI(3)
I2C™(3)
10-Bit 1 Msps ADC
(Channels)
Comparators
PMP/PSP
JTAG
Trace
Packages(4)
PIC32MX FEATURES
Device
TABLE 1:
PIC32MX575F256H
64
256 + 12(1)
64
1
0
1
5/5/5
8/4
6
3
4
16
2
Yes Yes
No
PT,
MR
PIC32MX675F256H
64
256 + 12(1)
64
1
1
0
5/5/5
8/4
6
3
4
16
2
Yes Yes
No
PT,
MR
PIC32MX775F256H
64
256 + 12(1)
64
1
1
2
5/5/5
8/8
6
3
4
16
2
Yes Yes
No
PT,
MR
PIC32MX575F512H
64
512 + 12(1)
64
1
0
1
5/5/5
8/4
6
3
4
16
2
Yes Yes
No
PT,
MR
PIC32MX675F512H
64
512 + 12(1)
64
1
1
0
5/5/5
8/4
6
3
4
16
2
Yes Yes
No
PT,
MR
PIC32MX695F512H
64
512 + 12(1) 128
1
1
0
5/5/5
8/4
6
3
4
16
2
Yes Yes
No
PT,
MR
PIC32MX775F512H
64
512 + 12(1)
64
1
1
2
5/5/5
8/8
6
3
4
16
2
Yes Yes
No
PT,
MR
PIC32MX795F512H
64
512 + 12(1) 128
1
1
2
5/5/5
8/8
6
3
4
16
2
Yes Yes
No
PT,
MR
PIC32MX575F256L
100 256 + 12(1)
64
1
0
1
5/5/5
8/4
6
4
5
16
2
Yes Yes Yes
PT,
PF,
BG
PIC32MX675F256L
100 256 + 12(1)
64
1
1
0
5/5/5
8/4
6
4
5
16
2
Yes Yes Yes
PT,
PF,
BG
PIC32MX775F256L
100 256 + 12(1)
64
1
1
2
5/5/5
8/8
6
4
5
16
2
Yes Yes Yes
PT,
PF,
BG
PIC32MX575F512L
100 512 + 12(1)
64
1
0
1
5/5/5
8/4
6
4
5
16
2
Yes Yes Yes
PT,
PF,
BG
PIC32MX675F512L
100 512 + 12(1)
64
1
1
0
5/5/5
8/4
6
4
5
16
2
Yes Yes Yes
PT,
PF,
BG
PIC32MX695F512L
100
128
1
1
0
5/5/5
8/4
6
4
5
16
2
Yes Yes Yes
PT,
PF,
BG
PIC32MX775F512L
100 512 + 12(1)
64
1
1
2
5/5/5
8/8
6
4
5
16
2
Yes Yes Yes
PT,
PF,
BG
PIC32MX795F512L
100 512 + 12(1) 128
1
1
2
5/5/5
8/8
6
4
5
16
2
Yes Yes Yes
PT,
PF,
BG
Legend:
Note 1:
2:
3:
4:
512 + 12(1)
PF, PT = TQFP
MR = QFN
BG = XBGA
This device features 12 KB boot Flash memory.
CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more
information.
Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Pin Diagrams” section for more
information.
Refer to Section 32.0 “Packaging Information” for detailed information.
DS61156C-page 4
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams
64-Pin QFN
C1TX/RF1
C1RX/RF0
VDD
VCAP/VDDCORE
CN16/RD7
CN15/RD6
PMRD/CN14/RD5
OC5/IC5/PMWR/CN13/RD4
SCL1A/SDO1A/U1ATX/OC4/RD3
SDA1A/SDI1A/U1ARX/OC3/RD2
SCK1A/U1BTX/U1ARTS/OC2/RD1
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PMD5/RE5
PMD6/RE6
PMD7/RE7
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
MCLR
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
VSS
VDD
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC32MX575F256H
PIC32MX575F512H
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/INT0/RD0
IC4/PMCS1/PMA14/INT4/RD11
SCL1/IC3/PMCS2/PMA15/INT3/RD10
SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9
RTCC/IC1/INT1/RD8
Vss
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
D+/RG2
D-/RG3
VUSB
VBUS
USBID/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AVDD
AVSS
AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8
AN9/C2OUT/PMA7/RB9
TMS/AN10/CVREFOUT/PMA13/RB10
TDO/AN11/PMA12/RB11
VSS
VDD
TCK/AN12/PMA11/RB12
TDI/AN13/PMA10/RB13
AN14/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14
AN15/OCFB/PMALL/PMA0/CN12/RB15
AC1TX/SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
AC1RX/SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 5
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin QFN
ETXEN/PMD5/RE5
1
ETXD0/PMD6/RE6
ETXD1/PMD7/RE7
2
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
4
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
5
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
6
MCLR
7
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
8
SDA1A/SDI1A/U1ARX/OC3/RD2
EMDIO/AEMDIO/SCK1A/U1BTX/U1ARTS/OC2/RD1
SCL1A/SDO1A/U1ATX/OC4/RD3
OC5/IC5/PMWR/CN13/RD4
PMRD/CN14/RD5
AETXEN/ETXERR/CN15/RD6
ETXCLK/AERXERR/CN16/RD7
VDD
VCAP/VDDCORE
AETXD0/ERXD2/RF1
AETXD1/ERXD3/RF0
ERXD1/PMD0/RE0
ERXD0/PMD1/RE1
ERXDV/ECRSDV/PMD2/RE2
ERXCLK/EREFCLK/PMD3/RE3
ERXERR/PMD4/RE4
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
3
VSS
9
VDD
10
AN5/C1IN+/VBUSON/CN7/RB5
11
AN4/C1IN-/CN6/RB4
12
AN3/C2IN+/CN5/RB3
13
AN2/C2IN-/CN4/RB2
14
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
15
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
16
PIC32MX675F256H
PIC32MX675F512H
PIC32MX695F512H
SOSCO/T1CK/CN0/RC14
47
SOSCI/CN1/RC13
46
OC1/INT0/RD0
45
ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
44
ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
43
AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9
42
RTCC/AERXD1/ETXD3/IC1/INT1/RD8
41
Vss
40
OSC2/CLKO/RC15
39
OSC1/CLKI/RC12
38
VDD
37
D+/RG2
36
D-/RG3
35
VUSB
34
VBUS
33
USBID/RF3
Note:
SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15
AN14/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14
TDI/AN13/PMA10/RB13
VDD
TCK/AN12/PMA11/RB12
VSS
TDO/AN11/PMA12/RB11
TMS/AN10/CVREFOUT/PMA13/RB10
AN9/C2OUT/PMA7/RB9
AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8
AVSS
AVDD
PGED2/AN7/RB7
PGEC2/AN6/OCFA/RB6
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
DS61156C-page 6
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin QFN
ETXEN/PMD5/RE5
1
ETXD0/PMD6/RE6
ETXD1/PMD7/RE7
2
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
4
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
5
6
MCLR
7
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
8
VSS
9
VDD
10
AN5/C1IN+/VBUSON/CN7/RB5
11
AN4/C1IN-/CN6/RB4
12
AN3/C2IN+/CN5/RB3
13
AN2/C2IN-/CN4/RB2
14
Note:
EMDIO/AEMDIO/SCK1A/U1BTX/U1ARTS/OC2/RD1
SDA1A/SDI1A/U1ARX/OC3/RD2
SCL1A/SDO1A/U1ATX/OC4/RD3
OC5/IC5/PMWR/CN13/RD4
PMRD/CN14/RD5
AETXEN/ETXERR/CN15/RD6
ETXCLK/AERXERR/CN16/RD7
VCAP/VDDCORE
VDD
C1TX/AETXD0/ERXD2/RF1
C1RX/AETXD1/ERXD3/RF0
ERXD1/PMD0/RE0
ERXD0/PMD1/RE1
PIC32MX775F256H
PIC32MX775F512H
PIC32MX795F512H
SOSCO/T1CK/CN0/RC14
47
SOSCI/CN1/RC13
46
OC1/INT0/RD0
45
ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
44
ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
43
AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9
42
RTCC/AERXD1/ETXD3/IC1/INT1/RD8
41
Vss
40
OSC2/CLKO/RC15
39
OSC1/CLKI/RC12
USBID/RF3
AC1RX/SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
AC1TX/SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15
AN14/C2RX/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14
TDI/AN13/PMA10/RB13
TCK/AN12/PMA11/RB12
VDD
VSS
TDO/AN11/PMA12/RB11
VBUS
TMS/AN10/CVREFOUT/PMA13/RB10
VUSB
34
15
33
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AN9/C2OUT/PMA7/RB9
D-/RG3
35
AN8/C2TX/SS3A/U3BRX/U3ACTS/C1OUT/RB8
36
AVSS
D+/RG2
AVDD
VDD
37
PGED2/AN7/RB7
38
PGEC2/AN6/OCFA/RB6
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
ERXDV/ECRSDV/PMD2/RE2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
3
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
ERXCLK/EREFCLKPMD3/RE3
ERXERR/PMD4/RE4
= Pins are up to 5V tolerant
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 7
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
C1TX/RF1
C1RX/RF0
VDD
VCAP/VDDCORE
CN16/RD7
CN15/RD6
PMRD/CN14/RD5
OC5/IC5/PMWR/CN13/RD4
SCL1A/SDO1A/U1ATX/OC4/RD3
SDA1A/SDI1A/U1ARX/OC3/RD2
SCK1A/U1BTX/U1ARTS/OC2/RD1
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
64-Pin TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PMD5/RE5
PMD6/RE6
PMD7/RE7
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
MCLR
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
VSS
VDD
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC32MX575F256H
PIC32MX575F512H
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/INT0/RD0
IC4/PMCS1/PMA14/INT4/RD11
SCL1/IC3/PMCS2/PMA15/INT3/RD10
SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9
RTCC/IC1/INT1/RD8
Vss
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
D+/RG2
D-/RG3
VUSB
VBUS
USBID/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AVDD
AVSS
AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8
AN9/C2OUT/PMA7/RB9
TMS/AN10/CVREFOUT/PMA13/RB10
TDO/AN11/PMA12/RB11
VSS
VDD
TCK/AN12/PMA11/RB12
TDI/AN13/PMA10/RB13
AN14/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14
AN15/OCFB/PMALL/PMA0/CN12/RB15
AC1TX/SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
AC1RX/SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DS61156C-page 8
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin TQFP
EMDIO/AEMDIO/SCK1A/U1BTX/U1ARTS/OC2/RD1
SDA1A/SDI1A/U1ARX/OC3/RD2
SCL1A/SDO1A/U1ATX/OC4/RD3
OC5/IC5/PMWR/CN13/RD4
PMRD/CN14/RD5
AETXEN/ETXERR/CN15/RD6
ETXCLK/AERXERR/CN16/RD7
VCAP/VDDCORE
VDD
AETXD0/ERXD2/RF1
AETXD1/ERXD3/RF0
ERXD1/PMD0/RE0
ERXD0/PMD1/RE1
ERXDV/ECRSDV/PMD2/RE2
ERXCLK/EREFCLK/PMD3/RE3
ERXERR/PMD4/RE4
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ETXEN/PMD5/RE5
1
ETXD0/PMD6/RE6
ETXD1/PMD7/RE7
2
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
4
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
5
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
6
MCLR
7
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
8
3
VSS
9
VDD
10
AN5/C1IN+/VBUSON/CN7/RB5
11
AN4/C1IN-/CN6/RB4
12
AN3/C2IN+/CN5/RB3
13
AN2/C2IN-/CN4/RB2
14
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
15
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
16
PIC32MX675F256H
PIC32MX675F512H
PIC32MX695F512H
48
SOSCO/T1CK/CN0/RC14
47
SOSCI/CN1/RC13
46
OC1/INT0/RD0
45
ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
44
ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
43
AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9
42
RTCC/AERXD1/ETXD3/IC1/INT1/RD8
41
Vss
40
OSC2/CLKO/RC15
39
OSC1/CLKI/RC12
38
VDD
37
D+/RG2
36
D-/RG3
35
VUSB
34
VBUS
33
USBID/RF3
 2010 Microchip Technology Inc.
Preliminary
SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15
AN14/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14
TDI/AN13/PMA10/RB13
TCK/AN12/PMA11/RB12
VDD
VSS
TDO/AN11/PMA12/RB11
TMS/AN10/CVREFOUT/PMA13/RB10
AN9/C2OUT/PMA7/RB9
AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8
AVSS
AVDD
PGED2/AN7/RB7
PGEC2/AN6/OCFA/RB6
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DS61156C-page 9
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin TQFP
EMDIO/AEMDIO/SCK1A/U1BTX/U1ARTS/OC2/RD1
SDA1A/SDI1A/U1ARX/OC3/RD2
SCL1A/SDO1A/U1ATX/OC4/RD3
OC5/IC5/PMWR/CN13/RD4
PMRD/CN14/RD5
AETXEN/ETXERR/CN15/RD6
ETXCLK/AERXERR/CN16/RD7
VDD
VCAP/VDDCORE
C1TX/AETXD0/ERXD2/RF1
C1RX/AETXD1/ERXD3/RF0
ERXD1/PMD0/RE0
ERXD0/PMD1/RE1
ERXDV/ECRSDV/PMD2/RE2
ERXCLK/EREFCLK/PMD3/RE3
ERXERR/PMD4/RE4
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ETXEN/PMD5/RE5
1
48
SOSCO/T1CK/CN0/RC14
ETXD0/PMD6/RE6
2
47
SOSCI/CN1/RC13
ETXD1/PMD7/RE7
3
46
OC1/INT0/RD0
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
4
45
ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
5
44
ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
6
43
AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9
MCLR
7
42
RTCC/AERXD1/ETXD3/IC1/INT1/RD8
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
8
VSS
9
PIC32MX775F256H
PIC32MX775F512H
PIC32MX795F512H
41
Vss
40
OSC2/CLKO/RC15
VDD
10
39
OSC1/CLKI/RC12
AN5/C1IN+/VBUSON/CN7/RB5
11
38
VDD
AN4/C1IN-/CN6/RB4
12
37
D+/RG2
AN3/C2IN+/CN5/RB3
13
36
D-/RG3
AN2/C2IN-/CN4/RB2
14
35
VUSB
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
15
34
VBUS
16
33
USBID/RF3
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
DS61156C-page 10
Preliminary
AC1TX/SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
AC1RX/SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15
AN14/C2RX/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14
TDI/AN13/PMA10/RB13
VDD
TCK/AN12/PMA11/RB12
VSS
TDO/AN11/PMA12/RB11
TMS/AN10/CVREFOUT/PMA13/RB10
AN9/C2OUT/PMA7/RB9
AN8/C2TX/SS3A/U3BRX/U3ACTS/C1OUT/RB8
AVSS
AVDD
PGED2/AN7/RB7
PGEC2/AN6/OCFA/RB6
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PMD4/RE4
PMD3/RE3
PMD2/RE2
TRD0/RG13
TRD1/RG12
TRD2/RG14
PMD1/RE1
PMD0/RE0
TRD3/RA7
TRCLK/RA6
PMD8/RG0
PMD9/RG1
C1TX/PMD10/RF1
C1RX/PMD11/RF0
VDD
VCAP/VDDCORE
PMD15/CN16/RD7
PMD14/CN15/RD6
PMRD/CN14/RD5
OC5/PMWR/CN13/RD4
PMD13/CN19/RD13
IC5/PMD12/RD12
OC4/RD3
OC3/RD2
OC2/RD1
100-Pin TQFP
RG15
1
75
VSS
VDD
2
74
SOSCO/T1CK/CN0/RC14
PMD5/RE5
3
73
SOSCI/CN1/RC13
PMD6/RE6
4
72
SDO1/OC1/INT0/RD0
PMD7/RE7
5
71
IC4/PMCS1/PMA14/RD11
T2CK/RC1
6
70
SCK1/IC3/PMCS2/PMA15/RD10
T3CK/RC2
7
69
SS1/IC2/RD9
T4CK/RC3
8
68
RTCC/IC1/RD8
T5CK/SDI1/RC4
9
67
SDA1/INT4/RA15
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
10
66
SCL1/INT3/RA14
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
11
65
VSS
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
12
64
OSC2/CLKO/RC15
63
OSC1/CLKI/RC12
62
VDD
61
TDO/RA5
MCLR
13
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
14
VSS
15
VDD
16
60
TDI/RA4
TMS/RA0
17
59
SDA2/RA3
INT1/RE8
18
58
SCL2/RA2
INT2/RE9
19
57
D+/RG2
AN5/C1IN+/VBUSON/CN7/RB5
20
56
D-/RG3
AN4/C1IN-/CN6/RB4
21
55
VUSB
AN3/C2IN+/CN5/RB3
22
54
VBUS
AN2/C2IN-/CN4/RB2
23
53
SCL1A/SDO1A/U1ATX/RF8
PGEC1/AN1/CN3/RB1
24
52
SDA1A/SDI1A/U1ARX/RF2
PGED1/AN0/CN2/RB0
25
51
USBID/RF3
 2010 Microchip Technology Inc.
Preliminary
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
VREF-/CVREF-/PMA7/RA9
VREF+/CVREF+/PMA6/RA10
AVDD
AVSS
AN8/C1OUT/RB8
AN9/C2OUT/RB9
AN10/CVREFOUT/PMA13/RB10
AN11/PMA12/RB11
VSS
VDD
TCK/RA1
AC1TX/SCK3A/U3BTX/U3ARTS/RF13
AC1RX/SS3A/U3BRX/U3ACTS/RF12
AN12/PMA11/RB12
AN13/PMA10/RB13
AN14/PMALH/PMA1/RB14
AN15/OCFB/PMALL/PMA0/CN12/RB15
VSS
VDD
SS1A/U1BRX/U1ACTS/CN20/RD14
SCK1A/U1BTX/U1ARTS/CN21/RD15
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PIC32MX575F512L
PIC32MX575F256L
DS61156C-page 11
PMD4/RE4
PMD3/RE3
PMD2/RE2
TRD0/RG13
TRD1/RG12
TRD2/RG14
PMD1/RE1
PMD0/RE0
TRD3/RA7
TRCLK/RA6
PMD8/RG0
ETXERR/PMD9/RG1
ETXD0/PMD10/RF1
ETXD1/PMD11/RF0
VDD
VCAP/VDDCORE
ETXCLK/PMD15/CN16/RD7
ETXEN/PMD14/CN15/RD6
PMRD/CN14/RD5
OC5/PMWR/CN13/RD4
ETXD3/PMD13/CN19/RD13
ETXD2/IC5/PMD12/RD12
OC4/RD3
OC3/RD2
OC2/RD1
PIC32MX675F256L
PIC32MX675F512L
PIC32MX695F512L
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
= Pins are up to 5V tolerant
 2010 Microchip Technology Inc.
PGED2/AN7/RB7
VREF-/CVREF-/AERXD2/PMA7/RA9
VREF+/CVREF+/AERXD3/PMA6/RA10
AVDD
AVSS
AN8/C1OUT/RB8
AN9/C2OUT/RB9
AN10/CVREFOUT/PMA13/RB10
AN11/ERXERR/AETXERR/PMA12/RB11
VSS
VDD
TCK/RA1
SCK3A/U3BTX/U3ARTS/RF13
SS3A/U3BRX/U3ACTS/RF12
AN12/ERXD0/AECRS/PMA11/RB12
AN13/ERXD1/AECOL/PMA10/RB13
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
VSS
VDD
AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14
AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
Preliminary
AERXERR/RG15
VDD
PMD5/RE5
PMD6/RE6
PMD7/RE7
T2CK/RC1
T3CK/RC2
T4CK/RC3
T5CK/SDI1/RC4
ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
MCLR
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
VSS
VDD
TMS/RA0
AERXD0/INT1/RE8
AERXD1/INT2/RE9
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/CN3/RB1
PGED1/AN0/CN2/RB0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
100-Pin TQFP
VSS
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
SDO1/OC1/INT0/RD0
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
SCK1/IC3/PMCS2/PMA15/RD10
SS1/IC2/RD9
RTCC/EMDIO/AEMDIO/IC1/RD8
AETXEN/SDA1/INT4/RA15
AETXCLK/SCL1/INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
D+/RG2
D-/RG3
VUSB
VBUS
SCL1A/SDO1A/U1ATX/RF8
SDA1A/SDI1A/U1ARX/RF2
USBID/RF3
PIC32MX5XX/6XX/7XX
DS61156C-page 12
Pin Diagrams (Continued)
PMD4/RE4
PMD3/RE3
PMD2/RE2
TRD0/RG13
TRD1/RG12
TRD2/RG14
PMD1/RE1
PMD0/RE0
TRD3/RA7
TRCLK/RA6
C2RX/PMD8/RG0
C2TX/ETXERR/PMD9/RG1
C1TX/ETXD0/PMD10/RF1
C1RX/ETXD1/PMD11/RF0
VDD
VCAP/VDDCORE
ETXCLK/PMD15/CN16/RD7
ETXEN/PMD14/CN15/RD6
PMRD/CN14/RD5
OC5/PMWR/CN13/RD4
ETXD3/PMD13/CN19/RD13
ETXD2/IC5/PMD12/RD12
OC4/RD3
OC3/RD2
OC2/RD1
PMD5/RE5
PMD6/RE6
PMD7/RE7
T2CK/RC1
T3CK/AC2TX/RC2
T4CK/AC2RX/RC3
T5CK/SDI1/RC4
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
MCLR
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
VSS
VDD
TMS/RA0
AERXD0/INT1/RE8
AERXD1/INT2/RE9
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/CN3/RB1
PGED1/AN0/CN2/RB0
19
20
21
22
23
24
25
73
72
71
70
69
PIC32MX775F256L
PIC32MX775F512L
PIC32MX795F512L
68
67
66
65
64
VSS
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
SDO1/OC1/INT0/RD0
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
SCK1/IC3/PMCS2/PMA15/RD10
SS1/IC2/RD9
RTCC/EMDIO/AEMDIO/IC1/RD8
AETXEN/SDA1/INT4/RA15
AETXCLK/SCL1/INT3/RA14
VSS
63
OSC2/CLKO/RC15
OSC1/CLKI/RC12
62
VDD
61
TDO/RA5
TDI/RA4
60
59
58
SDA2/RA3
SCL2/RA2
57
D+/RG2
56
55
D-/RG3
VUSB
54
53
VBUS
SCL1A/SDO1A/U1ATX/RF8
52
SDA1A/SDI1A/U1ARX/RF2
51
USBID/RF3
DS61156C-page 13
PIC32MX5XX/6XX/7XX
Preliminary
ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
75
74
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
VREF-/CVREF-/AERXD2/PMA7/RA9
VREF+/CVREF+/AERXD3/PMA6/RA10
AVDD
AVSS
AN8/C1OUT/RB8
AN9/C2OUT/RB9
AN10/CVREFOUT/PMA13/RB10
AN11/ERXERR/AETXERR/PMA12/RB11
VSS
VDD
TCK/RA1
AC1TX/SCK3A/U3BTX/U3ARTS/RF13
AC1RX/SS3A/U3BRX/U3ACTS/RF12
AN12/ERXD0/AECRS/PMA11/RB12
AN13/ERXD1/AECOL/PMA10/RB13
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
VSS
VDD
AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14
AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15
AERXERR/RG15
= Pins are up to 5V tolerant
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
100-Pin TQFP
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
 2010 Microchip Technology Inc.
Pin Diagrams (Continued)
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
121-Pin XBGA(1)
= Pins are up to 5V tolerant
PIC32MX575F256L
PIC32MX675F256L
PIC32MX775F256L
PIC32MX575F512L
PIC32MX675F512L
PIC32MX695F512L
PIC32MX775F512L
PIC32MX795F512L
A
B
C
D
E
F
G
H
J
K
L
1
2
3
4
5
6
7
8
9
10
11
RE4
RE3
RG13
RE0
RG0
RF1
VDD
VSS
RD12
RD2
RD1
NC
RG15
RE2
RE1
RA7
RF0
VCAP/
VDDCORE
RD5
RD3
VSS
RC14
RE6
VDD
RG12
RG14
RA6
NC
RD7
RD4
VDD
RC13
RD11
RC1
RE7
RE5
VSS
VSS
NC
RD6
RD13
RD0
NC
RD10
RC4
RC3
RG6
RC2
VDD
RG1
VSS
RA15
RD8
RD9
RA14
MCLR
RG8
RG9
RG7
VSS
NC
NC
VDD
RC12
VSS
RC15
RE8
RE9
RA0
NC
VDD
VSS
VSS
NC
RA5
RA3
RA4
RB5
RB4
VSS
VDD
NC
VDD
NC
VBUS
VUSB
RG2
RA2
RB3
RB2
RB7
AVDD
RB11
RA1
RB12
NC
NC
RF8
RG3
RB1
RB0
RA10
RB8
NC
RF12
RB14
VDD
RD15
RF3
RF2
RB6
RA9
AVSS
RB9
RB10
RF13
RB13
RB15
RD14
RF4
RF5
Note 1: Refer to Table 2, Table 3 and Table 4 for full pin names.
DS61156C-page 14
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 2:
PIN NAMES: PIC32MX575F256L AND PIC32MX575F512L DEVICES
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
A1
PMD4/RE4
E8
SDA1/INT4/RA15
A2
PMD3/RE3
E9
RTCC/IC1/RD8
A3
TRD0/RG13
E10
SS1/IC2/RD9
A4
PMD0/RE0
E11
SCL1/INT3/RA14
A5
PMD8/RG0
F1
MCLR
A6
C1TX/PMD10/RF1
F2
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
A7
VDD
F3
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
A8
VSS
F4
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
A9
IC5/PMD12/RD12
F5
VSS
A10
OC3/RD2
F6
No Connect (NC)
A11
OC2/RD1
F7
No Connect (NC)
B1
No Connect (NC)
F8
VDD
B2
RG15
F9
OSC1/CLKI/RC12
B3
PMD2/RE2
F10
VSS
B4
PMD1/RE1
F11
OSC2/CLKO/RC15
B5
TRD3/RA7
G1
INT1/RE8
B6
C1RX/PMD11/RF0
G2
INT2/RE9
B7
VCAP/VDDCORE
G3
TMS/RA0
B8
PMRD/CN14/RD5
G4
No Connect (NC)
B9
OC4/RD3
G5
VDD
B10
VSS
G6
VSS
B11
SOSCO/T1CK/CN0/RC14
G7
VSS
C1
PMD6/RE6
G8
No Connect (NC)
C2
VDD
G9
TDO/RA5
C3
TRD1/RG12
G10
SDA2/RA3
C4
TRD2/RG14
G11
TDI/RA4
C5
TRCLK/RA6
H1
AN5/C1IN+/VBUSON/CN7/RB5
C6
No Connect (NC)
H2
AN4/C1IN-/CN6/RB4
C7
PMD15/CN16/RD7
H3
VSS
C8
OC5/PMWR/CN13/RD4
H4
VDD
C9
VDD
H5
No Connect (NC)
C10
SOSCI/CN1/RC13
H6
VDD
C11
IC4/PMCS1/PMA14/RD11
H7
No Connect (NC)
VBUS
D1
T2CK/RC1
H8
D2
PMD7/RE7
H9
VUSB
D3
PMD5/RE5
H10
D+/RG2
SCL2/RA2
D4
VSS
H11
D5
VSS
J1
AN3/C2IN+/CN5/RB3
D6
No Connect (NC)
J2
AN2/C2IN-/CN4/RB2
D7
PMD14/CN15/RD6
J3
PGED2/AN7/RB7
D8
PMD13/CN19/RD13
J4
AVDD
D9
SDO1/OC1/INT0/RD0
J5
AN11/PMA12/RB11
D10
No Connect (NC)
J6
TCK/RA1
D11
SCK1/IC3/PMCS2/PMA15/RD10
J7
AN12/PMA11/RB12
E1
T5CK/SDI1/RC4
J8
No Connect (NC)
E2
T4CK/RC3
J9
No Connect (NC)
E3
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
J10
SCL1A/SDO1A/U1ATX/RF8
E4
T3CK/RC2
J11
D-/RG3
E5
VDD
K1
PGEC1/AN1/CN3/RB1
E6
PMD9/RG1
K2
PGED1/AN0/CN2/RB0
E7
VSS
K3
VREF+/CVREF+/PMA6/RA10
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 15
PIC32MX5XX/6XX/7XX
TABLE 2:
PIN NAMES: PIC32MX575F256L AND PIC32MX575F512L DEVICES (CONTINUED)
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
K4
AN8/C1OUT/RB8
L3
AVSS
K5
No Connect (NC)
L4
AN9/C2OUT/RB9
K6
AC1RX/SS3A/U3BRX/U3ACTS/RF12
L5
AN10/CVREFOUT/PMA13/RB10
K7
AN14/PMALH/PMA1/RB14
L6
AC1TX/SCK3A/U3BTX/U3ARTS/RF13
K8
VDD
L7
AN13/PMA10/RB13
K9
SCK1A/U1BTX/U1ARTS/CN21/RD15
L8
AN15/OCFB/PMALL/PMA0/CN12/RB15
SS1A/U1BRX/U1ACTS/CN20/RD14
K10
USBID/RF3
L9
K11
SDA1A/SDI1A/U1ARX/RF2
L10
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
L1
PGEC2/AN6/OCFA/RB6
L11
SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
L2
VREF-/CVREF-/PMA7/RA9
DS61156C-page 16
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 3:
PIN NAMES: PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
A1
PMD4/RE4
E8
AETXEN/SDA1/INT4/RA15
A2
PMD3/RE3
E9
RTCC/EMDIO/AEMDIO/IC1/RD8
A3
TRD0/RG13
E10
SS1/IC2/RD9
A4
PMD0/RE0
E11
AETXCLK/SCL1/INT3/RA14
A5
PMD8/RG0
F1
MCLR
A6
ETXD0/PMD10/RF1
F2
ERXDV/AERXDV/ECRSDV/AECRSDV//SCL2A/SDO2A/
U2ATX/PMA3/CN10/RG8
A7
VDD
F3
ERXCLK/AERXCLK/EREFCLK/AEREFCLK//SS2A/U2BRX/
U2ACTS/PMA2/CN11/RG9
ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
A8
VSS
F4
A9
ETXD2/IC5/PMD12/RD12
F5
VSS
A10
OC3/RD2
F6
No Connect (NC)
A11
OC2/RD1
F7
No Connect (NC)
B1
No Connect (NC)
F8
VDD
B2
AERXERR/RG15
F9
OSC1/CLKI/RC12
B3
PMD2/RE2
F10
VSS
B4
PMD1/RE1
F11
OSC2/CLKO/RC15
B5
TRD3/RA7
G1
AERXD0/INT1/RE8
B6
ETXD1/PMD11/RF0
G2
AERXD1/INT2/RE9
B7
VCAP/VDDCORE
G3
TMS/RA0
B8
PMRD/CN14/RD5
G4
No Connect (NC)
B9
OC4/RD3
G5
VDD
B10
VSS
G6
VSS
B11
SOSCO/T1CK/CN0/RC14
G7
VSS
C1
PMD6/RE6
G8
No Connect (NC)
C2
VDD
G9
TDO/RA5
C3
TRD1/RG12
G10
SDA2/RA3
C4
TRD2/RG14
G11
TDI/RA4
C5
TRCLK/RA6
H1
AN5/C1IN+/VBUSON/CN7/RB5
C6
No Connect (NC)
H2
AN4/C1IN-/CN6/RB4
C7
ETXCLK/PMD15/CN16/RD7
H3
VSS
C8
OC5/PMWR/CN13/RD4
H4
VDD
C9
VDD
H5
No Connect (NC)
C10
SOSCI/CN1/RC13
H6
VDD
C11
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
H7
No Connect (NC)
D1
T2CK/RC1
H8
VBUS
D2
PMD7/RE7
H9
VUSB
D3
PMD5/RE5
H10
D+/RG2
D4
VSS
H11
SCL2/RA2
D5
VSS
J1
AN3/C2IN+/CN5/RB3
D6
No Connect (NC)
J2
AN2/C2IN-/CN4/RB2
D7
ETXEN/PMD14/CN15/RD6
J3
PGED2/AN7/RB7
D8
ETXD3/PMD13/CN19/RD13
J4
AVDD
D9
SDO1/OC1/INT0/RD0
J5
AN11/ERXERR/AETXERR/PMA12/RB11
D10
No Connect (NC)
J6
TCK/RA1
D11
SCK1/IC3/PMCS2/PMA15/RD10
J7
AN12/ERXD0/AECRS/PMA11/RB12
E1
T5CK/SDI1/RC4
J8
No Connect (NC)
E2
T4CK/RC3
J9
No Connect (NC)
E3
ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
J10
SCL1A/SDO1A/U1ATX/RF8
E4
T3CK/RC2
J11
D-/RG3
E5
VDD
K1
PGEC1/AN1/CN3/RB1
E6
EXTERR/PMD9/RG1
K2
PGED1/AN0/CN2/RB0
E7
VSS
K3
VREF+/CVREF+/AERXD3/PMA6/RA10
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 17
PIC32MX5XX/6XX/7XX
TABLE 3:
PIN NAMES: PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
K4
AN8/C1OUT/RB8
L3
AVSS
K5
No Connect (NC)
L4
AN9/C2OUT/RB9
K6
SS3A/U3BRX/U3ACTS/RF12
L5
AN10/CVREFOUT/PMA13/RB10
K7
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
L6
SCK3A/U3BTX/U3ARTS/RF13
K8
VDD
L7
AN13/ERXD1/AECOL/PMA10/RB13
K9
AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15
L8
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
K10
USBID/RF3
L9
AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14
K11
SDA1A/SDI1A/U1ARX/RF2
L10
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
L1
PGEC2/AN6/OCFA/RB6
L11
SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
L2
VREF-/CVREF-/AERXD2/PMA7/RA9
DS61156C-page 18
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 4:
PIN NAMES: PIC32MX775F256L, PIC32MX775F512L, PIC32MX795F512L AND DEVICES
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
A1
PMD4/RE4
E8
AETXEN/SDA1/INT4/RA15
A2
PMD3/RE3
E9
RTCC/EMDIO/AEMDIO/IC1/RD8
A3
TRD0/RG13
E10
SS1/IC2/RD9
A4
PMD0/RE0
E11
AETXCLK/SCL1/INT3/RA14
A5
C2RX/PMD8/RG0
F1
MCLR
A6
C1TX/ETXD0/PMD10/RF1
F2
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/
U2ATX/PMA3/CN10/RG8
A7
VDD
F3
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/
U2ACTS/PMA2/CN11/RG9
A8
VSS
F4
ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
A9
ETXD2/IC5/PMD12/RD12
F5
VSS
A10
OC3/RD2
F6
No Connect (NC)
A11
OC2/RD1
F7
No Connect (NC)
B1
No Connect (NC)
F8
VDD
B2
AERXERR/RG15
F9
OSC1/CLKI/RC12
B3
PMD2/RE2
F10
VSS
B4
PMD1/RE1
F11
OSC2/CLKO/RC15
B5
TRD3/RA7
G1
AERXD0/INT1/RE8
B6
C1RX/ETXD1/PMD11/RF0
G2
AERXD1/INT2/RE9
B7
VCAP/VDDCORE
G3
TMS/RA0
B8
PMRD/CN14/RD5
G4
No Connect (NC)
B9
OC4/RD3
G5
VDD
B10
VSS
G6
VSS
B11
SOSCO/T1CK/CN0/RC14
G7
VSS
C1
PMD6/RE6
G8
No Connect (NC)
TDO/RA5
C2
VDD
G9
C3
TRD1/RG12
G10
SDA2/RA3
C4
TRD2/RG14
G11
TDI/RA4
C5
TRCLK/RA6
H1
AN5/C1IN+/VBUSON/CN7/RB5
C6
No Connect (NC)
H2
AN4/C1IN-/CN6/RB4
C7
ETXCLK/PMD15/CN16/RD7
H3
VSS
C8
OC5/PMWR/CN13/RD4
H4
VDD
No Connect (NC)
C9
VDD
H5
C10
SOSCI/CN1/RC13
H6
VDD
C11
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
H7
No Connect (NC)
VBUS
D1
T2CK/RC1
H8
D2
PMD7/RE7
H9
VUSB
D3
PMD5/RE5
H10
D+/RG2
SCL2/RA2
D4
VSS
H11
D5
VSS
J1
AN3/C2IN+/CN5/RB3
D6
No Connect (NC)
J2
AN2/C2IN-/CN4/RB2
D7
ETXEN/PMD14/CN15/RD6
J3
PGED2/AN7/RB7
D8
ETXD3/PMD13/CN19/RD13
J4
AVDD
D9
SDO1/OC1/INT0/RD0
J5
AN11/ERXERR/AETXERR/PMA12/RB11
D10
No Connect (NC)
J6
TCK/RA1
D11
SCK1/IC3/PMCS2/PMA15/RD10
J7
AN12/ERXD0/AECRS/PMA11/RB12
E1
T5CK/SDI1/RC4
J8
No Connect (NC)
E2
T4CK/AC2RX/RC3
J9
No Connect (NC)
E3
ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
J10
SCL1A/SDO1A/U1ATX/RF8
E4
T3CK/AC2TX/RC2
J11
D-/RG3
E5
VDD
K1
PGEC1/AN1/CN3/RB1
E6
C2TX/EXTERR/PMD9/RG1
K2
PGED1/AN0/CN2/RB0
E7
VSS
K3
VREF+/CVREF+/AERXD3/PMA6/RA10
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 19
PIC32MX5XX/6XX/7XX
TABLE 4:
PIN NAMES: PIC32MX775F256L, PIC32MX775F512L, PIC32MX795F512L AND DEVICES
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
K4
AN8/C1OUT/RB8
L3
AVSS
K5
No Connect (NC)
L4
AN9/C2OUT/RB9
K6
AC1RX/SS3A/U3BRX/U3ACTS/RF12
L5
AN10/CVREFOUT/PMA13/RB10
K7
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
L6
AC1TX/SCK3A/U3BTX/U3ARTS/RF13
K8
VDD
L7
AN13/ERXD1/AECOL/PMA10/RB13
K9
AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15
L8
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
K10
USBID/RF3
L9
AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14
K11
SDA1A/SDI1A/U1ARX/RF2
L10
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
L1
PGEC2/AN6/OCFA/RB6
L11
SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
L2
VREF-/CVREF-/AERXD2/PMA7/RA9
DS61156C-page 20
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
19.0
20.0
21.0
22.0
23.0
24.0
25.0
26.0
27.0
28.0
29.0
30.0
31.0
32.0
Device Overview ........................................................................................................................................................................ 23
Guidelines for Getting Started with 32-Bit Microcontrollers........................................................................................................ 35
PIC32MX MCU........................................................................................................................................................................... 39
Memory Organization ................................................................................................................................................................. 45
Flash Program Memory............................................................................................................................................................ 105
Resets ...................................................................................................................................................................................... 107
Interrupt Controller ................................................................................................................................................................... 109
Oscillator Configuration ............................................................................................................................................................ 113
Prefetch Cache......................................................................................................................................................................... 115
Direct Memory Access (DMA) Controller ................................................................................................................................ 117
USB On-The-Go (OTG)............................................................................................................................................................ 119
I/O Ports ................................................................................................................................................................................... 121
Timer1 ...................................................................................................................................................................................... 123
Timer2/3, Timer4/5 ................................................................................................................................................................... 125
Input Capture............................................................................................................................................................................ 127
Output Compare....................................................................................................................................................................... 129
Serial Peripheral Interface (SPI)............................................................................................................................................... 131
Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 133
Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 135
Parallel Master Port (PMP) ...................................................................................................................................................... 137
Real-Time Clock and Calendar (RTCC)................................................................................................................................... 139
10-Bit Analog-to-Digital Converter (ADC)................................................................................................................................. 141
Controller Area Network (CAN) ................................................................................................................................................ 143
Ethernet Controller ................................................................................................................................................................... 145
Comparator .............................................................................................................................................................................. 147
Comparator Voltage Reference (CVref) ................................................................................................................................... 149
Power-Saving Features ........................................................................................................................................................... 151
Special Features ...................................................................................................................................................................... 153
Instruction Set .......................................................................................................................................................................... 165
Development Support............................................................................................................................................................... 167
Electrical Characteristics .......................................................................................................................................................... 171
Packaging Information.............................................................................................................................................................. 213
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 21
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 22
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
1.0
DEVICE OVERVIEW
This document contains device-specific information for
PIC32MX5XX/6XX/7XX devices.
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“PIC32MX Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
Figure 1-1 shows a general block diagram of the core
and peripheral modules in the PIC32MX5XX/6XX/7XX
family of devices.
Table 1-1 lists the functions of the various pins shown
in the pinout diagrams.
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
BLOCK DIAGRAM(1,2)
FIGURE 1-1:
OSC2/CLKO
OSC1/CLKI
VCAP/VDDCORE
OSC/SOSC
Oscillators
Power-up
Timer
FRC/LPRC
Oscillators
Voltage
Regulator
PLL
Oscillator
Start-up Timer
PLL-USB
Watchdog
Timer
USBCLK
SYSCLK
PBCLK
Timing
Generation
Brown-out
Reset
Peripheral Bus Clocked by SYSCLK
CN1-22
PORTA
PORTC
IS
32
DS
32
32
32
32
32
32
32
32
PORTD
Bus Matrix
32
32
IC1-5
SPI1,1A,2A,3A
I2C1,2,1A,
2A,3A
32
PORTE
Prefetch
Module
PWM
OC1-5
Peripheral Bus Clocked by PBCLK
USB
MIPS32® M4K™
CPU Core
ICD
INT
PORTB
DMAC
EJTAG
Timer1-5
ETHERNET
Priority
Interrupt
Controller
CAN1, CAN2
JTAG
BSCAN
MCLR
Power-on
Reset
Precision
Band Gap
Reference
Dividers
VDD, VSS
32
Data RAM
Peripheral Bridge
PMP
10-Bit ADC
PORTF
128-Bit Wide
Program Flash Memory
PORTG
Flash
Controller
128
UART1A,1B,2A,
2B,3A,3B
RTCC
Comparators
Note
1:
2:
Some features are not available on all device variants.
BOR functionality is provided when the on-board voltage regulator is enabled.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 23
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin Number(1)
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
Pin
Type
Buffer
Type
AN0
16
25
K2
I
Analog
AN1
15
24
K1
I
Analog
AN2
14
23
J2
I
Analog
AN3
13
22
J1
I
Analog
AN4
12
21
H2
I
Analog
AN5
11
20
H1
I
Analog
AN6
17
26
L1
I
Analog
AN7
18
27
J3
I
Analog
AN8
21
32
K4
I
Analog
AN9
22
33
L4
I
Analog
AN10
23
34
L5
I
Analog
AN11
24
35
J5
I
Analog
AN12
27
41
J7
I
Analog
AN13
28
42
L7
I
Analog
AN14
29
43
K7
I
Analog
AN15
30
44
L8
I
Analog
CLKI
39
63
F9
I
CLKO
40
64
F11
O
OSC1
39
63
F9
I
OSC2
40
64
F11
I/O
SOSCI
47
73
C10
I
SOSCO
48
74
B11
O
Description
Analog input channels.
ST/CMOS External clock source input. Always associated
with OSC1 pin function.
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode. Optionally
functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
ST/CMOS Oscillator crystal input. ST buffer when
configured in RC mode; CMOS otherwise.
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode. Optionally
functions as CLKO in RC and EC modes.
ST/CMOS 32.768 kHz low-power oscillator crystal input;
CMOS otherwise.
—
32.768 kHz low-power oscillator crystal output.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
DS61156C-page 24
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
121-Pin
XBGA
Pin
Type
Buffer
Type
64-Pin
QFN/TQFP
100-Pin
TQFP
CN0
48
74
B11
I
ST
CN1
47
73
C10
I
ST
CN2
16
25
K2
I
ST
CN3
15
24
K1
I
ST
CN4
14
23
J2
I
ST
CN5
13
22
J1
I
ST
CN6
12
21
H2
I
ST
CN7
11
20
H1
I
ST
CN8
4
10
E3
I
ST
CN9
5
11
F4
I
ST
CN10
6
12
F2
I
ST
CN11
8
14
F3
I
ST
CN12
30
44
L8
I
ST
CN13
52
81
C8
I
ST
CN14
53
82
B8
I
ST
CN15
54
83
D7
I
ST
CN16
55
84
C7
I
ST
CN17
31
49
L10
I
ST
CN18
32
50
L11
I
ST
CN19
—
80
D8
I
ST
CN20
—
47
L9
I
ST
CN21
—
48
K9
I
ST
IC1
42
68
E9
I
ST
IC2
43
69
E10
I
ST
IC3
44
70
D11
I
ST
IC4
45
71
C11
I
ST
Description
Change notification inputs.
Can be software programmed for internal weak
pull-ups on all inputs.
Capture Inputs 1-5.
IC5
52
79
A9
I
ST
OCFA
17
26
L1
I
ST
Output Compare Fault A input.
OC1
46
72
D9
O
—
Output Compare Output 1.
OC2
49
76
A11
O
—
Output Compare Output 2
OC3
50
77
A10
O
—
Output Compare Output 3.
OC4
51
78
B9
O
—
Output Compare Output 4.
OC5
52
81
C8
O
—
Output Compare Output 5.
OCFB
30
44
L8
I
ST
Output Compare Fault B input.
INT0
46
72
D9
I
ST
External Interrupt 0.
INT1
42
18
G1
I
ST
External Interrupt 1.
INT2
43
19
G2
I
ST
External Interrupt 2.
INT3
44
66
E11
I
ST
External Interrupt 3.
INT4
45
67
E8
I
ST
External Interrupt 4.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 25
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
Pin
Type
Buffer
Type
RA0
—
17
G3
I/O
ST
RA1
—
38
J6
I/O
ST
RA2
—
58
H11
I/O
ST
RA3
—
59
G10
I/O
ST
RA4
—
60
G11
I/O
ST
RA5
—
61
G9
I/O
ST
RA6
—
91
C5
I/O
ST
RA7
—
92
B5
I/O
ST
RA9
—
28
L2
I/O
ST
RA10
—
29
K3
I/O
ST
RA14
—
66
E11
I/O
ST
RA15
—
67
E8
I/O
ST
RB0
16
25
K2
I/O
ST
RB1
15
24
K1
I/O
ST
RB2
14
23
J2
I/O
ST
RB3
13
22
J1
I/O
ST
RB4
12
21
H2
I/O
ST
RB5
11
20
H1
I/O
ST
RB6
17
26
L1
I/O
ST
RB7
18
27
J3
I/O
ST
RB8
21
32
K4
I/O
ST
RB9
22
33
L4
I/O
ST
RB10
23
34
L5
I/O
ST
RB11
24
35
J5
I/O
ST
RB12
27
41
J7
I/O
ST
RB13
28
42
L7
I/O
ST
RB14
29
43
K7
I/O
ST
RB15
30
44
L8
I/O
ST
RC1
—
6
D1
I/O
ST
RC2
—
7
E4
I/O
ST
RC3
—
8
E2
I/O
ST
RC4
—
9
E1
I/O
ST
RC12
39
63
F9
I/O
ST
RC13
47
73
C10
I/O
ST
RC14
48
74
B11
I/O
ST
RC15
40
64
F11
I/O
ST
Description
PORTA is a bidirectional I/O port.
PORTB is a bidirectional I/O port.
PORTC is a bidirectional I/O port.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
DS61156C-page 26
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
121-Pin
XBGA
Pin
Type
Buffer
Type
64-Pin
QFN/TQFP
100-Pin
TQFP
RD0
46
72
D9
I/O
ST
RD1
49
76
A11
I/O
ST
RD2
50
77
A10
I/O
ST
RD3
51
78
B9
I/O
ST
RD4
52
81
C8
I/O
ST
RD5
53
82
B8
I/O
ST
RD6
54
83
D7
I/O
ST
RD7
55
84
C7
I/O
ST
RD8
42
68
E9
I/O
ST
RD9
43
69
E10
I/O
ST
RD10
44
70
D11
I/O
ST
RD11
45
71
C11
I/O
ST
RD12
—
79
A9
I/O
ST
RD13
—
80
D8
I/O
ST
RD14
—
47
L9
I/O
ST
RD15
—
48
K9
I/O
ST
RE0
60
93
A4
I/O
ST
RE1
61
94
B4
I/O
ST
RE2
62
98
B3
I/O
ST
RE3
63
99
A2
I/O
ST
RE4
64
100
A1
I/O
ST
RE5
1
3
D3
I/O
ST
RE6
2
4
C1
I/O
ST
RE7
3
5
D2
I/O
ST
RE8
—
18
G1
I/O
ST
RE9
—
19
G2
I/O
ST
RF0
58
87
B6
I/O
ST
RF1
59
88
A6
I/O
ST
RF2
—
52
K11
I/O
ST
RF3
33
51
K10
I/O
ST
RF4
31
49
L10
I/O
ST
RF5
32
50
L11
I/O
ST
RF8
—
53
J10
I/O
ST
RF12
—
40
K6
I/O
ST
RF13
—
39
L6
I/O
ST
Description
PORTD is a bidirectional I/O port.
PORTE is a bidirectional I/O port.
PORTF is a bidirectional I/O port.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 27
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
Pin
Type
Buffer
Type
Description
RG0
—
90
A5
I/O
ST
RG1
—
89
E6
I/O
ST
PORTG is a bidirectional I/O port.
RG6
4
10
E3
I/O
ST
RG7
5
11
F4
I/O
ST
RG8
6
12
F2
I/O
ST
RG9
8
14
F3
I/O
ST
RG12
—
96
C3
I/O
ST
RG13
—
97
A3
I/O
ST
RG14
—
95
C4
I/O
ST
RG15
—
1
B2
I/O
ST
RG2
37
57
H10
I
ST
RG3
36
56
J11
I
ST
T1CK
48
74
B11
I
ST
Timer1 external clock input.
T2CK
—
6
D1
I
ST
Timer2 external clock input.
T3CK
—
7
E4
I
ST
Timer3 external clock input.
T4CK
—
8
E2
I
ST
Timer4 external clock input.
PORTG input pins.
T5CK
—
9
E1
I
ST
Timer5 external clock input.
U1ACTS
43
47
L9
I
ST
UART1A clear to send.
U1ARTS
49
48
K9
O
—
UART1A ready to send.
U1ARX
50
52
K11
I
ST
UART1A receive.
U1ATX
51
53
J10
O
—
UART1A transmit.
U2ACTS
8
14
F3
I
ST
UART2A clear to send.
U2ARTS
4
10
E3
O
—
UART2A ready to send.
U2ARX
5
11
F4
I
ST
UART2A receive.
U2ATX
6
12
F2
O
—
UART2A transmit.
U3ACTS
21
40
K6
I
ST
UART3A clear to send.
U3ARTS
29
39
L6
O
—
UART3A ready to send.
U3ARX
31
49
L10
I
ST
UART3A receive.
U3ATX
32
50
L11
O
—
UART3A transmit.
U1BRX
43
47
L9
I
ST
UART1B receive.
U1BTX
49
48
K9
O
—
UART1B transmit.
ST
UART2B receive.
U2BRX
8
14
F3
I
U2BTX
4
10
E3
O
—
UART2B transmit.
U3BRX
21
40
K6
I
ST
UART3B receive.
U3BTX
29
39
L6
O
—
UART3B transmit.
SCK1
—
70
D11
I/O
ST
Synchronous serial clock input/output for SPI1.
SDI1
—
9
E1
I
ST
SPI1 data in.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
DS61156C-page 28
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
121-Pin
XBGA
Pin
Type
Buffer
Type
Description
64-Pin
QFN/TQFP
100-Pin
TQFP
SDO1
—
72
D9
O
—
SPI1 data out.
SS1
—
69
E10
I/O
ST
SPI1 slave synchronization or frame pulse I/O.
SCK1A
49
48
K9
I/O
ST
Synchronous serial clock input/output for
SPI1A.
SDI1A
50
52
K11
I
ST
SPI1A data in.
SDO1A
51
53
J10
O
—
SPI1A data out.
SS1A
43
47
L9
I/O
ST
SPI1A slave synchronization or frame pulse
I/O.
SCK2A
4
10
E3
I/O
ST
Synchronous serial clock input/output for
SPI2A.
SDI2A
5
11
F4
I
ST
SPI2A data in.
SDO2A
6
12
F2
O
—
SPI2A data out.
SS2A
8
14
F3
I/O
ST
SPI2A slave synchronization or frame pulse
I/O.
SCK3A
29
39
L6
I/O
ST
Synchronous serial clock input/output for
SPI3A.
SDI3A
31
49
L10
I
ST
SPI3A data in.
SDO3A
32
50
L11
O
—
SPI3A data out.
SS3A
21
40
K6
I/O
ST
SPI3A slave synchronization or frame pulse
I/O.
SCL1
44
66
E11
I/O
ST
Synchronous serial clock input/output for I2C1.
SDA1
43
67
E8
I/O
ST
Synchronous serial data input/output for I2C1.
SCL1A
51
53
J10
I/O
ST
Synchronous serial clock input/output for
I2C1A.
SDA1A
50
52
K11
I/O
ST
Synchronous serial data input/output for
I2C1A.
SCL2
—
58
H11
I/O
ST
Synchronous serial clock input/output for I2C2.
SDA2
—
59
G10
I/O
ST
Synchronous serial data input/output for I2C2.
SCL2A
6
12
F2
I/O
ST
Synchronous serial clock input/output for
I2C2A.
SDA2A
5
11
F4
I/O
ST
Synchronous serial data input/output for
I2C2A.
SCL3A
32
50
L11
I/O
ST
Synchronous serial clock input/output for
I2C3A.
SDA3A
31
49
L10
I/O
ST
Synchronous serial data input/output for
I2C3A.
TMS
23
17
G3
I
ST
JTAG Test mode select pin.
TCK
27
38
J6
I
ST
JTAG test clock input pin.
TDI
28
60
G11
I
ST
JTAG test data input pin.
TDO
24
61
G9
O
—
JTAG test data output pin.
RTCC
42
68
E9
O
—
Real-Time Clock alarm output.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 29
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
Pin
Type
Buffer
Type
Description
CVREF-
15
28
L2
I
Analog
Comparator Voltage Reference (low).
CVREF+
16
29
K3
I
Analog
Comparator Voltage Reference (high).
CVREFOUT
23
34
L5
O
Analog
Comparator Voltage Reference output.
C1IN-
12
21
H2
I
Analog
Comparator 1 negative input.
C1IN+
11
20
H1
I
Analog
C1OUT
21
32
K4
O
—
Comparator 1 positive input.
Comparator 1 output.
C2IN-
14
23
J2
I
Analog
Comparator 2 negative input.
C2IN+
13
22
J1
I
Analog
Comparator 2 positive input.
C2OUT
22
33
L4
O
—
PMA0
—
44
L8
I/O
TTL/ST
Parallel Master Port Address Bit 0 input
(Buffered Slave modes) and output (Master
modes).
PMA1
—
43
K7
I/O
TTL/ST
Parallel Master Port Address Bit 1 input
(Buffered Slave modes) and output (Master
modes).
Parallel Master Port address (Demultiplexed
Master modes).
PMA2
8
14
F3
O
—
PMA3
6
12
F2
O
—
PMA4
5
11
F4
O
—
PMA5
4
10
E3
O
—
PMA6
16
29
K3
O
—
PMA7
22
28
L2
O
—
PMA8
32
50
L11
O
—
PMA9
31
49
L10
O
—
PMA10
28
42
L7
O
—
PMA11
27
41
J7
O
—
PMA12
24
35
J5
O
—
PMA13
23
34
L5
O
—
PMA14
45
71
C11
O
—
Comparator 2 output.
PMA15
44
70
D11
O
—
PMCS1
45
71
C11
O
—
Parallel Master Port Chip Select 1 strobe.
PMCS2
44
70
D11
O
—
Parallel Master Port Chip Select 2 strobe.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
DS61156C-page 30
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
Pin
Type
Buffer
Type
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
PMD0
60
93
A4
I/O
TTL/ST
PMD1
61
94
B4
I/O
TTL/ST
PMD2
62
98
B3
I/O
TTL/ST
PMD3
63
99
A2
I/O
TTL/ST
PMD4
64
100
A1
I/O
TTL/ST
PMD5
1
3
D3
I/O
TTL/ST
PMD6
2
4
C1
I/O
TTL/ST
PMD7
3
5
D2
I/O
TTL/ST
PMD8
—
90
A5
I/O
TTL/ST
PMD9
—
89
E6
I/O
TTL/ST
PMD10
—
88
A6
I/O
TTL/ST
PMD11
—
87
B6
I/O
TTL/ST
Description
Parallel Master Port data (Demultiplexed
Master mode) or address/data (Multiplexed
Master modes).
PMD12
—
79
A9
I/O
TTL/ST
PMD13
—
80
D8
I/O
TTL/ST
PMD14
—
83
D7
I/O
TTL/ST
PMD15
—
84
C7
I/O
TTL/ST
PMALL
30
44
L8
O
—
Parallel Master Port address latch enable
low byte (Multiplexed Master modes).
PMALH
29
43
K7
O
—
Parallel Master Port address latch enable
high byte (Multiplexed Master modes).
PMRD
53
82
B8
O
—
Parallel Master Port read strobe.
PMWR
52
81
C8
O
—
Parallel Master Port write strobe.
VBUS
34
54
H8
I
Analog
VUSB
35
55
H9
P
—
USB internal transceiver supply.
VBUSON
11
20
H1
O
—
USB Host and OTG bus power control output.
D+
37
57
H10
I/O
Analog
USB D+.
D-
36
56
J11
I/O
Analog
USB D-.
USBID
33
51
K10
I
ST
USB OTG ID detect.
C1RX
58
87
B6
I
ST
CAN1 bus receive pin.
C1TX
59
88
A6
O
—
CAN1 bus transmit pin.
AC1RX
32
40
K6
I
ST
Alternate CAN1 bus receive pin.
USB bus power monitor.
AC1TX
31
39
L6
O
—
Alternate CAN1 bus transmit pin.
C2RX
29
90
A5
I
ST
CAN2 bus receive pin.
C2TX
21
89
E6
O
—
CAN2 bus transmit pin.
AC2RX
—
8
E2
1
ST
Alternate CAN2 bus receive pin.
AC2TX
—
7
E4
O
—
Alternate CAN2 bus transmit pin.
ERXD0
61
41
J7
I
ST
Ethernet Receive Data 0.(2)
ERXD1
60
42
L7
I
ST
Ethernet Receive Data 1.(2)
ERXD2
59
43
K7
I
ST
Ethernet Receive Data 2.(2)
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 31
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
L8
I
ST
Ethernet Receive Data 3.(2)
35
J5
I
ST
Ethernet receive error input.(2)
62
12
F2
I
ST
Ethernet receive data valid.(2)
ECRSDV
61
12
F2
I
ST
Ethernet carrier sense data valid.(2)
ERXCLK
63
14
F3
I
ST
Ethernet receive clock.(2)
EREFCLK
63
14
F3
I
ST
Ethernet reference clock.(2)
ETXD0
2
88
A6
O
—
Ethernet Transmit Data 0.(2)
ETXD1
3
87
B6
O
—
Ethernet Transmit Data 1.(2)
ETXD2
43
79
A9
O
—
Ethernet Transmit Data 2.(2)
ETXD3
42
80
D8
O
—
Ethernet Transmit Data 3.(2)
ETXERR
54
89
E6
O
—
Ethernet transmit error.(2)
ETXEN
1
83
D7
O
—
Ethernet transmit enable.(2)
ETXCLK
55
84
C7
I
ST
Ethernet transmit clock.(2)
ECOL
44
10
E3
I
ST
Ethernet collision detect.(2)
ECRS
45
11
F4
I
ST
Ethernet carrier sense.(2)
EMDC
30
71
C11
O
—
Ethernet management data clock.(2)
EMDIO
49
68
E9
I/O
—
Ethernet management data.(2)
AERXD0
43
18
G1
I
ST
Alternate Ethernet Receive Data 0.(2)
AERXD1
42
19
G2
I
ST
Alternate Ethernet Receive Data 1.(2)
AERXD2
—
28
L2
I
ST
Alternate Ethernet Receive Data 2.(2)
AERXD3
—
29
K3
I
ST
Alternate Ethernet Receive Data 3.(2)
AERXERR
55
1
B2
I
ST
Alternate Ethernet receive error input.(2)
AERXDV
44
—
—
I
ST
Alternate Ethernet receive data valid.(2)
AECRSDV
44
—
—
I
ST
Alternate Ethernet carrier sense data valid.(2)
AERXCLK
45
—
—
I
ST
Alternate Ethernet receive clock.(2)
AEREFCLK
45
—
—
I
ST
Alternate Ethernet reference clock.(2)
AETXD0
59
47
L9
O
—
Alternate Ethernet Transmit Data 0.(2)
AETXD1
58
48
K9
O
—
Alternate Ethernet Transmit Data 1.(2)
AETXD2
—
44
L8
O
—
Alternate Ethernet Transmit Data 2.(2)
AETXD3
—
43
K7
O
—
Alternate Ethernet Transmit Data 3.(2)
AETXERR
—
35
J5
O
—
Alternate Ethernet transmit error.(2)
AETXEN
54
67
E8
O
—
Alternate Ethernet transmit enable.(2)
AETXCLK
—
66
E11
I
ST
Alternate Ethernet transmit clock.(2)
AECOL
—
42
L7
I
ST
Alternate Ethernet collision detect.(2)
AECRS
—
41
J7
I
ST
Alternate Ethernet carrier sense.(2)
TRCLK
—
91
C5
O
—
Trace clock.
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
ERXD3
58
44
ERXERR
64
ERXDV
Description
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
DS61156C-page 32
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
Buffer
Type
Description
100-Pin
TQFP
TRD0
—
97
A3
O
—
TRD1
—
96
C3
O
—
TRD2
—
95
C4
O
—
TRD3
—
92
B5
O
—
PGED1
16
25
K2
I/O
ST
Data I/O pin for Programming/Debugging
Communication Channel 1.
PGEC1
15
24
K1
I
ST
Clock input pin for Programming/Debugging
Communication Channel 1.
PGED2
18
27
J3
I/O
ST
Data I/O pin for Programming/Debugging
Communication Channel 2.
PGEC2
17
26
L1
I
ST
Clock input pin for Programming/Debugging
Communication Channel 2.
MCLR
7
13
F1
I/P
ST
Master Clear (Reset) input. This pin is an
active-low Reset to the device.
AVDD
19
30
J4
P
P
Positive supply for analog modules. This pin
must be connected at all times.
AVSS
20
31
L3
P
P
Ground reference for analog modules.
A7, C2,
C9, E5,
K8, F8,
G5, H4, H6
P
—
Positive supply for peripheral logic and I/O
pins.
VDD
VCAP/
VDDCORE
10, 26, 38, 2, 16, 37,
57
46, 62, 86
121-Pin
XBGA
Pin
Type
64-Pin
QFN/TQFP
Trace Data Bits 0-3.
56
85
B7
P
—
CPU logic filter capacitor connection.
9, 25, 41
15, 36, 45,
65, 75
A8, B10,
D4, D5,
E7, F5,
F10, G6,
G7, H3
P
—
Ground reference for logic and I/O pins. This
pin must be connected at all times.
VREF+
16
29
K3
I
Analog
Analog voltage reference (high) input.
VREF-
15
28
L2
I
Analog
Analog voltage reference (low) input.
VSS
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 33
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 34
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
2.0
GUIDELINES FOR GETTING
STARTED WITH 32-BIT
MICROCONTROLLERS
2.2
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32)
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
2.1
Basic Connection Requirements
Getting started with the PIC32MX5XX/6XX/7XX family
of 32-bit Microcontrollers (MCU) requires attention to a
minimal set of device pin connections before proceeding with development. The following is a list of pin
names, which must always be connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins–even if the ADC module
is not used
(see Section 2.2 “Decoupling Capacitors”)
• VCAP/VDDCORE pin
(see Section 2.3 “Capacitor on Internal
Voltage Regulator (VCAP/VDDCORE)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins–used for In-Circuit Serial
Programming (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins–when external oscillator
source is used
(see Section 2.8 “External Oscillator Pins”)
Decoupling Capacitors
The use of decoupling capacitors on power supply
pins, such as VDD, VSS, AVDD and AVSS is required.
See Figure 2-1.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A value of 0.1 µF
(100 nF), 10-20V is recommended. The capacitor
should be a low Equivalent Series Resistance
(low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is
further recommended that ceramic capacitors be
used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended that
the capacitors be placed on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within onequarter inch (6 mm) in length.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
The following pin may be required, as well:
VREF+/VREF- pins–used when external voltage reference for ADC module is implemented
Note:
The AVDD and AVSS pins must be
connected, regardless of ADC use and the
ADC voltage reference source.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 35
PIC32MX5XX/6XX/7XX
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
CBP
R1
MCLR
C
VDD
VCAP/VDDCORE
R
PIC32MX
VSS
10 
2.2.1
VDD
0.1 µF
Ceramic
CBP
VSS
VDD
AVSS
VDD
AVDD
0.1 µF
Ceramic
CBP
VSS
0.1 µF
Ceramic
CBP
0.1 µF
Ceramic
CBP
2.3.1
The MCLR pin provides for two specific device
functions:
Pulling The MCLR pin low generates a device Reset.
Figure 2-2 shows a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
BULK CAPACITORS
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.
2.3
Master Clear (MCLR) Pin
• Device Reset
• Device programming and debugging
VSS
CEFC
VDD
2.4
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
Capacitor on Internal Voltage
Regulator (VCAP/VDDCORE)
R
R1
INTERNAL REGULATOR MODE
A low-ESR (1 ohm) capacitor is required on the
VCAP/VDDCORE pin, which is used to stabilize the internal voltage regulator output. The VCAP/VDDCORE pin
must not be connected to VDD, and must have a CEFC
capacitor, with at least a 6V rating, connected to
ground. The type can be ceramic or tantalum. Refer to
Section 31.0 "Electrical Characteristics" for
additional information on CEFC specifications.
DS61156C-page 36
JP
MCLR
PIC32MX
C
Note 1:
R  10 k is recommended. A suggested
starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
2:
R1  470 will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
3:
The capacitor can be sized to prevent unintentional Resets from brief glitches or to extend
the device Reset period during POR.
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
2.5
ICSP Pins
2.6
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 2, MPLAB ICD 3, or MPLAB REAL
ICE™.
For more information on ICD 2, ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web
site.
• “MPLAB® ICD 2 In-Circuit Debugger User's
Guide” DS51331
• “Using MPLAB® ICD 2” (poster) DS51265
• “MPLAB® ICD 2 Design Advisory” DS51566
• “Using MPLAB® ICD 3” (poster) DS51765
• “MPLAB® ICD 3 Design Advisory” DS51764
• “MPLAB® REAL ICE™ In-Circuit Debugger
User's Guide” DS51616
• “Using MPLAB® REAL ICE™ Emulator” (poster)
DS51749
 2010 Microchip Technology Inc.
JTAG
The TMS, TDO, TDI and TCK pins are used for testing
and debugging according to the Joint Test Action
Group (JTAG) standard. It is recommended to keep the
trace length between the JTAG connector and the
JTAG pins on the device as short as possible. If the
JTAG connector is expected to experience an ESD
event, a series resistor is recommended, with the value
in the range of a few tens of Ohms, not to exceed 100
Ohms.
Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended
as they will interfere with the programmer/debugger
communications to the device. If such discrete components are an application requirement, they should be
removed from the circuit during programming and
debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the
respective device Flash programming specification for
information on capacitive loading limits and pin input
voltage high (VIH) and input low (VIL) requirements.
2.7
Trace
The trace pins can be connected to a hardware-traceenabled programmer to provide a compress real time
instruction trace. When used for trace the TRD3,
TRD2, TRD1, TRD0 and TRCLK pins should be dedicated for this use. The trace hardware requires a
22 ohm series resistor between the trace pins and the
trace connector.
Preliminary
DS61156C-page 37
PIC32MX5XX/6XX/7XX
2.8
External Oscillator Pins
2.9
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 "Oscillator
Configuration" for details).
The oscillator circuit should be placed on the same side
of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The
load capacitors should be placed next to the oscillator
itself, on the same side of the board. Use a grounded
copper pour around the oscillator circuit to isolate them
from surrounding circuits. The grounded copper pour
should be routed directly to the MCU ground. Do not
run any signal traces or power traces inside the ground
pour. Also, if using a two-sided board, avoid any traces
on the other side of the board where the crystal is
placed. A suggested layout is shown in Figure 2-3.
FIGURE 2-3:
SUGGESTED OSCILLATOR
CIRCUIT PLACEMENT
Oscillator
Secondary
Guard Trace
Guard Ring
Main Oscillator
DS61156C-page 38
Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 2, ICD 3, or REAL ICE is selected as a
debugger, it automatically initializes all of the A/D input
pins (ANx) as “digital” pins by setting all bits in the
ADPCFG register.
The bits in this register that correspond to the A/D pins
that are initialized by MPLAB ICD 2, ICD 3, or REAL
ICE, must not be cleared by the user application
firmware; otherwise, communication errors will result
between the debugger and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
ADPCFG register during initialization of the ADC
module.
When MPLAB ICD 2, ICD 3, or REAL ICE is used as a
programmer, the user application firmware must correctly configure the ADPCFG register. Automatic initialization of this register is only done during debugger
operation. Failure to correctly configure the register(s)
will result in all A/D pins being recognized as analog
input pins, resulting in the port value being read as a
logic '0', which may affect user application functionality.
2.10
Unused I/Os
Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
to a logic-low state.
Alternatively, inputs can be reserved by connecting the
pin to VSS through a 1k to 10k resistor and configuring
the pin as an input.
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
PIC32MX MCU
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “MCU”
(DS61113) in the “PIC32MX Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32). Resources
for the MIPS32® M4K® Processor Core
are available at http://www.mips.com.
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The MCU module is the heart of the
PIC32MX5XX/6XX/7XX family processor. The MCU
fetches instructions, decodes each instruction, fetches
source operands, executes each instruction and writes
the results of instruction execution to the proper
destinations.
3.1
•
•
•
•
Features
• 5-Stage Pipeline
• 32-Bit Address and Data Paths
• MIPS32 Enhanced Architecture (Release 2)
- Multiply-Accumulate and Multiply-Subtract
instructions
- Targeted Multiply instruction
- Zero/One Detect instructions
- WAIT instruction
- Conditional Move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
FIGURE 3-1:
•
•
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
for interrupt handlers
- Bit field manipulation instructions
MIPS16e™ Code Compression
- 16-bit encoding of 32-bit instructions to
improve code density
- Special PC-relative instructions for efficient
loading of addresses and constants
- SAVE & RESTORE macro instructions for
setting up and tearing down stack frames
within subroutines
- Improved support for handling 8 and 16-bit
data types
Simple Fixed Mapping Translation (FMT)
mechanism
Simple Dual Bus Interface
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
interrupt latency
Autonomous Multiply/Divide Unit
- Maximum issue rate of one 32x16 multiply
per clock
- Maximum issue rate of one 32x32 multiply
every other clock
- Early-in iterative divide. Minimum 11 and
maximum 33 clock latency (dividend (rs) sign
extension-dependent)
Power Control
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
instruction)
- Extensive use of local gated clocks
EJTAG Debug and Instruction Trace
- Support for single stepping
- Virtual instruction and data address/value
- Breakpoints
- PC tracing with trace compression
MCU BLOCK DIAGRAM
MCU
EJTAG
MDU
Execution
Core
(RF/ALU/Shift)
System
Coprocessor
 2010 Microchip Technology Inc.
Trace
TAP
FMT
Bus Interface
Trace I/F
Off-Chip
Debug I/F
Dual Bus I/F
Bus Matrix
3.0
Power
Management
Preliminary
DS61156C-page 39
PIC32MX5XX/6XX/7XX
3.2
Architecture Overview
3.2.2
The PIC32MX5XX/6XX/7XX family core contains several logic blocks working together in parallel, providing
an efficient high-performance computing engine. The
following blocks are included with the core:
•
•
•
•
•
•
•
•
Execution Unit
Multiply/Divide Unit (MDU)
System Control Coprocessor (CP0)
Fixed Mapping Translation (FMT)
Dual Internal Bus interfaces
Power Management
MIPS16e Support
Enhanced JTAG (EJTAG) Controller
3.2.1
EXECUTION UNIT
The PIC32MX5XX/6XX/7XX family core execution unit
implements a load/store architecture with single-cycle
ALU operations (logical, shift, add, subtract) and an
autonomous multiply/divide unit. The core contains
thirty-two 32-bit General Purpose Registers (GPRs)
used for integer operations and address calculation.
One additional register file shadow set (containing
thirty-two registers) is added to minimize context
switching overhead during interrupt/exception processing. The register file consists of two read ports and one
write port and is fully bypassed to minimize operation
latency in the pipeline.
The execution unit includes:
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
address
• Logic for branch determination and branch target
address calculation
• Load aligner
• Bypass multiplexers used to avoid stalls when
executing instruction streams where data
producing instructions are followed closely by
consumers of their results
• Leading Zero/One detect unit for implementing
the CLZ and CLO instructions
• Arithmetic Logic Unit (ALU) for performing bitwise
logical operations
• Shifter and store aligner
DS61156C-page 40
MULTIPLY/DIVIDE UNIT (MDU)
The PIC32MX5XX/6XX/7XX family core includes a
Multiply/Divide Unit (MDU) that contains a separate
pipeline for multiply and divide operations. This pipeline
operates in parallel with the Integer Unit (IU) pipeline
and does not stall when the IU pipeline stalls. This
allows MDU operations to be partially masked by
system stalls and/or other integer unit instructions.
The high-performance MDU consists of a 32x16 booth
recoded multiplier, result/accumulation registers (HI
and LO), a divide state machine, and the necessary
multiplexers and control logic. The first number shown
(‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
PIC32MX core only checks the value of the latter (rt)
operand to determine how many times the operation
must pass through the multiplier. The 16x16 and 32x16
operations pass through the multiplier once. A 32x32
operation passes through the multiplier twice.
The MDU supports execution of one 16x16 or 32x16
multiply operation every clock cycle; 32x32 multiply
operations can be issued every other clock cycle.
Appropriate interlocks are implemented to stall the
issuance of back-to-back 32x32 multiply operations.
The multiply operand size is automatically determined
by logic built into the MDU.
Divide operations are implemented with a simple 1 bit
per clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand.
If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit
wide rs, 15 iterations are skipped and for a 24-bit wide
rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active
causes an IU pipeline stall until the divide operation is
completed.
Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32MX
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 3-1:
PIC32MX5XX/6XX/7XX FAMILY CORE HIGH-PERFORMANCE INTEGER
MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode
Operand Size (mul rt) (div rs)
Latency
Repeat Rate
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU
16 bits
1
1
32 bits
2
2
MUL
16 bits
2
1
32 bits
3
2
DIV/DIVU
8 bits
12
11
16 bits
19
18
24 bits
26
25
32 bits
33
32
The MIPS architecture defines that the result of a
multiply or divide operation be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be
transferred to the General Purpose Register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction,
MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By
avoiding the explicit MFLO instruction required when
using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive
operations is increased.
3.2.3
SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (Kernel, User and Debug) and
whether interrupts are enabled or disabled. Configuration information, such as presence of options like
MIPS16e, is also available by accessing the CP0
registers, listed in Table 3-2.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 41
PIC32MX5XX/6XX/7XX
TABLE 3-2:
COPROCESSOR 0 REGISTERS
Register
Number
0-6
Register
Name
Function
Reserved
Reserved in the PIC32MX5XX/6XX/7XX family core.
7
HWREna
Enables access via the RDHWR instruction to selected hardware registers.
8
BadVAddr(1)
Reports the address for the most recent address-related exception.
9
Count(1)
Processor cycle count.
10
Reserved
11
Compare
12
Status(1)
(1)
Reserved in the PIC32MX5XX/6XX/7XX family core.
Timer interrupt control.
Processor status and control.
(1)
12
IntCtl
12
SRSCtl(1)
Interrupt system status and control.
Shadow register set status and control.
12
SRSMap(1)
Provides mapping from vectored interrupt to a shadow set.
13
Cause(1)
Cause of last general exception.
(1)
14
EPC
Program counter at last exception.
15
PRId
Processor identification and revision.
15
EBASE
Exception vector base register.
16
Config
Configuration register.
16
Config1
Configuration Register 1.
16
Config2
Configuration Register 2.
16
Config3
Configuration Register 3.
Reserved
Reserved in the PIC32MX5XX/6XX/7XX family core.
17-22
(2)
Debug control and exception status.
23
Debug
24
DEPC(2)
Program counter at last debug exception.
Reserved
Reserved in the PIC32MX5XX/6XX/7XX family core.
ErrorEPC(1)
Program counter at last error.
25-29
30
31
Note 1:
2:
(2)
DESAVE
Debug handler scratchpad register.
Registers used in exception processing.
Registers used during debug.
DS61156C-page 42
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events or program errors. Table 3-3 lists
the exception types in order of priority.
TABLE 3-3:
PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES
Exception
Description
Reset
Assertion MCLR or a Power-on Reset (POR).
DSS
EJTAG debug single step.
DINT
EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
NMI
Assertion of NMI signal.
Interrupt
Assertion of unmasked hardware or software interrupt signal.
DIB
EJTAG debug hardware instruction break matched.
AdEL
Fetch address alignment error.
Fetch reference to protected address.
IBE
Instruction fetch bus error.
DBp
EJTAG breakpoint (execution of SDBBP instruction).
Sys
Execution of SYSCALL instruction.
Bp
Execution of BREAK instruction.
RI
Execution of a reserved instruction.
CpU
Execution of a coprocessor instruction for a coprocessor that is not enabled.
CEU
Execution of a CorExtend instruction when CorExtend is not enabled.
Ov
Execution of an arithmetic instruction that overflowed.
Tr
Execution of a trap (when trap condition is true).
DDBL/DDBS
EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).
AdEL
Load address alignment error.
Load reference to protected address.
AdES
Store address alignment error.
Store to protected address.
DBE
Load or store bus error.
DDBL
EJTAG data hardware breakpoint matched in load data compare.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 43
PIC32MX5XX/6XX/7XX
3.3
Power Management
3.4
The PIC32MX5XX/6XX/7XX family core offers a number
of power management features, including low-power
design, active power management and power-down
modes of operation. The core is a static design that
supports slowing or Halting the clocks, which reduces
system power consumption during Idle periods.
3.3.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 27.0
“Power-Saving Features”.
3.3.2
LOCAL CLOCK GATING
The majority of the power consumed by the
PIC32MX5XX/6XX/7XX family core is in the clock tree
and clocking registers. The PIC32MX family uses
extensive use of local gated clocks to reduce this
dynamic power consumption.
DS61156C-page 44
EJTAG Debug Support
The PIC32MX5XX/6XX/7XX family core provides for
an Enhanced JTAG (EJTAG) interface for use in the
software debug of application and kernel code. In
addition to standard User mode and Kernel modes of
operation, the PIC32MX5XX/6XX/7XX family core provides a Debug mode that is entered after a debug
exception (derived from a hardware breakpoint, singlestep exception, etc.) is taken and continues until a
Debug Exception Return (DERET) instruction is
executed. During this time, the processor executes the
debug exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for transferring
test
data
in
and
out
of
the
PIC32MX5XX/6XX/7XX family core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification define which
registers are selected and how they are used.
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
4.0
Note:
MEMORY ORGANIZATION
4.1
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a comprehensive reference source. For detailed
information, refer to Section 3. “Memory
Organization”
(DS61115)
in
the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB
of unified virtual memory address space. All memory
regions, including program, data memory, SFRs and
Configuration registers, reside in this address space at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, the data memory can
be made executable, allowing PIC32MX5XX/6XX/7XX
devices to execute from data memory.
Key features include:
• 32-bit native data width
• Separate User (KUSEG) and Kernel
(KSEG0/KSEG1) mode address space
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
program space
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
runaway code
• Simple memory mapping with Fixed Mapping
Translation (FMT) unit
• Cacheable (KSEG0) and non-cacheable (KSEG1)
address regions
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX Memory
Layout
PIC32MX5XX/6XX/7XX microcontrollers implement
two address schemes: virtual and physical. All
hardware resources, such as program memory, data
memory and peripherals, are located at their respective
physical addresses. Virtual addresses are exclusively
used by the CPU to fetch and execute instructions as
well as access peripherals. Physical addresses are
used by bus master peripherals, such as DMA and the
Flash controller, that access memory independently of
the CPU.
The memory maps for the PIC32MX5XX/6XX/7XX
devices are shown in Figure 4-1, Figure 4-2 and
Figure 4-3.
4.1.1
PERIPHERAL REGISTERS
LOCATIONS
Table 4-1 through Table 4-44 contain the peripheral
address maps for the PIC32MX5XX/6XX/7XX
devices. Peripherals located on the PB bus are
mapped to 512-byte boundaries. Peripherals on the
FPB bus are mapped to 4-Kbyte boundaries.
Preliminary
DS61156C-page 45
PIC32MX5XX/6XX/7XX
FIGURE 4-1:
MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L,
PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND
PIC32MX775F256L DEVICES(1)
Virtual
Memory Map
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD040000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD03FFFF
Program Flash(2)
0xBD000000
0xA0010000
Reserved
0xA000FFFF
RAM(2)
0xA0000000
0x9FC02FF0
0x9FC02FFF
0x9FC02FEF
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
Reserved
0x9D040000
0x9D03FFFF
Program Flash(2)
KSEG0
0x1F8FFFFF
SFRs
0x1F800000
Reserved
0x9D000000
0x80008000
0x1D040000
0x1D03FFFF
Reserved
Program Flash(2)
0x1D000000
0x80007FFF
RAM(2)
Reserved
0x80000000
0x00000000
Note 1:
2:
DS61156C-page 46
RAM(2)
Reserved
0x00010000
0x0000FFFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end user development
tools (refer to the specific development tool documentation for information).
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 4-2:
MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L,
PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND
PIC32MX775F512L DEVICES
Virtual
Memory Map
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD080000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD07FFFF
Program Flash(2)
0xBD000000
0xA0010000
Reserved
0xA000FFFF
RAM(2)
0xA0000000
0x9FC02FF0
0x9FC02FFF
0x9FC02FEF
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
Reserved
0x9D080000
0x9D07FFFF
Program Flash(2)
KSEG0
0x1F8FFFFF
SFRs
0x1F800000
Reserved
0x9D000000
0x80010000
0x1D080000
0x1D07FFFF
Reserved
Program Flash(2)
0x1D000000
0x8000FFFF
RAM(2)
Reserved
0x80000000
0x00000000
Note 1:
2:
Reserved
RAM
(2)
0x00010000
0x0000FFFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end user development
tools (refer to the specific development tool documentation for information).
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 47
PIC32MX5XX/6XX/7XX
FIGURE 4-3:
MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L,
PIC32MX795F512H AND PIC32MX795F512L DEVICES
Virtual
Memory Map
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD080000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD07FFFF
Program Flash(2)
0xBD000000
0xA0020000
Reserved
0xA001FFFF
RAM(2)
0xA0000000
0x9FC02FF0
0x9FC02FFF
0x9FC02FEF
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
Reserved
0x9D080000
0x9D07FFFF
KSEG0
0x1F8FFFFF
Program Flash(2)
SFRs
0x1F800000
Reserved
0x9D000000
0x80020000
0x1D080000
0x1D07FFFF
Reserved
Program Flash(2)
0x1D000000
0x8001FFFF
RAM(2)
Reserved
0x80000000
0x00000000
Note 1:
2:
DS61156C-page 48
RAM(2)
Reserved
0x00020000
0x0001FFFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end user development
tools (refer to the specific development tool documentation for information).
Preliminary
 2010 Microchip Technology Inc.
2000
BMXCON(1)
2010 BMXDKPBA(1)
2020 BMXDUDBA(1)
2030 BMXDUPBA(1)
2040 BMXDRMSZ
2060
BMXPFMSZ
2070 BMXBOOTSZ
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
BMXCHEDMA
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
BMXWSDRM
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
15:0
16/0
BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F
BMXARB<2:0>
—
—
0040
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
xxxx
BMXDRMSZ<31:0>
15:0
31:16
17/1
BMXDUPBA<15:0>
31:16
15:0
18/2
BMXDUDBA<15:0>
15:0
31:16
19/3
BMXDKPBA<15:0>
15:0
31:16
20/4
All
Resets
Bits
xxxx
—
—
—
—
—
—
—
—
—
—
BMXPUPBA<15:0>
BMXPFMSZ<31:0>
—
—
BMXPUPBA<19:16>
0000
0000
xxxx
xxxx
BMXBOOTSZ<31:0>
0000
3000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
DS61156C-page 49
PIC32MX5XX/6XX/7XX
Preliminary
2050 BMXPUPBA(1)
BUS MATRIX REGISTER MAP
Bit Range
Register
Name
Virtual Address
(BF88_#)
 2010 Microchip Technology Inc.
TABLE 4-1:
Virtual Address
(BF88_#)
1000 INTCON
1010 INTSTAT
1020
IPTMR
31/15
30/14
29/13
28/12
27/11
26/10
—
31:16
—
—
—
—
—
15:0
—
FRZ
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
Preliminary
1040
IFS0
IFS1
1060
1070
IFS2
IEC0
IEC1
—
 2010 Microchip Technology Inc.
IEC2
1090
IPC0
10A0
IPC1
22/6
21/5
—
—
—
—
—
—
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
—
—
—
—
—
—
—
—
—
—
—
RIPL<2:0>
20/4
19/3
18/2
17/1
16/0
SS0
0000
INT0EP 0000
—
VEC<5:0>
0000
0000
0000
IPTMR<31:0>
15:0
0000
31:16 I2C1MIF
I2CSIF
I2CBIF
U1ARXIF
U1AEIF
SPI1ATXIF SPI1ARXIF SPI1AEIF
I2C1AMIF
I2C1ASIF
—
—
—
OC5IF
IC5IF
T5IF
INT4IF
OC4IF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
INT1IF
OC1IF
IC1IF
T1IF
INT0IF
CS1IF
31:16
IC3EIF
IC2EIF
IC1EIF
—
—
CAN1IF
USBIF
FCEIF
DMA7IF
DMA6IF
DMA5IF
DMA4IF
DMA3IF
DMA2IF
U3ATXIF
U3ARXIF
U3AEIF
U2ATXIF
U2ARXIF
U2AEIF
15:0
RTCCIF
FSCMIF
—
—
—
CMP2IF
CMP1IF
PMPIF
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF
I2C3ASIF I2C3ASIF I2C2AMIF
I2C2ASIF
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
U3BTXIF
U3BRXIF
U3BEIF
U2BTXIF
U2BRXIF
U2BEIF
U1ATXIE
U1ARXIE
U1AEIE
—
—
—
OC5IE
31:16 I2C1MIE I2C1SIE
I2C1BIE SPI1ATXIE SPI1ARXIE SPI1AEIE
I2C1AMIE
I2C1ASIE
IC4IF
T4IF
0000
CS0IF
CTIF
0000
I2C1ABIF
DMA1IF DMA0IF 0000
AD1IF
CNIF
0000
—
0000
I2C2ABIF
—
—
U1BTXIF U1BRXIF
IC5IE
T5IE
—
—
—
U1BEIF
PMPEIF
IC5EIF
INT4IE
OC4IE
IC4IE
T4IE
0000
CS0IE
CTIE
0000
IC4EIF 0000
I2C1ABIE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
INT1IE
OC1IE
IC1IE
T1IE
INT0IE
CS1IE
31:16
IC3EIE
IC2EIE
IC1EIE
—
—
CAN1IE
USBIE
FCEIE
DMA7IE
DMA6IE
DMA5IE
DMA4IE
DMA3IE
DMA2IE
U3ATXIE
U3ARXIE
U3AEIE
U2ATXIE
U2ARXIE
U2AEIE
15:0
RTCCIE
FSCMIE
—
—
—
CMP2IE
CMP1IE
PMPIE
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE
I2C3AMIE
1080
23/7
TPC<2:0>
I2C3AMIF
1050
24/8
31:16
U1ATXIF
1030
25/9
All
Resets
Register
Name
Bit Range
Bits
I2C3ASIE I2C3ASIE I2C2AMIE
I2C2ASIE
DMA1IE DMA0IE 0000
AD1IE
CNIE
0000
—
0000
I2C2ABIE
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
U3BTXIE
U3BRXIE
U3BEIE
U2BTXIE
U2BRXIE
U2BEIE
31:16
—
—
—
INT0IP<2:0>
INT0IS<1:0>
—
—
—
CS1IP<2:0>
CS1IS<1:0>
0000
15:0
—
—
—
CS0IP<2:0>
CS0IS<1:0>
—
—
—
CTIP<2:0>
CTIS<1:0>
0000
31:16
—
—
—
INT1IP<2:0>
INT1IS<1:0>
—
—
—
OC1IP<2:0>
OC1IS<1:0>
0000
15:0
—
—
—
IC1IP<2:0>
IC1IS<1:0>
—
—
—
T1IP<2:0>
T1IS<1:0>
0000
—
—
U1BTXIE U1BRXIE
—
—
—
U1BEIE
PMPEIE
IC5EIE
IC4EIE 0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
PIC32MX5XX/6XX/7XX
DS61156C-page 50
INTERRUPT REGISTER MAP FOR THE PIC32MX575F256H AND PIC32MX575F512H DEVICES(1)
TABLE 4-2:
Virtual Address
(BF88_#)
Register
Name
10B0
IPC2
10C0
IPC3
10D0
IPC4
10E0
IPC5
10F0
IPC6
1130
1140
1150
23/7
22/6
21/5
31:16
—
—
—
INT2IP<2:0>
15:0
—
—
—
IC2IP<2:0>
INT2IS<1:0>
—
—
—
OC2IP<2:0>
OC2IS<1:0>
0000
IC2IS<1:0>
—
—
—
T2IP<2:0>
T2IS<1:0>
31:16
—
—
—
0000
INT3IP<2:0>
INT3IS<1:0>
—
—
—
OC3IP<2:0>
OC3IS<1:0>
15:0
—
—
0000
—
IC3IP<2:0>
IC3IS<1:0>
—
—
—
T3IP<2:0>
T3IS<1:0>
31:16
—
0000
—
—
INT4IP<2:0>
INT4IS<1:0>
—
—
—
OC4IP<2:0>
OC4IS<1:0>
15:0
0000
—
—
—
IC4IP<2:0>
IC4IS<1:0>
—
—
—
T4IP<2:0>
T4IS<1:0>
0000
31:16
—
—
—
—
—
—
OC5IP<2:0>
OC5IS<1:0>
0000
15:0
—
—
—
IC5IP<2:0>
IC5IS<1:0>
—
—
—
T5IP<2:0>
T5IS<1:0>
0000
31:16
—
—
—
AD1IP<2:0>
AD1IS<1:0>
—
—
—
CNIP<2:0>
CNIS<1:0>
0000
U1AIP<2:0>
U1AIS<1:0>
SPI1AIP<2:0>
SPI1AIS<1:0>
I2C1AIP<2:0>
I2C1AIS<1:0>
CMP2IP<2:0>
CMP2IS<1:0>
0000
31:16
IPC8
1120
29/13
15:0
IPC7
1110
30/14
IPC10
IPC11
IPC12
—
—
—
—
—
27/11
—
26/10
—
I2C1IP<2:0>
—
25/9
—
24/8
—
I2C1IS<1:0>
U2AIP<2:0>
U2AIS<1:0>
SPI2AIP<2:0>
SPI2AIS<1:0>
I2C2AIP<2:0>
I2C2AIS<1:0>
—
—
20/4
—
—
—
—
19/3
18/2
17/1
16/0
0000
15:0
—
—
—
CMP1IP<2:0>
CMP1IS<1:0>
—
—
—
PMPIP<2:0>
PMPIS<1:0>
0000
31:16
—
—
—
RTCCIP<2:0>
RTCCIS<1:0>
—
—
—
FSCMIP<2:0>
FSCMIS<1:0>
0000
U3AIP<2:0>
U3AIS<1:0>
SPI3AIP<2:0>
SPI3AIS<1:0>
I2C3AIP<2:0>
I2C3AIS<1:0>
15:0
IPC9
—
28/12
—
—
—
—
—
—
—
—
—
—
—
0000
DS61156C-page 51
31:16
—
—
—
DMA3IP<2:0>
DMA3IS<1:0>
—
—
—
DMA2IP<2:0>
DMA2IS<1:0>
0000
15:0
—
—
—
DMA1IP<2:0>
DMA1IS<1:0>
—
—
—
DMA0IP<2:0>
DMA0IS<1:0>
0000
31:16
—
—
—
DMA7IP<2:0>
DMA7IS<1:0>
—
—
—
DMA6IP<2:0>
DMA6IS<1:0>
0000
15:0
—
—
—
DMA5IP<2:0>
DMA5IS<1:0>
—
—
—
DMA4IP<2:0>
DMA4IS<1:0>
0000
31:16
—
—
—
—
—
—
—
CAN1IP<2:0>
CAN1IS<1:0>
0000
15:0
—
—
—
USBIP<2:0>
USBIS<1:0>
—
—
—
FCEIP<2:0>
FCEIS<1:0>
0000
31:16
—
—
—
U3BIP<2:0>
U3BIS<1:0>
—
—
—
U2BIP<2:0>
U2BIS<1:0>
0000
15:0
—
—
—
U1BIP<2:0>
U1BIS<1:0>
—
—
—
—
0000
—
—
—
—
—
—
—
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
PIC32MX5XX/6XX/7XX
Preliminary
1100
31/15
All
Resets
Bits
Bit Range
 2010 Microchip Technology Inc.
INTERRUPT REGISTER MAP FOR THE PIC32MX575F256H AND PIC32MX575F512H DEVICES(1) (CONTINUED)
TABLE 4-2:
Virtual Address
(BF88_#)
INTERRUPT REGISTER MAP FOR THE PIC32MX675F256H, PIC32MX675F512H AND
PIC32MX695F512H DEVICES(1)
1000 INTCON
1010 INTSTAT
1020
IPTMR
31/15
30/14
29/13
28/12
27/11
26/10
—
31:16
—
—
—
—
—
15:0
—
FRZ
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
IFS0
Preliminary
1040
IFS1
—
IFS2
1060
IEC0
1070
IEC1
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
SS0
0000
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
—
—
—
—
—
—
—
—
—
—
—
I2C1MIF
I2CSIF
I2CBIF
U1ARXIF
 2010 Microchip Technology Inc.
IEC2
1090
IPC0
10A0
IPC1
10B0
IPC2
10C0
IPC3
18/2
17/1
16/0
VEC<5:0>
SPI1ATXIF SPI1ARXIF SPI1AEIF
I2C1AMIF I2C1ASIF
0000
0000
0000
0000
U1AEIF
—
—
—
OC5IF
IC5IF
T5IF
INT4IF
OC4IF
IC4IF
T4IF
0000
I2C1ABIF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
INT1IF
OC1IF
IC1IF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
31:16
IC3EIF
IC2EIF
IC1EIF
ETHIF
—
—
USBIF
FCEIF
DMA7IF
DMA6IF
DMA5IF
DMA4IF
DMA3IF
DMA2IF
DMA1IF
DMA0IF
0000
U3ATXIF
U3ARXIF
U3AEIF
U2ATXIF
U2ARXIF
U2AEIF
CMP2IF
CMP1IF
PMPIF
AD1IF
CNIF
0000
15:0
RTCCIF
FSCMIF
—
—
—
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF
31:16
—
—
15:0
—
—
—
I2C1SIE
I2C1BIE
31:16 I2C1MIE
I2C3ASIF
I2C3ASIF
I2C2AMIF
I2C2ASIF
I2C2ABIF
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
U3BTXIF
U3BRXIF
U3BEIF
U2BTXIF
U2BRXIF
U2BEIF
U1BTXIF
U1BRXIF
U1BEIF
PMPEIF
IC5EIF
IC4EIF
0000
U1ATXIE
U1ARXIE
U1AEIE
—
—
—
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
SPI1ATXIE SPI1ARXIE SPI1AEIE
I2C1AMIE I2C1ASIE
I2C1ABIE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
INT1IE
OC1IE
IC1IE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
0000
31:16
IC3EIE
IC2EIE
IC1EIE
ETHIE
—
—
USBIE
FCEIE
DMA7IE
DMA6IE
DMA5IE
DMA4IE
DMA3IE
DMA2IE
DMA1IE
DMA0IE
0000
U3ATXIE
U3ARXIE
U3AEIE
U2ATXIE
U2ARXIE
U2AEIE
CMP2IE
CMP1IE
PMPIE
AD1IE
CNIE
0000
15:0
RTCCIE
FSCMIE
—
—
—
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE
I2C3AMIE I2C3ASIE
1080
19/3
IPTMR<31:0>
15:0
31:16
—
RIPL<2:0>
I2C3AMIF
1050
24/8
31:16
U1ATXIF
1030
25/9
TPC<2:0>
20/4
All Resets
Bit Range
Register
Name
Bits
I2C3ASIE I2C2AMIE I2C2ASIE
I2C2ABIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U3BTXIE
U3BRXIE
U3BEIE
U2BTXIE
U2BRXIE
U2BEIE
U1BTXIE
U1BRXIE
U1BEIE
PMPEIE
IC5EIE
IC4EIE
0000
31:16
—
—
—
INT0IP<2:0>
INT0IS<1:0>
—
—
—
CS1IP<2:0>
CS1IS<1:0>
0000
15:0
—
—
—
CS0IP<2:0>
CS0IS<1:0>
—
—
—
CTIP<2:0>
CTIS<1:0>
0000
31:16
—
—
—
INT1IP<2:0>
INT1IS<1:0>
—
—
—
OC1IP<2:0>
OC1IS<1:0>
0000
15:0
—
—
—
IC1IP<2:0>
IC1IS<1:0>
—
—
—
T1IP<2:0>
T1IS<1:0>
0000
31:16
—
—
—
INT2IP<2:0>
INT2IS<1:0>
—
—
—
OC2IP<2:0>
OC2IS<1:0>
0000
15:0
—
—
—
IC2IP<2:0>
IC2IS<1:0>
—
—
—
T2IP<2:0>
T2IS<1:0>
0000
31:16
—
—
—
INT3IP<2:0>
INT3IS<1:0>
—
—
—
OC3IP<2:0>
OC3IS<1:0>
0000
15:0
—
—
—
IC3IP<2:0>
IC3IS<1:0>
—
—
—
T3IP<2:0>
T3IS<1:0>
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
PIC32MX5XX/6XX/7XX
DS61156C-page 52
TABLE 4-3:
Virtual Address
(BF88_#)
Register
Name
10D0
IPC4
INTERRUPT REGISTER MAP FOR THE PIC32MX675F256H, PIC32MX675F512H AND
PIC32MX695F512H DEVICES(1) (CONTINUED)
10E0
IPC5
10F0
IPC6
1100
1120
1130
IPC10
1140
IPC11
1150
IPC12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
INT4IP<2:0>
INT4IS<1:0>
—
—
—
OC4IP<2:0>
OC4IS<1:0>
0000
—
—
—
IC4IP<2:0>
IC4IS<1:0>
—
—
—
T4IP<2:0>
T4IS<1:0>
0000
31:16
—
—
—
—
—
—
OC5IP<2:0>
OC5IS<1:0>
0000
15:0
—
—
—
IC5IP<2:0>
IC5IS<1:0>
—
—
—
T5IP<2:0>
T5IS<1:0>
0000
31:16
—
—
—
AD1IP<2:0>
AD1IS<1:0>
—
—
—
CNIP<2:0>
CNIS<1:0>
0000
U1AIP<2:0>
U1AIS<1:0>
SPI1AIP<2:0>
SPI1AIS<1:0>
I2C1AIP<2:0>
I2C1AIS<1:0>
CMP2IP<2:0>
CMP2IS<1:0>
0000
—
—
—
—
—
—
—
—
I2C1IP<2:0>
—
—
—
I2C1IS<1:0>
U2AIP<2:0>
U2AIS<1:0>
SPI2AIP<2:0>
SPI2AIS<1:0>
I2C2AIP<2:0>
I2C2AIS<1:0>
—
—
—
—
—
—
0000
15:0
—
—
—
CMP1IP<2:0>
CMP1IS<1:0>
—
—
—
PMPIP<2:0>
PMPIS<1:0>
0000
31:16
—
—
—
RTCCIP<2:0>
RTCCIS<1:0>
—
—
—
FSCMIP<2:0>
FSCMIS<1:0>
0000
U3AIP<2:0>
U3AIS<1:0>
SPI3AIP<2:0>
SPI3AIS<1:0>
I2C3AIP<2:0>
I2C3AIS<1:0>
15:0
IPC9
28/12
15:0
31:16
IPC8
29/13
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
DMA3IP<2:0>
DMA3IS<1:0>
—
—
—
DMA2IP<2:0>
DMA2IS<1:0>
0000
15:0
—
—
—
DMA1IP<2:0>
DMA1IS<1:0>
—
—
—
DMA0IP<2:0>
DMA0IS<1:0>
0000
31:16
—
—
—
DMA7IP<2:0>
DMA7IS<1:0>
—
—
—
DMA6IP<2:0>
DMA6IS<1:0>
0000
15:0
—
—
—
DMA5IP<2:0>
DMA5IS<1:0>
—
—
—
DMA4IP<2:0>
DMA4IS<1:0>
0000
31:16
—
—
—
—
—
—
—
15:0
—
—
—
USBIP<2:0>
USBIS<1:0>
—
—
—
31:16
—
—
—
U3BIP<2:0>
U3BIS<1:0>
—
—
—
15:0
—
—
—
U1BIP<2:0>
U1BIS<1:0>
—
—
—
—
—
—
—
—
—
FCEIP<2:0>
—
—
—
0000
FCEIS<1:0>
0000
U2BIP<2:0>
U2BIS<1:0>
0000
ETHIP<2:0>
ETHIS<1:0>
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
DS61156C-page 53
PIC32MX5XX/6XX/7XX
Preliminary
1110
30/14
31:16
15:0
IPC7
31/15
All Resets
Bits
Bit Range
 2010 Microchip Technology Inc.
TABLE 4-3:
Virtual Address
(BF88_#)
INTERRUPT REGISTER MAP FOR PIC32MX775F256H, PIC32MX775F512H AND
PIC32MX795F512H DEVICES(1)
1000 INTCON
1010 INTSTAT
1020
IPTMR
31/15
30/14
29/13
28/12
27/11
26/10
—
31:16
—
—
—
—
—
15:0
—
FRZ
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
IFS0
Preliminary
1040
IFS1
—
IFS2
1060
IEC0
1070
IEC1
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
SS0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
—
—
—
—
—
—
—
—
0000
—
—
—
I2C1MIF
I2CSIF
I2CBIF
U1ARXIF
IEC2
 2010 Microchip Technology Inc.
1090
IPC0
10A0
IPC1
10B0
IPC2
10C0
IPC3
18/2
17/1
16/0
VEC<5:0>
SPI1ATXIF SPI1ARXIF SPI1AEIF
I2C1AMIF
I2C1ASIF
0000
0000
0000
0000
U1AEIF
—
—
—
OC5IF
IC5IF
T5IF
INT4IF
OC4IF
IC4IF
T4IF
0000
I2C1ABIF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
INT1IF
OC1IF
IC1IF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
31:16
IC3EIF
IC2EIF
IC1EIF
ETHIF
CAN2IF
CAN1IF
USBIF
FCEIF
DMA7IF
DMA6IF
DMA5IF
DMA4IF
DMA3IF
DMA2IF
DMA1IF
DMA0IF
0000
U3ATXIF
U3ARXIF
U3AEIF
U2ATXIF
U2ARXIF
U2AEIF
CMP2IF
CMP1IF
PMPIF
AD1IF
CNIF
0000
15:0
RTCCIF
FSCMIF
—
—
—
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF
I2C3ASIF
I2C3ASIF
I2C2AMIF
I2C2ASIF
I2C2ABIF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U3BTXIF
U3BRXIF
U3BEIF
U2BTXIF
U2BRXIF
U2BEIF
U1BTXIF
U1BRXIF
U1BEIF
PMPEIF
IC5EIF
IC4EIF
0000
U1ATXIE
U1ARXIE
U1AEIE
—
—
—
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
31:16
I2C1MIE
I2C1SIE
I2C1BIE
SPI1ATXIE SPI1ARXIE SPI1AEIE
I2C1AMIE I2C1ASIE
I2C1ABIE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
INT1IE
OC1IE
IC1IE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
0000
31:16
IC3EIE
IC2EIE
IC1EIE
ETHIE
CAN2IE
CAN1IE
USBIE
FCEIE
DMA7IE
DMA6IE
DMA5IE
DMA4IE
DMA3IE
DMA2IE
DMA1IE
DMA0IE
0000
U3ATXIE
U3ARXIE
U3AEIE
U2ATXIE
U2ARXIE
U2AEIE
CMP2IE
CMP1IE
PMPIE
AD1IE
CNIE
0000
0000
15:0
RTCCIE
FSCMIE
—
—
—
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE
I2C3AMIE I2C3ASIE
1080
19/3
IPTMR<31:0>
15:0
31:16
—
RIPL<2:0>
I2C3AMIF
1050
24/8
31:16
U1ATXIF
1030
25/9
TPC<2:0>
20/4
All Resets
Bit Range
Register
Name
Bits
I2C3ASIE I2C2AMIE I2C2ASIE
I2C2ABIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
U3BTXIE
U3BRXIE
U3BEIE
U2BTXIE
U2BRXIE
U2BEIE
U1BTXIE
U1BRXIE
U1BEIE
PMPEIE
IC5EIE
IC4EIE
31:16
—
—
—
INT0IS<1:0>
—
—
—
INT0IP<2:0>
CS1IP<2:0>
0000
CS1IS<1:0>
0000
15:0
—
—
—
CS0IP<2:0>
CS0IS<1:0>
—
—
—
CTIP<2:0>
CTIS<1:0>
0000
31:16
—
—
—
INT1IP<2:0>
INT1IS<1:0>
—
—
—
OC1IP<2:0>
OC1IS<1:0>
0000
15:0
—
—
—
IC1IP<2:0>
IC1IS<1:0>
—
—
—
T1IP<2:0>
T1IS<1:0>
0000
31:16
—
—
—
INT2IP<2:0>
INT2IS<1:0>
—
—
—
OC2IP<2:0>
OC2IS<1:0>
0000
15:0
—
—
—
IC2IP<2:0>
IC2IS<1:0>
—
—
—
T2IP<2:0>
T2IS<1:0>
0000
31:16
—
—
—
INT3IP<2:0>
INT3IS<1:0>
—
—
—
OC3IP<2:0>
OC3IS<1:0>
0000
15:0
—
—
—
IC3IP<2:0>
IC3IS<1:0>
—
—
—
T3IP<2:0>
T3IS<1:0>
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
PIC32MX5XX/6XX/7XX
DS61156C-page 54
TABLE 4-4:
Virtual Address
(BF88_#)
Register
Name
10D0
IPC4
INTERRUPT REGISTER MAP FOR PIC32MX775F256H, PIC32MX775F512H AND
PIC32MX795F512H DEVICES(1) (CONTINUED)
10E0
IPC5
10F0
IPC6
1100
IPC7
IPC8
1120
IPC9
1130
IPC10
1140
IPC11
1150
IPC12
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
INT4IP<2:0>
INT4IS<1:0>
—
—
—
OC4IP<2:0>
OC4IS<1:0>
0000
15:0
—
—
—
IC4IP<2:0>
IC4IS<1:0>
—
—
—
T4IP<2:0>
T4IS<1:0>
0000
31:16
—
—
—
—
—
—
OC5IP<2:0>
OC5IS<1:0>
0000
15:0
—
—
—
IC5IP<2:0>
IC5IS<1:0>
—
—
—
T5IP<2:0>
T5IS<1:0>
0000
31:16
—
—
—
AD1IP<2:0>
AD1IS<1:0>
—
—
—
CNIP<2:0>
CNIS<1:0>
0000
U1AIP<2:0>
U1AIS<1:0>
SPI1AIP<2:0>
SPI1AIS<1:0>
I2C1AIP<2:0>
I2C1AIS<1:0>
CMP2IP<2:0>
CMP2IS<1:0>
0000
15:0
31:16
—
—
—
—
—
—
—
—
I2C1IP<2:0>
—
—
—
I2C1IS<1:0>
U2AIP<2:0>
U2AIS<1:0>
SPI2AIP<2:0>
SPI2AIS<1:0>
I2C2AIP<2:0>
I2C2AIS<1:0>
—
—
—
—
—
—
0000
15:0
—
—
—
CMP1IP<2:0>
CMP1IS<1:0>
—
—
—
PMPIP<2:0>
PMPIS<1:0>
0000
31:16
—
—
—
RTCCIP<2:0>
RTCCIS<1:0>
—
—
—
FSCMIP<2:0>
FSCMIS<1:0>
0000
U3AIP<2:0>
U3AIS<1:0>
SPI3AIP<2:0>
SPI3AIS<1:0>
I2C3AIP<2:0>
I2C3AIS<1:0>
15:0
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
DMA3IP<2:0>
DMA3IS<1:0>
—
—
—
DMA2IP<2:0>
DMA2IS<1:0>
0000
15:0
—
—
—
DMA1IP<2:0>
DMA1IS<1:0>
—
—
—
DMA0IP<2:0>
DMA0IS<1:0>
0000
31:16
—
—
—
DMA7IP<2:0>
DMA7IS<1:0>
—
—
—
DMA6IP<2:0>
DMA6IS<1:0>
0000
15:0
—
—
—
DMA5IP<2:0>
DMA5IS<1:0>
—
—
—
DMA4IP<2:0>
DMA4IS<1:0>
0000
31:16
—
—
—
CAN2IP<2:0>
CAN2IS<1:0>
—
—
—
CAN1IP<2:0>
CAN1IS<1:0>
0000
15:0
—
—
—
USBIP<2:0>
USBIS<1:0>
—
—
—
FCEIP<2:0>
FCEIS<1:0>
0000
31:16
—
—
—
U3BIP<2:0>
U3BIS<1:0>
—
—
—
U2BIP<2:0>
U2BIS<1:0>
0000
15:0
—
—
—
U1BIP<2:0>
U1BIS<1:0>
—
—
—
ETHIP<2:0>
ETHIS<1:0>
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
DS61156C-page 55
PIC32MX5XX/6XX/7XX
Preliminary
1110
31/15
All Resets
Bits
Bit Range
 2010 Microchip Technology Inc.
TABLE 4-4:
Virtual Address
(BF88_#)
1000 INTCON
1010 INTSTAT
1020
IPTMR
31/15
30/14
29/13
28/12
27/11
26/10
—
31:16
—
—
—
—
—
15:0
—
FRZ
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
IFS0
1040
IFS1
—
Preliminary
IFS2
1060
IEC0
1070
IEC1
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
SS0
0000
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
—
—
—
—
—
—
—
—
—
—
—
IEC2
1090
IPC0
 2010 Microchip Technology Inc.
10A0
IPC1
10B0
IPC2
10C0
IPC3
10D0
IPC4
18/2
17/1
16/0
VEC<5:0>
I2C1MIF
I2CSIF
I2CBIF
U1ARXIF
I2C1ASIF
0000
U1AEIF
SPI1ATXIF SPI1ARXIF SPI1AEIF
I2C1AMIF
0000
0000
0000
SPI1TXIF
SPI1RXIF
SPI1EIF
OC5IF
IC5IF
T5IF
INT4IF
OC4IF
IC4IF
T4IF
0000
I2C1ABIF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
INT1IF
OC1IF
IC1IF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
31:16
IC3EIF
IC2EIF
IC1EIF
—
—
CAN1IF
USBIF
FCEIF
DMA7IF
DMA6IF
DMA5IF
DMA4IF
DMA3IF
DMA2IF
DMA1IF
DMA0IF
0000
U3ATXIF
U3ARXIF
U3AEIF
U2ATXIF
U2ARXIF
U2AEIF
CMP2IF
CMP1IF
PMPIF
AD1IF
CNIF
0000
15:0
RTCCIF
FSCMIF
I2C2MIF
I2C2SIF
I2C2BIF
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF
I2C3ASIF
I2C3ASIF
I2C2AMIF
I2C2ASIF
I2C2ABIF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U3BTXIF
U3BRXIF
U3BEIF
U2BTXIF
U2BRXIF
U2BEIF
U1BTXIF
U1BRXIF
U1BEIF
PMPEIF
IC5EIF
IC4EIF
0000
U1ATXIE
U1ARXIE
U1AEIE
31:16
I2C1MIE
I2C1SIE
I2C1BIE
SPI1TXIE SPI1RXIE
SPI1EIE
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
SPI1ATXIE SPI1ARXIE SPI1AEIE
I2C1AMIE I2C1ASIE
I2C1ABIE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
INT1IE
OC1IE
IC1IE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
0000
31:16
IC3EIE
IC2EIE
IC1EIE
—
—
CAN1IE
USBIE
FCEIE
DMA7IE
DMA6IE
DMA5IE
DMA4IE
DMA3IE
DMA2IE
DMA1IE
DMA0IE
0000
U3ATXIE
U3ARXIE
U3AEIE
U2ATXIE
U2ARXIE
U2AEIE
15:0
RTCCIE
FSCMIE
I2C2MIE
I2C2SIE
I2C2BIE
CMP2IE
CMP1IE
PMPIE
AD1IE
CNIE
0000
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE
I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE
1080
19/3
IPTMR<31:0>
15:0
31:16
—
RIPL<2:0>
I2C3AMIF
1050
24/8
31:16
U1ATXIF
1030
25/9
TPC<2:0>
20/4
All Resets
Bit Range
Register
Name
Bits
I2C2ABIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U3BTXIE
U3BRXIE
U3BEIE
U2BTXIE
U2BRXIE
U2BEIE
U1BTXIE
U1BRXIE
U1BEIE
PMPEIE
IC5EIE
IC4EIE
0000
31:16
—
—
—
INT0IP<2:0>
INT0IS<1:0>
—
—
—
CS1IP<2:0>
CS1IS<1:0>
0000
15:0
—
—
—
CS0IP<2:0>
CS0IS<1:0>
—
—
—
CTIP<2:0>
CTIS<1:0>
0000
31:16
—
—
—
INT1IP<2:0>
INT1IS<1:0>
—
—
—
OC1IP<2:0>
OC1IS<1:0>
0000
15:0
—
—
—
IC1IP<2:0>
IC1IS<1:0>
—
—
—
T1IP<2:0>
T1IS<1:0>
0000
31:16
—
—
—
INT2IP<2:0>
INT2IS<1:0>
—
—
—
OC2IP<2:0>
OC2IS<1:0>
0000
15:0
—
—
—
IC2IP<2:0>
IC2IS<1:0>
—
—
—
T2IP<2:0>
T2IS<1:0>
0000
31:16
—
—
—
INT3IP<2:0>
INT3IS<1:0>
—
—
—
OC3IP<2:0>
OC3IS<1:0>
0000
15:0
—
—
—
IC3IP<2:0>
IC3IS<1:0>
—
—
—
T3IP<2:0>
T3IS<1:0>
0000
31:16
—
—
—
INT4IP<2:0>
INT4IS<1:0>
—
—
—
OC4IP<2:0>
OC4IS<1:0>
0000
15:0
—
—
—
IC4IP<2:0>
IC4IS<1:0>
—
—
—
T4IP<2:0>
T4IS<1:0>
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
PIC32MX5XX/6XX/7XX
DS61156C-page 56
INTERRUPT REGISTER MAP FOR THE PIC32MX575F512L AND PIC32MX575F256L DEVICES(1)
TABLE 4-5:
Virtual Address
(BF88_#)
Register
Name
10E0
IPC5
10F0
IPC6
1100
IPC7
1110
IPC8
IPC9
1130
IPC10
1140
IPC11
1150
IPC12
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
SPI1IP<2:0>
SPI1IS<1:0>
—
—
—
OC5IP<2:0>
OC5IS<1:0>
0000
15:0
—
—
—
IC5IP<2:0>
IC5IS<1:0>
—
—
—
T5IP<2:0>
T5IS<1:0>
0000
31:16
—
—
—
AD1IP<2:0>
AD1IS<1:0>
—
—
—
CNIP<2:0>
CNIS<1:0>
0000
U1AIP<2:0>
U1AIS<1:0>
SPI1AIP<2:0>
SPI1AIS<1:0>
I2C1AIP<2:0>
I2C1AIS<1:0>
CMP2IP<2:0>
CMP2IS<1:0>
0000
15:0
31:16
—
—
—
—
—
I2C1IP<2:0>
—
I2C1IS<1:0>
U2AIP<2:0>
U2AIS<1:0>
SPI2AIP<2:0>
SPI2AIS<1:0>
I2C2AIP<2:0>
I2C2AIS<1:0>
—
—
—
—
—
—
0000
15:0
—
—
—
CMP1IP<2:0>
CMP1IS<1:0>
—
—
—
PMPIP<2:0>
PMPIS<1:0>
0000
31:16
—
—
—
RTCCIP<2:0>
RTCCIS<1:0>
—
—
—
FSCMIP<2:0>
FSCMIS<1:0>
0000
U3AIP<2:0>
U3AIS<1:0>
SPI3AIP<2:0>
SPI3AIS<1:0>
I2C3AIP<2:0>
I2C3AIS<1:0>
15:0
—
—
—
I2C2IP<2:0>
I2C2IS<1:0>
—
—
—
0000
31:16
—
—
—
DMA3IP<2:0>
DMA3IS<1:0>
—
—
—
DMA2IP<2:0>
DMA2IS<1:0>
0000
15:0
—
—
—
DMA1IP<2:0>
DMA1IS<1:0>
—
—
—
DMA0IP<2:0>
DMA0IS<1:0>
0000
31:16
—
—
—
DMA7IP<2:0>
DMA7IS<1:0>
—
—
—
DMA6IP<2:0>
DMA6IS<1:0>
0000
15:0
—
—
—
DMA5IP<2:0>
DMA5IS<1:0>
—
—
—
DMA4IP<2:0>
DMA4IS<1:0>
0000
31:16
—
—
—
—
—
—
—
CAN1IP<2:0>
CAN1IS<1:0>
0000
15:0
—
—
—
USBIP<2:0>
USBIS<1:0>
—
—
—
FCEIP<2:0>
FCEIS<1:0>
0000
31:16
—
—
—
U3BIP<2:0>
U3BIS<1:0>
—
—
—
U2BIP<2:0>
U2BIS<1:0>
0000
15:0
—
—
—
U1BIP<2:0>
U1BIS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
DS61156C-page 57
PIC32MX5XX/6XX/7XX
Preliminary
1120
31/15
All Resets
Bits
Bit Range
 2010 Microchip Technology Inc.
INTERRUPT REGISTER MAP FOR THE PIC32MX575F512L AND PIC32MX575F256L DEVICES(1) (CONTINUED)
TABLE 4-5:
Virtual Address
(BF88_#)
INTERRUPT REGISTER MAP FOR PIC32MX675F256L, PIC32MX675F512L AND
PIC32MX695F512L DEVICES(1)
1000 INTCON
1010 INTSTAT
1020
IPTMR
31/15
30/14
29/13
28/12
27/11
26/10
—
31:16
—
—
—
—
—
15:0
—
FRZ
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
IFS0
Preliminary
1040
IFS1
—
IFS2
1060
IEC0
1070
IEC1
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
SS0
0000
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
—
—
—
—
—
—
—
—
—
—
—
I2C1MIF
I2CSIF
I2CBIF
U1ARXIF
IEC2
 2010 Microchip Technology Inc.
1090
IPC0
10A0
IPC1
10B0
IPC2
10C0
IPC3
18/2
17/1
16/0
VEC<5:0>
SPI1ATXIF SPI1ARXIF SPI1AEIF
I2C1AMIF I2C1ASIF
0000
0000
0000
0000
U1AEIF
SPI1TXIF
SPI1RXIF
SPI1EIF
OC5IF
IC5IF
T5IF
INT4IF
OC4IF
IC4IF
T4IF
0000
I2C1ABIF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
INT1IF
OC1IF
IC1IF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
31:16
IC3EIF
IC2EIF
IC1EIF
ETHIF
—
—
USBIF
FCEIF
DMA7IF
DMA6IF
DMA5IF
DMA4IF
DMA3IF
DMA2IF
DMA1IF
DMA0IF
0000
U3ATXIF
U3ARXIF
U3AEIF
U2ATXIF
U2ARXIF
U2AEIF
CMP2IF
CMP1IF
PMPIF
AD1IF
CNIF
0000
15:0
RTCCIF
FSCMIF
I2C2MIF
I2C2SIF
I2C2BIF
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF
I2C3ASIF
I2C3ASIF
I2C2AMIF
I2C2ASIF
I2C2ABIF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U3BTXIF
U3BRXIF
U3BEIF
U2BTXIF
U2BRXIF
U2BEIF
U1BTXIF
U1BRXIF
U1BEIF
PMPEIF
IC5EIF
IC4EIF
0000
U1ATXIE
U1ARXIE
U1AEIE
SPI1ATXIE SPI1ARXIE SPI1AEIE SPI1TXIE SPI1RXIE
SPI1EIE
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
31:16
I2C1MIE
I2C1SIE
I2C1BIE
I2C1AMIE I2C1ASIE
I2C1ABIE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
INT1IE
OC1IE
IC1IE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
0000
31:16
IC3EIE
IC2EIE
IC1EIE
ETHIE
—
—
USBIE
FCEIE
DMA7IE
DMA6IE
DMA5IE
DMA4IE
DMA3IE
DMA2IE
DMA1IE
DMA0IE
0000
U3ATXIE
U3ARXIE
U3AEIE
U2ATXIE
U2ARXIE
U2AEIE
CMP2IE
CMP1IE
PMPIE
AD1IE
CNIE
0000
0000
15:0
RTCCIE
FSCMIE
I2C2MIE
I2C2SIE
I2C2BIE
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE
I2C3AMIE I2C3ASIE
1080
19/3
IPTMR<31:0>
15:0
31:16
—
RIPL<2:0>
I2C3AMIF
1050
24/8
31:16
U1ATXIF
1030
25/9
TPC<2:0>
20/4
All Resets
Register
Name
Bit Range
Bits
I2C3ASIE I2C2AMIE I2C2ASIE
I2C2ABIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
U3BTXIE
U3BRXIE
U3BEIE
U2BTXIE
U2BRXIE
U2BEIE
U1BTXIE
U1BRXIE
U1BEIE
PMPEIE
IC5EIE
IC4EIE
31:16
—
—
—
INT0IS<1:0>
—
—
—
INT0IP<2:0>
CS1IP<2:0>
0000
CS1IS<1:0>
0000
15:0
—
—
—
CS0IP<2:0>
CS0IS<1:0>
—
—
—
CTIP<2:0>
CTIS<1:0>
0000
31:16
—
—
—
INT1IP<2:0>
INT1IS<1:0>
—
—
—
OC1IP<2:0>
OC1IS<1:0>
0000
15:0
—
—
—
IC1IP<2:0>
IC1IS<1:0>
—
—
—
T1IP<2:0>
T1IS<1:0>
0000
31:16
—
—
—
INT2IP<2:0>
INT2IS<1:0>
—
—
—
OC2IP<2:0>
OC2IS<1:0>
0000
15:0
—
—
—
IC2IP<2:0>
IC2IS<1:0>
—
—
—
T2IP<2:0>
T2IS<1:0>
0000
31:16
—
—
—
INT3IP<2:0>
INT3IS<1:0>
—
—
—
OC3IP<2:0>
OC3IS<1:0>
0000
15:0
—
—
—
IC3IP<2:0>
IC3IS<1:0>
—
—
—
T3IP<2:0>
T3IS<1:0>
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
PIC32MX5XX/6XX/7XX
DS61156C-page 58
TABLE 4-6:
Virtual Address
(BF88_#)
Register
Name
10D0
IPC4
INTERRUPT REGISTER MAP FOR PIC32MX675F256L, PIC32MX675F512L AND
PIC32MX695F512L DEVICES(1) (CONTINUED)
10E0
IPC5
10F0
IPC6
1100
1120
1130
IPC10
1140
IPC11
1150
IPC12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
INT4IP<2:0>
INT4IS<1:0>
—
—
—
OC4IP<2:0>
OC4IS<1:0>
0000
—
—
—
IC4IP<2:0>
IC4IS<1:0>
—
—
—
T4IP<2:0>
T4IS<1:0>
0000
31:16
—
—
—
SPI1IP<2:0>
SPI1IS<1:0>
—
—
—
OC5IP<2:0>
OC5IS<1:0>
0000
15:0
—
—
—
IC5IP<2:0>
IC5IS<1:0>
—
—
—
T5IP<2:0>
T5IS<1:0>
0000
31:16
—
—
—
AD1IP<2:0>
AD1IS<1:0>
—
—
—
CNIP<2:0>
CNIS<1:0>
0000
U1AIP<2:0>
U1AIS<1:0>
SPI1AIP<2:0>
SPI1AIS<1:0>
I2C1AIP<2:0>
I2C1AIS<1:0>
CMP2IP<2:0>
CMP2IS<1:0>
0000
—
—
—
—
—
I2C1IP<2:0>
—
I2C1IS<1:0>
U2AIP<2:0>
U2AIS<1:0>
SPI2AIP<2:0>
SPI2AIS<1:0>
I2C2AIP<2:0>
I2C2AIS<1:0>
—
—
—
—
—
—
0000
15:0
—
—
—
CMP1IP<2:0>
CMP1IS<1:0>
—
—
—
PMPIP<2:0>
PMPIS<1:0>
0000
31:16
—
—
—
RTCCIP<2:0>
RTCCIS<1:0>
—
—
—
FSCMIP<2:0>
FSCMIS<1:0>
0000
U3AIP<2:0>
U3AIS<1:0>
SPI3AIP<2:0>
SPI3AIS<1:0>
I2C3AIP<2:0>
I2C3AIS<1:0>
15:0
IPC9
28/12
15:0
31:16
IPC8
29/13
—
—
—
I2C2IP<2:0>
I2C2IS<1:0>
—
—
—
0000
31:16
—
—
—
DMA3IP<2:0>
DMA3IS<1:0>
—
—
—
DMA2IP<2:0>
DMA2IS<1:0>
0000
15:0
—
—
—
DMA1IP<2:0>
DMA1IS<1:0>
—
—
—
DMA0IP<2:0>
DMA0IS<1:0>
0000
31:16
—
—
—
DMA7IP<2:0>
DMA7IS<1:0>
—
—
—
DMA6IP<2:0>
DMA6IS<1:0>
0000
15:0
—
—
—
DMA5IP<2:0>
DMA5IS<1:0>
—
—
—
DMA4IP<2:0>
DMA4IS<1:0>
0000
31:16
—
—
—
—
—
—
—
15:0
—
—
—
USBIP<2:0>
USBIS<1:0>
—
—
—
31:16
—
—
—
U3BIP<2:0>
U3BIS<1:0>
—
—
—
15:0
—
—
—
U1BIP<2:0>
U1BIS<1:0>
—
—
—
—
—
—
—
—
—
FCEIP<2:0>
—
—
—
0000
FCEIS<1:0>
0000
U2BIP<2:0>
U2BIS<1:0>
0000
ETHIP<2:0>
ETHIS<1:0>
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
DS61156C-page 59
PIC32MX5XX/6XX/7XX
Preliminary
1110
30/14
31:16
15:0
IPC7
31/15
All Resets
Bits
Bit Range
 2010 Microchip Technology Inc.
TABLE 4-6:
Virtual Address
(BF88_#)
INTERRUPT REGISTER MAP FOR PIC32MX775F256L, PIC32MX775F512L AND
PIC32MX795F512L DEVICES(1)
1000 INTCON
1010 INTSTAT
1020
IPTMR
31/15
30/14
29/13
28/12
27/11
26/10
—
31:16
—
—
—
—
—
15:0
—
FRZ
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
Preliminary
1040
—
1060
IEC0
1070
IEC1
—
—
—
—
—
—
—
—
—
SS0
0000
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
—
—
—
—
—
—
—
—
—
—
—
I2C1MIF
I2CSIF
I2CBIF
U1ARXIF
 2010 Microchip Technology Inc.
IEC2
1090
IPC0
10A0
IPC1
10B0
IPC2
10C0
IPC3
18/2
17/1
16/0
VEC<5:0>
SPI1ATXIF SPI1ARXIF SPI1AEIF
I2C1ASIF
0000
0000
0000
0000
U1AEIF
SPI1TXIF
SPI1RXIF
SPI1EIF
OC5IF
IC5IF
T5IF
INT4IF
OC4IF
IC4IF
T4IF
0000
I2C1ABIF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
INT1IF
OC1IF
IC1IF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
IC3EIF
IC2EIF
IC1EIF
ETHIF
CAN2IF
CAN1IF
USBIF
FCEIF
DMA7IF
DMA6IF
DMA5IF
DMA4IF
DMA3IF
DMA2IF
DMA1IF
DMA0IF
0000
U3ATXIF
U3ARXIF
U3AEIF
U2ATXIF
U2ARXIF
U2AEIF
CMP2IF
CMP1IF
PMPIF
AD1IF
CNIF
0000
RTCCIF
FSCMIF
I2C2MIF
I2C2SIF
I2C2BIF
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF
I2C3ASIF
I2C3ASIF
I2C2AMIF
I2C2ASIF
I2C2ABIF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U3BTXIF
U3BRXIF
U3BEIF
U2BTXIF
U2BRXIF
U2BEIF
U1BTXIF
U1BRXIF
U1BEIF
PMPEIF
IC5EIF
IC4EIF
0000
U1ATXIE
U1ARXIE
U1AEIE
31:16
I2C1MIE
I2C1SIE
I2C1BIE
SPI1TXIE SPI1RXIE
SPI1EIE
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
SPI1ATXIE SPI1ARXIE SPI1AEIE
I2C1AMIE I2C1ASIE I2C1ABIE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
INT1IE
OC1IE
IC1IE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
0000
31:16
IC3EIE
IC2EIE
IC1EIE
ETHIE
CAN2IE
CAN1IE
USBIE
FCEIE
DMA7IE
DMA6IE
DMA5IE
DMA4IE
DMA3IE
DMA2IE
DMA1IE
DMA0IE
0000
U3ATXIE
U3ARXIE
U3AEIE
U2ATXIE
U2ARXIE
U2AEIE
CMP2IE
CMP1IE
PMPIE
AD1IE
CNIE
0000
15:0
RTCCIE
FSCMIE
I2C2MIE
I2C2SIE
I2C2BIE
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE
I2C3AMIE I2C3ASIE
1080
—
19/3
31:16
15:0
IFS2
21/5
RIPL<2:0>
I2C3AMIF
1050
22/6
IPTMR<31:0>
I2C1AMIF
IFS1
23/7
15:0
31:16
IFS0
24/8
31:16
U1ATXIF
1030
25/9
TPC<2:0>
20/4
All Resets
Bit Range
Register
Name
Bits
I2C3ASIE I2C2AMIE I2C2ASIE
I2C2ABIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U3BTXIE
U3BRXIE
U3BEIE
U2BTXIE
U2BRXIE
U2BEIE
U1BTXIE
U1BRXIE
U1BEIE
PMPEIE
IC5EIE
IC4EIE
0000
31:16
—
—
—
INT0IP<2:0>
INT0IS<1:0>
—
—
—
CS1IP<2:0>
CS1IS<1:0>
0000
15:0
—
—
—
CS0IP<2:0>
CS0IS<1:0>
—
—
—
CTIP<2:0>
CTIS<1:0>
0000
31:16
—
—
—
INT1IP<2:0>
INT1IS<1:0>
—
—
—
OC1IP<2:0>
OC1IS<1:0>
0000
15:0
—
—
—
IC1IP<2:0>
IC1IS<1:0>
—
—
—
T1IP<2:0>
T1IS<1:0>
0000
31:16
—
—
—
INT2IP<2:0>
INT2IS<1:0>
—
—
—
OC2IP<2:0>
OC2IS<1:0>
0000
15:0
—
—
—
IC2IP<2:0>
IC2IS<1:0>
—
—
—
T2IP<2:0>
T2IS<1:0>
0000
31:16
—
—
—
INT3IP<2:0>
INT3IS<1:0>
—
—
—
OC3IP<2:0>
OC3IS<1:0>
0000
15:0
—
—
—
IC3IP<2:0>
IC3IS<1:0>
—
—
—
T3IP<2:0>
T3IS<1:0>
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
PIC32MX5XX/6XX/7XX
DS61156C-page 60
TABLE 4-7:
Virtual Address
(BF88_#)
Register
Name
10D0
IPC4
10E0
IPC5
INTERRUPT REGISTER MAP FOR PIC32MX775F256L, PIC32MX775F512L AND
PIC32MX795F512L DEVICES(1) (CONTINUED)
10F0
IPC6
1100
IPC7
IPC8
1120
IPC9
1130
IPC10
1140
IPC11
1150
IPC12
30/14
29/13
31:16
—
—
—
INT4IP<2:0>
15:0
—
—
—
IC4IP<2:0>
31:16
—
—
—
15:0
—
—
—
31:16
—
—
—
15:0
31:16
—
—
—
—
—
—
28/12
27/11
23/7
22/6
21/5
INT4IS<1:0>
—
—
—
OC4IP<2:0>
OC4IS<1:0>
0000
IC4IS<1:0>
—
—
—
T4IP<2:0>
T4IS<1:0>
0000
SPI1IP<2:0>
SPI1IS<1:0>
—
—
—
OC5IP<2:0>
OC5IS<1:0>
0000
IC5IP<2:0>
IC5IS<1:0>
—
—
—
T5IP<2:0>
T5IS<1:0>
0000
AD1IP<2:0>
AD1IS<1:0>
—
—
—
CNIP<2:0>
CNIS<1:0>
0000
U1AIP<2:0>
U1AIS<1:0>
SPI1AIP<2:0>
SPI1AIS<1:0>
I2C1AIP<2:0>
I2C1AIS<1:0>
CMP2IP<2:0>
CMP2IS<1:0>
0000
I2C1IP<2:0>
26/10
25/9
24/8
I2C1IS<1:0>
U2AIP<2:0>
U2AIS<1:0>
SPI2AIP<2:0>
SPI2AIS<1:0>
I2C2AIP<2:0>
I2C2AIS<1:0>
—
—
—
—
—
—
20/4
19/3
18/2
17/1
16/0
0000
15:0
—
—
—
CMP1IP<2:0>
CMP1IS<1:0>
—
—
—
PMPIP<2:0>
PMPIS<1:0>
0000
31:16
—
—
—
RTCCIP<2:0>
RTCCIS<1:0>
—
—
—
FSCMIP<2:0>
FSCMIS<1:0>
0000
U3AIP<2:0>
U3AIS<1:0>
SPI3AIP<2:0>
SPI3AIS<1:0>
I2C3AIP<2:0>
I2C3AIS<1:0>
15:0
—
—
—
I2C2IP<2:0>
I2C2IS<1:0>
—
—
—
0000
31:16
—
—
—
DMA3IP<2:0>
DMA3IS<1:0>
—
—
—
DMA2IP<2:0>
DMA2IS<1:0>
0000
15:0
—
—
—
DMA1IP<2:0>
DMA1IS<1:0>
—
—
—
DMA0IP<2:0>
DMA0IS<1:0>
0000
31:16
—
—
—
DMA7IP<2:0>
DMA7IS<1:0>
—
—
—
DMA6IP<2:0>
DMA6IS<1:0>
0000
15:0
—
—
—
DMA5IP<2:0>
DMA5IS<1:0>
—
—
—
DMA4IP<2:0>
DMA4IS<1:0>
0000
31:16
—
—
—
CAN2IP<2:0>
CAN2IS<1:0>
—
—
—
CAN1IP<2:0>
CAN1IS<1:0>
0000
15:0
—
—
—
USBIP<2:0>
USBIS<1:0>
—
—
—
FCEIP<2:0>
FCEIS<1:0>
0000
31:16
—
—
—
U3BIP<2:0>
U3BIS<1:0>
—
—
—
U2BIP<2:0>
U2BIS<1:0>
0000
15:0
—
—
—
U1BIP<2:0>
U1BIS<1:0>
—
—
—
ETHIP<2:0>
ETHIS<1:0>
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
DS61156C-page 61
PIC32MX5XX/6XX/7XX
Preliminary
1110
31/15
All Resets
Bits
Bit Range
 2010 Microchip Technology Inc.
TABLE 4-7:
Virtual Address
(BF80_#)
0600 T1CON
0610
TMR1
0620
TMR2
0820
Preliminary
TMR3
TMR4
TMR5
 2010 Microchip Technology Inc.
PR5
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
FRZ
SIDL
TWDIS
TWIP
—
—
—
TGATE
—
TCKPS<1:0>
—
TSYNC
TCS
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
T32
—
TCS
—
0000
15:0
TMR1<15:0>
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
TCKPS<2:0>
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
TCS
—
0000
0000
PR2<15:0>
15:0
FFFF
TCKPS<2:0>
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
T32
—
TCS
—
0000
TMR3<15:0>
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
—
0000
PR3<15:0>
15:0
FFFF
TCKPS<2:0>
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
TCS
—
0000
TMR4<15:0>
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
—
0000
PR4<15:0>
15:0
15:0
FFFF
TMR2<15:0>
—
31:16
0000
PR1<15:0>
15:0
0E00 T5CON
0E20
24/8
—
31:16
PR4
0E10
25/9
15:0
0C00 T4CON
0C20
26/10
ON
31:16
PR3
0C10
27/11
15:0
0A00 T3CON
0A20
28/12
15:0
31:16
PR2
0A10
29/13
15:0
0800 T2CON
0810
30/14
31:16
31:16
PR1
31/15
All Resets
Register
Name
Bit Range
Bits
FFFF
TCKPS<2:0>
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
TMR5<15:0>
—
—
—
—
—
—
—
—
—
PR5<15:0>
0000
FFFF
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
PIC32MX5XX/6XX/7XX
DS61156C-page 62
TIMER1-TIMER5 REGISTER MAP(1)
TABLE 4-8:
Virtual Address
(BF80_#)
Register
Name
2000
IC1CON(1)
IC1BUF
2200
IC2CON(1)
2210
IC2BUF
IC3CON
2410
IC3BUF
IC4CON
(1)
2610
IC4BUF
2800
IC5CON(1)
2810
IC5BUF
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
—
—
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
FEDGE
C32
ICTMR
31:16
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
FEDGE
C32
ICTMR
31:16
18/2
—
—
—
ICOV
ICBNE
17/1
16/0
—
—
ICM<2:0>
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
FEDGE
C32
ICTMR
31:16
xxxx
xxxx
—
—
ICI<1:0>
—
—
ICOV
ICBNE
—
—
—
ICM<2:0>
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
FEDGE
C32
ICTMR
31:16
xxxx
xxxx
—
—
ICI<1:0>
—
—
ICOV
ICBNE
—
—
—
ICM<2:0>
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
FEDGE
C32
ICTMR
xxxx
xxxx
—
—
ICI<1:0>
—
—
ICOV
ICBNE
—
—
—
ICM<2:0>
0000
0000
xxxx
xxxx
—
—
ICI<1:0>
—
—
ICOV
ICBNE
—
—
—
ICM<2:0>
IC5BUF<31:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
1:
0000
0000
IC4BUF<31:0>
15:0
0000
0000
IC3BUF<31:0>
15:0
0000
0000
IC2BUF<31:0>
15:0
15:0
19/3
IC1BUF<31:0>
15:0
31:16
ICI<1:0>
20/4
0000
0000
xxxx
xxxx
DS61156C-page 63
PIC32MX5XX/6XX/7XX
Preliminary
2600
(1)
31/15
All Resets
Bits
2010
2400
INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP
Bit Range
 2010 Microchip Technology Inc.
TABLE 4-9:
Virtual Address
(BF80_#)
3000 OC1CON
3010
OC1R
3020
OC1RS
3200 OC2CON
3210
OC2R
3220
OC2RS
Preliminary
3400 OC3CON
3410
OC3R
3420
OC3RS
3600 OC4CON
3610
OC4R
3620
OC4RS
3800 OC5CON
3810
OC5R
 2010 Microchip Technology Inc.
3820
OC5RS
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
31:16
xxxx
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM<2:0>
31:16
xxxx
xxxx
xxxx
OC2RS<31:0>
15:0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM<2:0>
31:16
15:0
xxxx
xxxx
xxxx
OC3RS<31:0>
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM<2:0>
31:16
15:0
xxxx
xxxx
xxxx
OC4RS<31:0>
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
OC5R<31:0>
OC5RS<31:0>
0000
0000
OC4R<31:0>
15:0
0000
0000
OC3R<31:0>
15:0
0000
0000
OC2R<31:0>
15:0
0000
0000
xxxx
—
15:0
—
xxxx
31:16
31:16
—
OCM<2:0>
OC1RS<31:0>
15:0
15:0
16/0
OC1R<31:0>
15:0
31:16
17/1
All Resets
Bit Range
Register
Name
Bits
—
—
OCM<2:0>
—
0000
0000
xxxx
xxxx
xxxx
xxxx
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
PIC32MX5XX/6XX/7XX
DS61156C-page 64
OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP(1)
TABLE 4-10:
Virtual Address
(BF80_#)
5000 I2C1ACON
5010 I2C1ASTAT
5020 I2C1AADD
5030 I2C1AMSK
5040 I2C1ABRG
5050
I2C1ATRN
5100 I2C2ACON
5110 I2C2ASTAT
5120 I2C2AADD
5130 I2C2AMSK
5140 I2C2ABRG
I2C2ATRN
5160 I2C2ARCV
5200 I2C3ACON
5210 I2C3ASTAT
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
ADD<9:0>
—
—
—
—
—
—
—
—
—
—
MSK<9:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
—
—
—
—
—
I2CT1DATA<7:0>
—
0000
0000
I2C1BRG<11:0>
—
0000
0000
—
—
0000
0000
—
—
—
I2CR1DATA<7:0>
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
ADD<9:0>
—
—
—
—
—
—
—
—
—
—
MSK<9:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
—
—
—
—
—
I2CT1DATA<7:0>
—
0000
0000
I2C1BRG<11:0>
—
0000
0000
—
—
0000
0000
—
—
—
I2CR1DATA<7:0>
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
DS61156C-page 65
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
All Resets
Bit Range
31/15
0000
PIC32MX5XX/6XX/7XX
Preliminary
5060 I2C1ARCV
5150
I2C1, I2C1A, I2C2A AND I2C3A REGISTER MAP(1)
Bits
Register
Name
 2010 Microchip Technology Inc.
TABLE 4-11:
Virtual Address
(BF80_#)
5230 I2C3AMSK
5240 I2C3ABRG
I2C3ATRN
5260 I2C3ARCV
Preliminary
5300
I2C1CON
5310
I2C1STAT
5320
I2C1ADD
5330
I2C1MSK
5340
I2C1BRG
5350
I2C1TRN
5360
I2C1RCV
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
ADD<9:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
I2CR1DATA<7:0>
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
ADD<9:0>
—
—
—
—
—
—
—
—
—
—
MSK<9:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
—
—
—
—
—
I2CT1DATA<7:0>
—
0000
0000
I2C1BRG<11:0>
—
0000
0000
—
—
0000
0000
—
—
—
I2CR1DATA<7:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
0000
0000
I2CT1DATA<7:0>
—
0000
0000
I2C1BRG<11:0>
—
0000
0000
MSK<9:0>
—
All Resets
Bit Range
Register
Name
Bits
5220 I2C3AADD
5250
I2C1, I2C1A, I2C2A AND I2C3A REGISTER MAP(1) (CONTINUED)
0000
0000
PIC32MX5XX/6XX/7XX
DS61156C-page 66
TABLE 4-11:
 2010 Microchip Technology Inc.
Virtual Address
(BF80_#)
I2C2 REGISTER MAP FOR PIC32MX575F512L, PIC32MX575F256L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
5400 I2C2CON
5410 I2C2STAT
5420 I2C2ADD
5430 I2C2MSK
5440 I2C2BRG
5450 I2C2TRN
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
FRZ
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
—
—
—
—
—
—
—
—
—
—
15:0 ACKSTAT
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
ADD<9:0>
—
—
—
—
—
—
—
—
—
—
MSK<9:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
I2CT1DATA<7:0>
—
0000
0000
I2C2BRG<11:0>
—
0000
0000
—
—
0000
0000
—
—
—
I2CR1DATA<7:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
All Resets
31/15
0000
0000
DS61156C-page 67
PIC32MX5XX/6XX/7XX
Preliminary
5460 I2C2RCV
Bit Range
Bits
Register
Name
 2010 Microchip Technology Inc.
TABLE 4-12:
Virtual Address
(BF80_#)
U1ASTA
(1)
6020 U1ATXREG
6030 U1ARXREG
6040 U1ABRG
(1)
(1)
Preliminary
U1BSTA(1)
6220 U1BTXREG
6230 U1BRXREG
6240
U1BBRG(1)
6400 U2AMODE
6410
U2ASTA
(1)
(1)
6420 U2ATXREG
6430 U2ARXREG
 2010 Microchip Technology Inc.
6440 U2ABRG
6600
6610
(1)
U2BMODE(1)
U2BSTA
30/14
29/13
28/12
27/11
26/10
25/9
24/8
—
—
31:16
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
IREN
RTSMD
—
31:16
—
—
—
—
—
—
—
ADM_EN
15:0
UTXISEL<1:0>
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
31:16
—
—
—
—
—
—
—
—
UEN<1:0>
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
6200 U1BMODE
6210
31/15
(1)
6620 U2BTXREG
23/7
22/6
21/5
20/4
19/3
18/2
17/1
—
—
—
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL<1:0>
16/0
—
0000
STSEL
0000
ADDR<7:0>
URXISEL<1:0>
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
0000
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
STSEL
0000
Transmit Register
—
—
0000
Receive Register
0000
BRG<15:0>
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
FRZ
SIDL
IREN
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
31:16
—
—
—
—
—
—
—
ADM_EN
15:0
UTXISEL<1:0>
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
IREN
RTSMD
—
31:16
—
—
—
—
—
—
—
ADM_EN
15:0
UTXISEL<1:0>
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
31:16
—
—
—
—
—
—
—
—
15:0
PDSEL<1:0>
ADDR<7:0>
URXISEL<1:0>
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
0000
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
WAKE
LPBACK
ABAUD
RXINV
BRGH
STSEL
0000
Transmit Register
—
—
0000
Receive Register
0000
BRG<15:0>
UEN<1:0>
0000
PDSEL<1:0>
ADDR<7:0>
URXISEL<1:0>
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
0000
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
STSEL
0000
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
IREN
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
31:16
—
—
—
—
—
—
—
ADM_EN
15:0
UTXISEL<1:0>
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
15:0
Transmit Register
—
—
0000
Receive Register
0000
BRG<15:0>
0000
PDSEL<1:0>
ADDR<7:0>
URXISEL<1:0>
—
—
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
—
0000
Transmit Register
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
1:
All Resets
Register
Name
Bit Range
Bits
6000 U1AMODE(1)
6010
UART1A, UART1B, UART2A, UART2B, UART3A AND UART3B REGISTER MAP
0000
PIC32MX5XX/6XX/7XX
DS61156C-page 68
TABLE 4-13:
Virtual Address
(BF80_#)
6640 U2BBRG
(1)
(1)
U3ASTA(1)
6820 U3ATXREG
6830 U3ARXREG
U3BSTA
(1)
(1)
6A20 U3BTXREG
6A30 U3BRXREG
6A40 U3BBRG
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
IREN
RTSMD
—
31:16
—
—
—
—
—
—
—
ADM_EN
15:0
UTXISEL<1:0>
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
31:16
—
—
—
—
—
—
—
—
(1)
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
0000
0000
Receive Register
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
WAKE
LPBACK
ABAUD
RXINV
BRGH
STSEL
0000
BRG<15:0>
UEN<1:0>
0000
ADDR<7:0>
URXISEL<1:0>
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
0000
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
STSEL
0000
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
IREN
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
31:16
—
—
—
—
—
—
—
ADM_EN
15:0
UTXISEL<1:0>
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
31:16
—
—
—
—
—
—
—
—
15:0
PDSEL<1:0>
Transmit Register
—
—
0000
Receive Register
0000
BRG<15:0>
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
0000
PDSEL<1:0>
ADDR<7:0>
URXISEL<1:0>
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
0000
—
—
—
0000
—
—
—
0000
—
—
—
—
—
—
—
—
—
Transmit Register
—
—
0000
Receive Register
—
—
0000
BRG<15:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
1:
0000
DS61156C-page 69
PIC32MX5XX/6XX/7XX
Preliminary
U3ABRG(1)
6A00 U3BMODE
6A10
30/14
15:0
6800 U3AMODE
6840
31/15
All Resets
Bit Range
6630 U2BRXREG
6810
UART1A, UART1B, UART2A, UART2B, UART3A AND UART3B REGISTER MAP (CONTINUED)
Bits
Register
Name
 2010 Microchip Technology Inc.
TABLE 4-13:
Virtual Address
(BF80_#)
5800 SPI1ACON
5810 SPI1ASTAT
5820 SPI1ABUF
5830 SPI1ABRG
5A00 SPI2ACON
5A10 SPI2ASTAT
Preliminary
5A20 SPI2ABUF
5A30 SPI2ABRG
5C00 SPI3ACON
5C10 SPI3ASTAT
5C20 SPI3ABUF
5C30 SPI3ABRG
31/15
30/14
29/13
31:16
FRMEN
15:0
ON
FRMSYNC FRMPOL
FRZ
SIDL
31:16
—
—
—
15:0
—
—
—
28/12
27/11
26/10
MSSEN
FRMSYPW
DISSDO
MODE32
25/9
SMP
—
CKE
SSEN
—
—
—
SRMT
SPIROV
SPIRBE
RXBUFELM<4:0>
—
SPIBUSY
—
—
SPITUR
22/6
21/5
20/4
19/3
18/2
17/1
—
—
CKP
MSTEN
—
—
—
SPIFE
—
STXISEL<1:0>
16/0
ENHBUF 0000
SRXISEL<1:0>
TXBUFELM<4:0>
—
SPITBE
—
—
15:0
—
31:16
FRMEN
—
—
—
—
FRMSYNC FRMPOL
15:0
ON
FRZ
SIDL
31:16
—
—
—
15:0
—
—
—
—
—
—
—
—
—
MSSEN
FRMSYPW
DISSDO
MODE32
—
—
SPITBF
SPIRBF
—
SPIBUSY
0000
—
—
—
—
—
—
MODE16
SMP
SSEN
CKP
MSTEN
—
—
—
—
—
31:16
SRMT
SPIROV
SPIRBE
—
—
—
—
—
—
—
SPIFE
—
STXISEL<1:0>
—
BRG<8:0>
CKE
RXBUFELM<4:0>
SPITUR
0000
SRXISEL<1:0>
TXBUFELM<4:0>
—
—
15:0
—
31:16
FRMEN
—
—
—
—
FRMSYNC FRMPOL
15:0
ON
FRZ
SIDL
31:16
—
—
—
15:0
—
—
—
—
—
—
—
—
—
MSSEN
FRMSYPW
DISSDO
MODE32
—
—
SPITBE
—
SPITBF
SPIRBF
MODE16
SMP
CKE
—
SPIBUSY
—
—
31:16
SPITUR
—
—
—
—
—
SSEN
CKP
MSTEN
—
—
—
SRMT
SPIROV
SPIRBE
—
—
—
—
—
—
—
SPIFE
—
STXISEL<1:0>
—
0000
SRXISEL<1:0>
TXBUFELM<4:0>
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
SPITBE
—
0000
0000
SPITBF
SPIRBF
0000
0000
0000
—
—
—
—
—
—
—
BRG<8:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
0000
ENHBUF 0000
DATA<31:0>
15:0
0000
0000
—
BRG<8:0>
RXBUFELM<4:0>
0000
0000
0000
—
FRMCNT<2:0>
0000
ENHBUF 0000
DATA<31:0>
15:0
0000
0000
—
FRMCNT<2:0>
0000
0000
DATA<31:0>
15:0
31:16
23/7
FRMCNT<2:0>
MODE16
31:16
31:16
24/8
All Resets
Bit Range
Register
Name
Bits
0000
0000
PIC32MX5XX/6XX/7XX
DS61156C-page 70
SPI1A, SPI2A AND SPI3A REGISTER MAP(1)
TABLE 4-14:
 2010 Microchip Technology Inc.
Register
Name
5E10 SPI1STAT
SPI1BUF
5E30 SPI1BRG
31/15
30/14
29/13
31:16
FRMEN
15:0
ON
FRMSYNC FRMPOL
FRZ
SIDL
31:16
—
—
—
15:0
—
—
—
28/12
27/11
26/10
MSSEN
FRMSYPW
DISSDO
MODE32
25/9
24/8
23/7
—
CKE
SSEN
—
—
—
SRMT
SPIROV
SPIRBE
FRMCNT<2:0>
MODE16
SMP
RXBUFELM<4:0>
—
SPIBUSY
—
—
31:16
SPITUR
22/6
21/5
20/4
19/3
18/2
17/1
—
—
CKP
MSTEN
—
—
—
SPIFE
—
STXISEL<1:0>
16/0
ENHBUF 0000
SRXISEL<1:0>
TXBUFELM<4:0>
—
SPITBE
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
SPITBF
SPIRBF
0000
0000
0000
—
—
—
—
—
—
—
BRG<8:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
0000
0000
DATA<31:0>
15:0
All Resets
Bits
5E00 SPI1CON
5E20
SPI1 REGISTER MAP FOR PIC32MX575F512L, PIC32MX575F256L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bit Range
Virtual Address
(BF80_#)
 2010 Microchip Technology Inc.
TABLE 4-15:
0000
0000
DS61156C-page 71
PIC32MX5XX/6XX/7XX
Preliminary
Register
Name
31/15
30/14
29/13
28/12
27/11
26/10
—
25/9
24/8
23/7
—
—
—
22/6
21/5
—
—
31:16
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
9010 AD1CON2
(1)
31:16
—
—
—
—
—
—
—
—
—
—
15:0
VCFG2
VCFG1
VCFG0
OFFCAL
—
CSCNA
—
—
BUFS
—
9020 AD1CON3
(1)
31:16
—
—
—
—
—
—
—
—
—
9000 AD1CON1(1)
9040
AD1CHS(1)
9060 AD1PCFG(1)
9050 AD1CSSL
(1)
Preliminary
9070 ADC1BUF0
9080 ADC1BUF1
9090 ADC1BUF2
90A0 ADC1BUF3
90B0 ADC1BUF4
90C0 ADC1BUF5
90D0 ADC1BUF6
90E0 ADC1BUF7
 2010 Microchip Technology Inc.
90F0 ADC1BUF8
9100 ADC1BUF9
9110 ADC1BUFA
9120 ADC1BUFB
15:0
ADRC
—
—
31:16
CH0NB
—
—
—
15:0
—
—
—
—
18/2
17/1
16/0
—
—
—
—
—
—
ASAM
SAMP
DONE
0000
—
—
—
—
—
—
0000
BUFM
ALTS
0000
—
—
—
—
—
0000
CH0NA
—
—
—
—
—
—
—
SSRC<2:0>
SMPI<3:0>
—
—
ADCS<7:0>
CH0SB<3:0>
—
19/3
CLRASAM
FORM<2:0>
SAMC<4:0>
—
20/4
—
—
—
0000
0000
CH0SA<3:0>
—
—
0000
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
PCFG15
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CSSL15
CSSL14
CSSL13
CSSL12
CSSL11
CSSL10
CSSL9
CSSL8
CSSL7
CSSL6
CSSL5
CSSL4
CSSL3
CSSL2
CSSL1
CSSL0
0000
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
ADC Result Word 0 (ADC1BUF0<31:0>)
ADC Result Word 1 (ADC1BUF1<31:0>)
ADC Result Word 2 (ADC1BUF2<31:0>)
ADC Result Word 3 (ADC1BUF3<31:0>)
ADC Result Word 4 (ADC1BUF4<31:0>)
ADC Result Word 5 (ADC1BUF5<31:0>)
ADC Result Word 6 (ADC1BUF6<31:0>)
ADC Result Word 7 (ADC1BUF7<31:0>)
ADC Result Word 8 (ADC1BUF8<31:0>)
ADC Result Word 9 (ADC1BUF9<31:0>)
ADC Result Word A (ADC1BUFA<31:0>)
ADC Result Word B (ADC1BUFB<31:0>)
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
All Resets
Bits
Bit Range
Virtual Address
(BF80_#)
ADC REGISTER MAP
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MX5XX/6XX/7XX
DS61156C-page 72
TABLE 4-16:
ADC REGISTER MAP (CONTINUED)
Register
Name
9130 ADC1BUFC
9140 ADC1BUFD
9150 ADC1BUFE
9160 ADC1BUFF
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
ADC Result Word C (ADC1BUFC<31:0>)
ADC Result Word D (ADC1BUFD<31:0>)
ADC Result Word E (ADC1BUFE<31:0>)
ADC Result Word F (ADC1BUFF<31:0>)
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
All Resets
Bits
Bit Range
Virtual Address
(BF80_#)
 2010 Microchip Technology Inc.
TABLE 4-16:
0000
0000
0000
0000
0000
0000
0000
0000
DS61156C-page 73
PIC32MX5XX/6XX/7XX
Preliminary
Virtual Address
(BF88_#)
DMASTAT
3020 DMAADDR
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
FRZ
—
SUSPEND
BUSY
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
RDWR
31:16
DMACH<2:0>
0000
0000
DMAADDR<31:0>
15:0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
1:
DMA CRC REGISTER MAP(1)
3030 DCRCCON
3040 DCRCDATA
3050 DCRCXOR
31/15
30/14
31:16
—
—
15:0
—
—
31:16
15:0
31:16
15:0
29/13
28/12
BYTO<1:0>
—
27/11
WBO
26/10
25/9
24/8
—
—
BITO
PLEN<4:0>
23/7
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
—
CRCEN
CRCAPP
CRCTYP
—
—
17/1
16/0
—
—
CRCCH<2:0>
DCRCDATA<31:0>
DCRCXOR<31:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
All Resets
Bit Range
Bits
Register
Name
Preliminary
Virtual Address
(BF88_#)
TABLE 4-18:
All Resets
Bit Range
Register
Name
Bits
3000 DMACON(1)
3010
DMA GLOBAL REGISTER MAP
0000
0000
0000
0000
0000
0000
PIC32MX5XX/6XX/7XX
DS61156C-page 74
TABLE 4-17:
 2010 Microchip Technology Inc.
Virtual Address
(BF88_#)
3060 DCH0CON
3070 DCH0ECON
3080
3090
DCH0INT
DCH0SSA
30A0 DCH0DSA
30B0 DCH0SSIZ
30D0 DCH0SPTR
30E0 DCH0DPTR
30F0 DCH0CSIZ
3100 DCH0CPTR
DCH0DAT
3120 DCH1CON
3130 DCH1ECON
3140
3150
DCH1INT
DCH1SSA
DS61156C-page 75
3160 DCH1DSA
3170 DCH1SSIZ
24/8
30/14
29/13
28/12
27/11
26/10
25/9
31:16
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
0000
CHSIRQ<7:0>
15:0
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
CHCHN
CHAEN
—
—
—
—
—
CHEDET
CHPRI<1:0>
CHAIRQ<7:0>
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
31:16
31:16
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCPTR<15:0>
0000
0000
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
0000
CHSIRQ<7:0>
15:0
—
0000
0000
CHCSIZ<15:0>
15:0
0000
0000
CHDPTR<15:0>
15:0
31:16
—
CHSPTR<15:0>
15:0
31:16
—
CHDSIZ<15:0>
15:0
31:16
0000
CHSSIZ<15:0>
15:0
31:16
0000
CHDSA<31:0>
15:0
0000
0000
CHSSA<31:0>
15:0
31:16
0000
0000
00FF
CHPDAT<7:0>
—
—
CHPRI<1:0>
CHAIRQ<7:0>
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
15:0
0000
0000
CHDSA<31:0>
15:0
31:16
—
—
—
—
—
—
—
—
—
0000
0000
CHSSA<31:0>
15:0
31:16
0000
0000
00FF
31:16
31:16
0000
0000
0000
—
—
—
—
—
—
—
CHSSIZ<15:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
All Resets
Bit Range
31/15
0000
0000
PIC32MX5XX/6XX/7XX
Preliminary
30C0 DCH0DSIZ
3110
DMA CHANNELS 0-7 REGISTER MAP(1)
Bits
Register
Name
 2010 Microchip Technology Inc.
TABLE 4-19:
Virtual Address
(BF88_#)
3190 DCH1SPTR
31A0 DCH1DPTR
31B0 DCH1CSIZ
31C0 DCH1CPTR
31D0 DCH1DAT
Preliminary
31E0 DCH2CON
31F0 DCH2ECON
3200
DCH2INT
3210
DCH2SSA
3220 DCH2DSA
3230 DCH2SSIZ
3240 DCH2DSIZ
3250 DCH2SPTR
 2010 Microchip Technology Inc.
3260 DCH2DPTR
3270 DCH2CSIZ
3280 DCH2CPTR
DCH2DAT
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
CHSIRQ<7:0>
15:0
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCPTR<15:0>
31:16
0000
0000
CHCSIZ<15:0>
15:0
0000
0000
CHDPTR<15:0>
15:0
31:16
—
0000
0000
00FF
CHSPTR<15:0>
15:0
31:16
CHAIRQ<7:0>
CHDSIZ<15:0>
15:0
31:16
—
CHPRI<1:0>
CHSSIZ<15:0>
15:0
31:16
—
CHDSA<31:0>
15:0
0000
0000
CHSSA<31:0>
31:16
31:16
CHPDAT<7:0>
0000
0000
CHPDAT<7:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
0000
0000
CHCPTR<15:0>
—
0000
0000
CHCSIZ<15:0>
15:0
0000
0000
CHDPTR<15:0>
15:0
31:16
22/6
CHSPTR<15:0>
15:0
31:16
23/7
CHDSIZ<15:0>
15:0
31:16
24/8
All Resets
Bit Range
Register
Name
Bits
3180 DCH1DSIZ
3290
DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED)
0000
0000
PIC32MX5XX/6XX/7XX
DS61156C-page 76
TABLE 4-19:
Virtual Address
(BF88_#)
32A0 DCH3CON
32B0 DCH3ECON
32C0
DCH3INT
32D0 DCH3SSA
32E0 DCH3DSA
32F0 DCH3SSIZ
3310 DCH3SPTR
3320 DCH3DPTR
3330 DCH3CSIZ
3340 DCH3CPTR
DCH3DAT
3360 DCH4CON
3370 DCH4ECON
3380
3390
DCH4INT
DCH4SSA
DS61156C-page 77
33A0 DCH4DSA
33B0 DCH4SSIZ
24/8
30/14
29/13
28/12
27/11
26/10
25/9
31:16
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
CHSIRQ<7:0>
15:0
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
CHCHN
CHAEN
—
—
—
—
—
CHEDET
CHPRI<1:0>
CHAIRQ<7:0>
0000
0000
00FF
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
31:16
31:16
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCPTR<15:0>
0000
0000
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
0000
15:0
CHSIRQ<7:0>
—
0000
0000
CHCSIZ<15:0>
15:0
0000
0000
CHDPTR<15:0>
15:0
31:16
—
CHSPTR<15:0>
15:0
31:16
—
CHDSIZ<15:0>
15:0
31:16
0000
CHSSIZ<15:0>
15:0
31:16
0000
CHDSA<31:0>
15:0
31:16
0000
CHSSA<31:0>
15:0
CHPDAT<7:0>
—
—
CHPRI<1:0>
CHAIRQ<7:0>
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
31:16
31:16
15:0
0000
0000
CHDSA<31:0>
15:0
—
—
—
—
—
—
—
—
—
0000
0000
CHSSA<31:0>
15:0
0000
0000
00FF
31:16
31:16
0000
0000
0000
—
—
—
—
—
—
—
CHSSIZ15:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
All Resets
Bit Range
31/15
0000
0000
PIC32MX5XX/6XX/7XX
Preliminary
3300 DCH3DSIZ
3350
DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED)
Bits
Register
Name
 2010 Microchip Technology Inc.
TABLE 4-19:
Virtual Address
(BF88_#)
33D0 DCH4SPTR
33E0 DCH4DPTR
33F0 DCH4CSIZ
3400 DCH4CPTR
DCH4DAT
Preliminary
3420 DCH5CON
3430 DCH5ECON
3440
DCH5INT
3450
DCH5SSA
3460
DCH5DSA
3470 DCH5SSIZ
3480 DCH5DSIZ
3490 DCH5SPTR
 2010 Microchip Technology Inc.
34A0 DCH5DPTR
34B0 DCH5CSIZ
34C0 DCH5CPTR
34D0 DCH5DAT
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
CHSIRQ<7:0>
15:0
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCPTR<15:0>
31:16
0000
0000
CHCSIZ<15:0>
15:0
0000
0000
CHDPTR<15:0>
15:0
31:16
—
0000
0000
00FF
CHSPTR<15:0>
15:0
31:16
CHAIRQ<7:0>
CHDSIZ<15:0>
15:0
31:16
—
CHPRI<1:0>
CHSSIZ<15:0>
15:0
31:16
—
CHDSA<31:0>
15:0
0000
0000
CHSSA<31:0>
31:16
31:16
CHPDAT<7:0>
0000
0000
CHPDAT<7:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
0000
0000
CHCPTR<15:0>
—
0000
0000
CHCSIZ<15:0>
15:0
0000
0000
CHDPTR<15:0>
15:0
31:16
22/6
CHSPTR<15:0>
15:0
31:16
23/7
CHDSIZ<15:0>
15:0
31:16
24/8
All Resets
Bit Range
Register
Name
Bits
33C0 DCH4DSIZ
3410
DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED)
0000
0000
PIC32MX5XX/6XX/7XX
DS61156C-page 78
TABLE 4-19:
Virtual Address
(BF88_#)
34E0 DCH6CON
34F0 DCH6ECON
3500
3510
DCH6INT
DCH6SSA
3520 DCH6DSA
3530 DCH6SSIZ
3550 DCH6SPTR
3560 DCH6DPTR
3570 DCH6CSIZ
3580 DCH6CPTR
DCH6DAT
35A0 DCH7CON
35B0 DCH7ECON
35C0
DCH7INT
35D0 DCH7SSA
DS61156C-page 79
35E0 DCH7DSA
35F0 DCH7SSIZ
24/8
30/14
29/13
28/12
27/11
26/10
25/9
31:16
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
0000
CHSIRQ<7:0>
15:0
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
CHCHN
CHAEN
—
—
—
—
—
CHEDET
CHPRI<1:0>
CHAIRQ<7:0>
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
31:16
31:16
31:16
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCPTR<15:0>
0000
0000
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
FF00
15:0
CHSIRQ<7:0>
—
0000
0000
CHCSIZ<15:0>
15:0
0000
0000
CHDPTR<15:0>
15:0
31:16
0000
—
CHSPTR<15:0>
15:0
31:16
—
CHDSIZ<15:0>
15:0
31:16
—
CHSSIZ<15:0>
15:0
31:16
0000
0000
CHDSA<31:0>
15:0
0000
0000
CHSSA<31:0>
15:0
0000
0000
00FF
CHPDAT<7:0>
0000
0000
—
—
CHPRI<1:0>
CHAIRQ<7:0>
0000
0000
00FF
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
31:16
31:16
15:0
0000
0000
CHDSA<31:0>
15:0
31:16
0000
CHSSA<31:0>
15:0
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
CHSSIZ<15:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
All Resets
Bit Range
31/15
0000
0000
PIC32MX5XX/6XX/7XX
Preliminary
3540 DCH6DSIZ
3590
DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED)
Bits
Register
Name
 2010 Microchip Technology Inc.
TABLE 4-19:
Virtual Address
(BF88_#)
3610 DCH7SPTR
3620 DCH7DPTR
3630 DCH7CSIZ
3640 DCH7CPTR
DCH7DAT
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
CHPDAT<7:0>
Preliminary
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
0000
0000
CHCPTR<15:0>
31:16
0000
0000
CHCSIZ<15:0>
15:0
0000
0000
CHDPTR<15:0>
15:0
31:16
22/6
CHSPTR<15:0>
15:0
31:16
23/7
CHDSIZ<15:0>
15:0
31:16
24/8
All Resets
Bit Range
Register
Name
Bits
3600 DCH7DSIZ
3650
DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED)
0000
0000
PIC32MX5XX/6XX/7XX
DS61156C-page 80
TABLE 4-19:
 2010 Microchip Technology Inc.
Virtual Address
(BF80_#)
A000 CM1CON
A010 CM2CON
CMSTAT
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
—
31:16
—
—
—
—
—
—
—
—
15:0
ON
COE
CPOL
—
—
—
—
COUT
31:16
—
—
—
—
—
—
—
—
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
EVPOL<1:0>
—
CREF
—
—
—
—
—
—
—
—
CCH<1:0>
—
—
CCH<1:0>
0000
0000
15:0
ON
COE
CPOL
—
—
—
—
COUT
EVPOL<1:0>
—
CREF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
FRZ
SIDL
—
—
—
—
—
—
—
—
—
—
—
C2OUT
C1OUT
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
0000
COMPARATOR VOLTAGE REFERENCE REGISTER MAP(1)
TABLE 4-21:
Register
Name
Bit Range
Bits
9800 CVRCON
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
—
—
—
—
—
—
—
—
—
15:0
ON
—
—
—
—
—
—
—
—
CVROE
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
CVRR
CVRSS
CVR<3:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
0000
0000
DS61156C-page 81
PIC32MX5XX/6XX/7XX
Preliminary
Virtual Address
(BF80_#)
0000
31:16
Legend:
1:
All Resets
31/15
All Resets
A060
Bit Range
Bits
Register
Name
 2010 Microchip Technology Inc.
COMPARATOR REGISTER MAP(1)
TABLE 4-20:
Virtual Address
(BF80_#)
FLASH CONTROLLER REGISTER MAP
F400 NVMCON(1)
F410
NVMKEY
(1)
F420 NVMADDR
F430
NVMDATA
F440
NVMSRC
ADDR
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
WR
WREN
WRERR
LVDERR
LVDSTAT
—
—
—
—
—
—
—
31:16
NVMOP<3:0>
31:16
0000
0000
0000
NVMADDR<31:0>
15:0
31:16
0000
0000
NVMDATA<31:0>
15:0
31:16
0000
0000
NVMSRCADDR<31:0>
15:0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
Virtual Address
(BF80_#)
F000 OSCCON
OSCTUN
0000 WDTCON
 2010 Microchip Technology Inc.
F600
RCON
F610 RSWRST
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
—
15:0
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
PLLODIV<2:0>
COSC<2:0>
—
25/9
24/8
21/5
20/4
19/3
18/2
23/7
22/6
RCDIV<2:0>
—
SOSCRDY
—
NOSC<2:0>
CLKLOCK
ULOCK
LOCK
SLPEN
CF
UFRCEN
SOSCEN
OSWEN
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
0000
PBDIV<1:0>
17/1
All Resets(2)
Bit Range
Bits
Register
Name
Preliminary
SYSTEM CONTROL REGISTER MAP(1,2)
TABLE 4-23:
F010
0000
0000
NVMKEY<31:0>
15:0
All Resets
Register
Name
Bit Range
Bits
16/0
PLLMULT<2:0>
0000
TUN<5:0>
—
—
—
SWDTPS<4:0>
0000
15:0
ON
—
—
—
—
—
—
—
—
—
WDTCLR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
CM
VREGS
EXTR
SWR
—
WDTO
SLEEP
IDLE
BOR
POR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SWRST
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
1:
2:
PIC32MX5XX/6XX/7XX
DS61156C-page 82
TABLE 4-22:
Virtual Address
(BF88_#)
Register
Name
6000
TRISA
6020
LATA
6030
ODCA
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
TRISA15
TRISA14
—
—
—
TRISA10
TRISA9
—
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
C6FF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RA15
RA14
—
—
—
RA10
RA9
—
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATA15
LATA14
—
—
—
LATA10
LATA9
—
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCA15
ODCA14
—
—
—
ODCA10
ODCA9
—
ODCA7
ODCA6
ODCA5
ODCA4
ODCA3
ODCA2
ODCA1
ODCA0
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
Virtual Address
(BF88_#)
Register
Name
TRISB
6050
PORTB
6060
LATB
6070
ODCB
PORTB REGISTER MAP(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
TRISB15
TRISB14
TRISB13
TRISB12
TRISB11
TRISB10
TRISB9
TRISB8
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
FFFF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATB15
LATB14
LATB13
LATB12
LATB11
LATB10
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCB15
ODCB14
ODCB13
ODCB12
ODCB11
ODCB10
ODCB9
ODCB8
ODCB7
ODCB6
ODCB5
ODCB4
ODCB3
ODCB2
ODCB1
ODCB0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
0000
DS61156C-page 83
PIC32MX5XX/6XX/7XX
Preliminary
TABLE 4-25:
6040
0000
31:16
Legend:
1:
All Resets
Bit Range
PORTA
31/15
All Resets
6010
PORTA REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits
Bit Range
 2010 Microchip Technology Inc.
TABLE 4-24:
Virtual Address
(BF88_#)
Register
Name
6080
TRISC
PORTC
60A0
LATC
60B0
ODCC
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
TRISC15
TRISC14
TRISC13
TRISC12
—
—
—
—
—
—
—
—
—
—
—
—
F000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RC15
RC14
RC13
RC12
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATC15
LATC14
LATC13
LATC12
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCC15
ODCC14
ODCC13
ODCC12
—
—
—
—
—
—
—
—
—
—
—
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
Virtual Address
(BF88_#)
Register
Name
TRISC
6090 PORTC
 2010 Microchip Technology Inc.
60A0
60B0
PORTC REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits
Bit Range
Preliminary
TABLE 4-27:
6080
All Resets
Bit Range
Bits
LATC
ODCC
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
TRISC15
TRISC14
TRISC13
TRISC12
—
—
—
—
—
—
—
TRISC4
TRISC3
TRISC2
TRISC1
—
F00F
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RC15
RC14
RC13
RC12
—
—
—
—
—
—
—
RC4
RC3
RC2
RC1
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATC15
LATC14
LATC13
LATC12
—
—
—
—
—
—
—
LATC4
LATC3
LATC2
LATC1
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCC15
ODCC14
ODCC13
ODCC12
—
—
—
—
—
—
—
ODCC4
ODCC3
ODCC2
ODCC1
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
All Resets
6090
PORTC REGISTER MAP FOR PIC32MX575F256H, PIC32MX675F256H, PIC32MX575F512H, PIC32MX675F512H,
PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
PIC32MX5XX/6XX/7XX
DS61156C-page 84
TABLE 4-26:
Virtual Address
(BF88_#)
Register
Name
60C0
TRISD
60D0
PORTD
60E0
LATD
60F0
ODCD
PORTD REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H,
PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31/15
30/14
29/13
28/12
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
TRISD11
TRISD10
TRISD9
TRISD8
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
0FFF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
RD11
RD10
RD9
RD8
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
LATD11
LATD10
LATD9
LATD8
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
ODCD11
ODCD10
ODCD9
ODCD8
ODCD7
ODCD6
ODCD5
ODCD4
ODCD3
ODCD2
ODCD1
ODCD0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
Register
Name
TRISD
PORTD REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
60D0 PORTD
60E0
LATD
60F0
ODCD
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
TRISD15
TRISD14
TRISD13
TRISD12
TRISD11
TRISD10
TRISD9
TRISD8
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
FFFF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RD15
RD14
RD13
RD12
RD11
RD10
RD9
RD8
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LAT15
LAT14
LAT13
LAT12
LATD11
LATD10
LATD9
LATD8
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCD15
ODCD14
ODCD13
ODCD12
ODCD11
ODCD10
ODCD9
ODCD8
ODCD7
ODCD6
ODCD5
ODCD4
ODCD3
ODCD2
ODCD1
ODCD0
0000
DS61156C-page 85
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
All Resets
Bit Range
Bits
PIC32MX5XX/6XX/7XX
Preliminary
TABLE 4-29:
60C0
All Resets
Bit Range
Bits
Virtual Address
(BF88_#)
 2010 Microchip Technology Inc.
TABLE 4-28:
Virtual Address
(BF88_#)
Register
Name
6100
TRISE
PORTE REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H,
PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
6110
PORTE
6120
LATE
6130
ODCE
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
00FF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
xxxx
15:0
—
—
—
—
—
—
—
—
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
ODCE7
0DCE6
ODCE5
ODCE4
ODCE3
ODCE2
ODCE1
ODCE0
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
Virtual Address
(BF88_#)
Register
Name
TRISE
6110
PORTE
6120
LATE
6130
ODCE
PORTE REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
TRISE9
TRISE8
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
03FF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
RE9
RE8
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
LATE9
LATE8
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
ODCE9
ODCE8
ODCE7
0DCE6
ODCE5
ODCE4
ODCE3
ODCE2
ODCE1
ODCE0
0000
DS61156C-page 86
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
All Resets
Bits
PIC32MX5XX/6XX/7XX
Preliminary
TABLE 4-31:
6100
0000
31:16
Legend:
1:
All Resets
Bit Range
Bits
Bit Range
 2010 Microchip Technology Inc.
TABLE 4-30:
Virtual Address
(BF88_#)
Register
Name
6140
TRISF
PORTF REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H,
PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
6150 PORTF
6160
LATF
6170
ODCF
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
TRISF5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
RF5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
LATF5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
ODCF5
20/4
17/1
16/0
19/3
18/2
—
—
—
—
—
0000
TRISF4
TRISF3
—
TRISF1
TRISF0
003B
—
—
—
—
—
0000
RF4
RF3
—
RF1
RF0
xxxx
—
—
—
—
—
0000
LATF4
LATF3
—
LATF1
LATF0
xxxx
—
—
—
—
—
0000
ODCF4
ODCF3
—
ODCF1
ODCF0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
Register
Name
6140
TRISF
6150
PORTF
6160
LATF
6170
ODCF
PORTF REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
31/15
30/14
31:16
—
—
15:0
—
—
31:16
—
—
29/13
28/12
27/11
26/10
25/9
—
—
—
—
TRISF13
TRISF12
—
—
—
—
—
21/5
20/4
19/3
18/2
17/1
16/0
24/8
23/7
22/6
—
—
—
—
—
—
—
—
—
—
—
TRISF8
—
—
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0
313F
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
—
—
RF13
RF12
—
—
—
RF8
—
—
RF5
RF4
RF3
RF2
RF1
RF0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
LATF13
LATF12
—
—
—
LATF8
—
—
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
ODCF13
ODCF12
—
—
—
ODCF8
—
—
ODCF5
ODCF4
ODCF3
ODCF2
ODCF1
ODCF0
0000
DS61156C-page 87
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
All Resets
Bit Range
Bits
PIC32MX5XX/6XX/7XX
Preliminary
TABLE 4-33:
All Resets
Bit Range
Bits
Virtual Address
(BF88_#)
 2010 Microchip Technology Inc.
TABLE 4-32:
Virtual Address
(BF88_#)
Register
Name
6180
TRISG
61A0
LATG
ODCG
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
TRISG9
TRISG8
—
—
—
—
TRISG7
TRISG6
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
RG9
RG8
RG7
RG6
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
LATG9
LATG8
LATG7
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
ODCG9
ODCG8
19/3
18/2
17/1
16/0
—
—
—
—
0000
TRISG3
TRISG2
—
—
03CC
—
—
—
—
0000
—
RG3
RG2
—
—
xxxx
—
—
—
—
—
—
0000
LATG6
—
—
LATG3
LATG2
—
—
xxxx
—
—
—
—
—
—
—
—
0000
ODCG7
ODCG6
—
—
ODCG3
ODCG2
—
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
Virtual Address
(BF88_#)
Register
Name
6180
TRISG
PORTG REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
6190 PORTG
 2010 Microchip Technology Inc.
61A0
LATG
61B0
ODCG
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
TRISG15
TRISG14
TRISG13
TRISG12
—
—
TRISG9
TRISG8
TRISG7
TRISG6
—
—
TRISG3
TRISG2
TRISG1
TRISG0
F3CF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
RG15
RG14
RG13
RG12
—
—
RG9
RG8
RG7
RG6
—
—
RG3
RG2
RG1
RG0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATG15
LATG14
LATG13
LATG12
—
—
LATG9
LATG8
LATG7
LATG6
—
—
LATG3
LATG2
LATG1
LATG0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCG15
ODCG14
ODCG13
ODCG12
—
—
ODCG9
ODCG8
ODCG7
ODCG6
—
—
ODCG3
ODCG2
ODCG1
ODCG0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
All Resets
Bits
Bit Range
Preliminary
TABLE 4-35:
All Resets
Bit Range
Bits
6190 PORTG
61B0
PORTG REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H,
PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
PIC32MX5XX/6XX/7XX
DS61156C-page 88
TABLE 4-34:
Virtual Address
(BF88_#)
CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L,
PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512 AND PIC32MX795F512L DEVICES(1)
61C0 CNCON
61D0
CNEN
61E0
CNPUE
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
CNEN21
CNEN20
CNEN19
CNEN18
CNEN17
CNEN16
0000
15:0
CNEN15
CNEN14
CNEN13
CNEN12
CNEN11
CNEN10
CNEN9
CNEN8
CNEN7
CNEN6
CNEN5
CNEN4
CNEN3
CNEN2
CNEN1
CNEN0
0000
31:16
—
—
—
—
—
—
—
—
—
—
CNPUE21
CNPUE20
CNPUE19 CNPUE18 CNPUE17 CNPUE16 0000
CNPUE9
CNPUE8
CNPUE7
CNPUE6
CNPUE5
CNPUE4
CNPUE3
15:0
CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10
CNPUE2
CNPUE1
CNPUE0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
0000
CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H,
PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
61C0 CNCON
61D0
CNEN
61E0
CNPUE
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
CNEN18
CNEN17
CNEN16
0000
15:0
CNEN15
CNEN14
CNEN13
CNEN12
CNEN11
CNEN10
CNEN9
CNEN8
CNEN7
CNEN6
CNEN5
CNEN4
CNEN3
CNEN2
CNEN1
CNEN0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPUE9
CNPUE8
CNPUE7
CNPUE6
CNPUE5
CNPUE4
CNPUE3
15:0
CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10
CNPUE18 CNPUE17 CNPUE16 0000
CNPUE2
CNPUE1
CNPUE0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
1:
All Resets
Bit Range
Register
Name
Bits
0000
DS61156C-page 89
PIC32MX5XX/6XX/7XX
Preliminary
TABLE 4-37:
Virtual Address
(BF88_#)
All Resets
Bit Range
Bits
Register
Name
 2010 Microchip Technology Inc.
TABLE 4-36:
Virtual Address
(BF80_#)
Register
Name
7000
PMCON
7010 PMMODE
7020 PMADDR
7030 PMDOUT
PMDIN
7050
PMAEN
PMSTAT
29/13
31:16
—
—
—
15:0
ON
FRZ
SIDL
31:16
—
—
—
15:0
BUSY
31:16
—
IRQM<1:0>
—
—
28/12
27/11
—
—
ADRMUX<1:0>
—
—
INCM<1:0>
—
—
26/10
25/9
24/8
23/7
22/6
—
—
—
—
—
PMPTTL
PTWREN
PTRDEN
—
—
—
MODE16
—
—
MODE<1:0>
—
—
—
—
—
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
0000
ALP
CS2P
CS1P
—
WRSP
RDSP
0000
—
—
—
—
—
—
0000
WAITB<1:0>
15:0 CS2EN/A15 CS1EN/A14
WAITM<3:0>
—
—
—
WAITE<1:0>
—
—
—
ADDR<13:0>
31:16
31:16
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
15:0
—
0000
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
0080
PTEN<15:0>
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-39:
PROGRAMMING AND DIAGNOSTICS REGISTER MAP
Bit Range
Register
Name
Bits
F200 DDPCON
 2010 Microchip Technology Inc.
Legend:
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
0000
0000
DATAIN<31:0>
15:0
0000
0000
DATAOUT<31:0>
15:0
31:16
CSF<1:0>
21/5
All Resets
30/14
Legend:
Virtual Address
(BF80_#)
Preliminary
7060
31/15
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
19/3
All Resets
7040
Bit Range
Bits
18/2
17/1
16/0
—
—
—
—
0000
JTAGEN
TROEN
—
—
0008
PIC32MX5XX/6XX/7XX
DS61156C-page 90
PARALLEL MASTER PORT REGISTER MAP(1)
TABLE 4-38:
Virtual Address
(BF88_#)
PREFETCH REGISTER MAP
4000 CHECON(1,2)
4010 CHEACC
(1)
4020 CHETAG(1)
4030 CHEMSK(1)
4040
CHEW0
4050
CHEW1
CHEW2
4070
CHEW3
4080
CHELRU
4090
CHEHIT
40A0
CHEMIS
40C0 CHEPFABT
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16 CHEWEN
15:0
—
31:16 LTAGBOOT
15:0
31:16
DCSZ<1:0>
—
—
—
—
—
—
—
31:16
31:16
31:16
31:16
15:0
—
—
—
PREFEN<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
CHECOH 0000
PFMWS<2:0>
—
—
0000
—
CHEIDX<3:0>
LTAG<23:16>
—
—
—
—
—
—
—
—
—
—
00xx
LVALID
LLOCK
LTYPE
—
xxx0
—
—
—
—
—
0000
—
—
—
—
—
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
CHELRU<24:16>
0000
CHELRU<15:0>
0000
CHEHIT<31:0>
xxxx
CHEMIS<31:0>
CHEPFABT<31:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
Reset value is dependent on DEVCFGx configuration.
1:
2:
0000
0000
CHEW3<31:0>
15:0
15:0
—
—
16/0
CHEW2<31:0>
15:0
31:16
—
17/1
CHEW1<31:0>
15:0
15:0
18/2
CHEW0<31:0>
15:0
31:16
19/3
LMASK<15:5>
31:16
15:0
20/4
LTAG<15:4>
15:0
31:16
21/5
xxxx
xxxx
xxxx
xxxx
xxxx
DS61156C-page 91
PIC32MX5XX/6XX/7XX
Preliminary
4060
31/15
All Resets
Bit Range
Bits
Register
Name
 2010 Microchip Technology Inc.
TABLE 4-40:
Virtual Address
(BF80_#)
Register
Name
0200
RTCCON
0210 RTCALRM
0220
RTCTIME
0230 RTCDATE
0240 ALRMTIME
0250 ALRMDATE
Legend:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
ALRMEN
CHIME
PIV
ALRMSYNC
HR01<3:0>
15:0
SEC10<3:0>
SEC01<3:0>
31:16
YEAR10<3:0>
YEAR01<3:0>
15:0
DAY10<3:0>
DAY01<3:0>
31:16
HR10<3:0>
HR01<3:0>
15:0
SEC10<3:0>
SEC01<3:0>
—
—
—
DAY10<3:0>
—
21/5
RTSECSEL RTCCLKON
—
—
20/4
19/3
18/2
17/1
16/0
—
—
—
0000
—
—
—
—
AMASK<3:0>
HR10<3:0>
15:0
22/6
CAL<9:0>
31:16
31:16
23/7
RTCWREN RTCSYNC HALFSEC
—
—
—
RTCOE
0000
—
0000
ARPT<7:0>
MIN10<3:0>
—
—
—
—
—
—
—
—
—
—
MIN10<3:0>
—
DAY01<3:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
—
—
xxxx
—
—
—
xx00
MONTH01<3:0>
xxxx
WDAY01<3:0>
xx00
MIN01<3:0>
—
MONTH10<3:0>
—
0000
MIN01<3:0>
MONTH10<3:0>
—
All Resets
Bit Range
Bits
—
—
xxxx
—
xx00
MONTH01<3:0>
00xx
WDAY01<3:0>
xx0x
Preliminary
PIC32MX5XX/6XX/7XX
DS61156C-page 92
RTCC REGISTER MAP(1)
TABLE 4-41:
 2010 Microchip Technology Inc.
DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
2FF0 DEVCFG3
2FF4 DEVCFG2
2FF8 DEVCFG1
2FFC DEVCFG0
Legend:
31/15
30/14
31:16 FVBUSIO FUSBIDIO
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
FSCMIO
—
—
FCANIO
FETHIO
FMIIEN
—
—
—
—
—
FSRSSEL<2:0>
xxxx
—
—
—
—
FPLLODIV<2:0>
xxxx
15:0
18/2
17/1
16/0
USERID<15:0>
31:16
—
—
—
—
—
15:0
FUPLLEN
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
FWDTEN
—
—
FUPLLIDIV<2:0>
—
xxxx
—
—
FPLLMULT<2:0>
—
15:0
FCKSM<1:0>
FPBDIV<1:0>
—
OSCIOFNC
IESO
—
FSOSCEN
—
—
—
—
—
—
BWP
—
—
—
—
—
—
—
—
—
—
—
—
23/7
22/6
21/5
20/4
15:0
CP
PWP<3:0>
POSCMOD<1:0>
FPLLIDIV<2:0>
xxxx
WDTPS<4:0>
31:16
—
All Resets
Bit Range
Bits
Register
Name
—
xxxx
FNOSC<2:0>
xxxx
PWP<7:4>
ICESEL
—
xxxx
DEBUG<1:0>
xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Register
Name
F220
DEVID
DEVICE AND REVISION ID SUMMARY(1)
Legend:
Note
1:
31:16
15:0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
VER<3:0>
19/3
DEVID<27:16>
DEVID<15:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset values are dependent on the device variant. Refer to the “PIC32MX5XX/6XX/7XX Family Silicon Errata and Data Sheet Clarification” (DS80480) for more information.
18/2
17/1
16/0
All Resets
Bits
xxxx
xxxx
DS61156C-page 93
PIC32MX5XX/6XX/7XX
Preliminary
Virtual Address
(BF80_#)
TABLE 4-43:
Bit Range
Virtual Address
(BFC0_#)
 2010 Microchip Technology Inc.
TABLE 4-42:
Virtual Address
(BF88_#)
Register
Name
5040
U1OTGIR
5050
U1OTGIE
5070 U1OTGCON
5080
U1PWRC
5200
U1IR
Preliminary
5220
5230
5240
5250
U1IE
U1EIR
U1EIE
U1STAT
U1CON
 2010 Microchip Technology Inc.
5260
U1ADDR
5270
U1BDTP1
5280
U1FRML
5290
U1FRMH
52A0
U1TOK
Legend:
23/7
22/6
21/5
—
—
20/4
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
IDIF
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
IDIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
ID
—
LSTATE
—
SESVD
SESEND
—
VBUSVD
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
UACTPND
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
T1MSECIF LSTATEIF
—
ACTVIF
—
18/2
17/1
—
—
—
SESVDIF SESENDIF
—
T1MSECIE LSTATEIE
19/3
—
ACTVIE
—
—
—
—
—
—
—
—
—
STALLIF
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
STALLIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
ATTACHIE RESUMEIE
—
—
—
—
0000
—
0000
VBUSVDIE 0000
—
—
—
0000
VBUSCHG
VBUSDIS
0000
—
—
—
—
—
VBUSVDIF 0000
OTGEN
—
USLPGRD USBBUSY
ATTACHIF RESUMEIF
—
SESVDIE SESENDIE
DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON
15:0
—
16/0
All Resets
Bit Range
Bits
5060 U1OTGSTAT
5210
USB REGISTER MAP
USUSPEND USBPWR
—
—
IDLEIF
TRNIF
SOFIF
UERRIF
—
—
—
—
IDLEIE
TRNIE
SOFIE
UERRIE
—
—
—
—
15:0
—
—
—
—
—
—
—
—
BTSEF
BMXEF
DMAEF
BTOEF
DFN8EF
CRC16EF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CRC5EF
EOFEF
—
CRC5EE
0000
0000
—
0000
URSTIF
0000
DETACHIF 0000
—
0000
URSTIE
0000
DETACHIE 0000
—
PIDEF
—
0000
0000
0000
0000
0000
15:0
—
—
—
—
—
—
—
—
BTSEE
BMXEE
DMAEE
BTOEE
DFN8EE
CRC16EE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
DIR
PPBI
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
USBEN
0000
SOFEN
0000
ENDPT<3:0>
—
PKTDIS
—
15:0
—
—
—
—
—
—
—
—
JSTATE
SE0
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
LSPDEN
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TOKBUSY
—
EOFEE
USBRST
HOSTEN
RESUME
PPBRST
—
—
—
—
—
DEVADDR<6:0>
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
0000
—
0000
—
FRML<7:0>
PID<3:0>
0000
0000
BDTPTRL<7:1>
—
PIDEE
0000
0000
—
—
—
FRMH<2:0>
—
—
EP<3:0>
0000
0000
—
0000
0000
PIC32MX5XX/6XX/7XX
DS61156C-page 94
TABLE 4-44:
Register
Name
DS61156C-page 95
52B0
U1SOF
52C0
U1BDTP2
52D0
U1BDTP3
52E0
U1CNFG1
5300
U1EP0
5310
U1EP1
5320
U1EP2
5330
U1EP3
5340
U1EP4
5350
U1EP5
5360
U1EP6
5370
U1EP7
5380
U1EP8
5390
U1EP9
53A0
U1EP10
53B0
U1EP11
53C0
U1EP12
53D0
U1EP13
Legend:
USB REGISTER MAP (CONTINUED)
All Resets
Bit Range
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
UTEYE
UOEMON
USBFRZ
USBSIDL
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
LSPD
RETRYDIS
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
CNT<7:0>
—
—
—
—
—
—
—
—
BDTPTRH<7:0>
—
—
—
—
0000
0000
—
0000
0000
—
—
—
BDTPTRU<7:0>
0000
0000
—
0000
UASUSPND 0001
PIC32MX5XX/6XX/7XX
Preliminary
Virtual Address
(BF88_#)
 2010 Microchip Technology Inc.
TABLE 4-44:
Virtual Address
(BF88_#)
Register
Name
53E0
U1EP14
53F0
U1EP15
Legend:
USB REGISTER MAP (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Bits
Preliminary
PIC32MX5XX/6XX/7XX
DS61156C-page 96
TABLE 4-44:
 2010 Microchip Technology Inc.
Virtual Address
(BF88_#)
Register
Name
B000
C1CON
B010
C1CFG
C1INT
B030
B060
C1TREC
C1FSTAT
C1RXOVF
B070
B080
B090
B0A0
B0B0
C1TMR
C1RXM0
C1RXM1
C1RXM2
C1RXM3
B0C0 C1FLTCON0
B0D0 C1FLTCON1
B0E0 C1FLTCON2
DS61156C-page 97
B0F0 C1FLTCON3
B100 C1FLTCON4
Legend:
Note
1:
30/14
31:16
—
15:0
ON
31:16
—
15:0 SEG2PHTS
29/13
28/12
—
—
—
ABAT
—
SIDLE
—
BUSY
—
—
—
—
—
—
SAM
27/11
26/10
25/9
24/8
23/7
—
—
—
—
—
—
—
—
WAKFIL
—
REQOP<2:0>
SEG1PH<2:0>
22/6
21/5
OPMOD<2:0>
PRSEG<2:0>
20/4
19/3
CANCAP
—
18/2
17/1
16/0
—
—
—
DNCNT<4:0>
—
—
SJW<1:0>
0400
0000
SEG2PH<2:0>
0000
BRP<5:0>
0000
31:16
IVRIE
WAKIE
CERRIE
SERRIE
RBOVIE
—
—
—
—
—
—
—
MODIE
CTMRIE
RBIE
TBIE
15:0
IVRIF
WAKIF
CERRIF
SERRIF
RBOVIF
—
—
—
—
—
—
—
MODIF
CTMRIF
RBIF
TBIF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
TXBO
TXBP
TXWARN
RXWARN
FIFOIP24
FIFOIP23
FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18
FIFOIP17 FIFOIP16 0000
FIFOIP7
FIFOIP6
FIFOIP1
15:0
FILHIT<4:0>
—
ICOD<6:0>
TEC<7:0>
0000
EWARN 0000
REC<7:0>
31:16 FIFOIP31
FIFOIP30
FIFOIP29 FIFOIP28 FIFOIP27
FIFOIP26
FIFOIP25
15:0
FIFOIP14
FIFOIP13 FIFOIP12 FIFOIP11
FIFOIP10
FIFOIP9
FIFOIP15
RXBP
FIFOIP8
FIFOIP5
FIFOIP4
0000
0000
FIFOIP3
FIFOIP2
FIFOIP0 0000
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25
RXOVF24
RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10
RXOVF8
RXOVF7
31:16
RXOVF9
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0 0000
CANTS<15:0>
15:0
0000
CANTSPRE<15:0>
31:16
0000
SID<10:0>
15:0
-—
MIDE
—
EID<17:16>
xxxx
-—
MIDE
—
EID<17:16>
xxxx
xxxx
-—
MIDE
—
EID<17:16>
xxxx
-—
MIDE
—
EID<17:16>
xxxx
EID<15:0>
31:16
xxxx
SID<10:0>
15:0
EID<15:0>
31:16
SID<10:0>
15:0
EID<15:0>
31:16
xxxx
SID<10:0>
15:0
EID<15:0>
31:16
FLTEN3
MSEL3<1:0>
FSEL3<4:0>
FLTEN2
xxxx
MSEL2<1:0>
FSEL2<4:0>
0000
15:0
FLTEN1
MSEL1<1:0>
FSEL1<4:0>
FLTEN0
MSEL0<1:0>
FSEL0<4:0>
0000
31:16
FLTEN7
MSEL7<1:0>
FSEL7<4:0>
FLTEN6
MSEL6<1:0>
FSEL6<4:0>
0000
15:0
FLTEN5
MSEL5<1:0>
FSEL5<4:0>
FLTEN4
MSEL4<1:0>
FSEL4<4:0>
0000
31:16 FLTEN11
MSEL11<1:0>
FSEL11<4:0>
FLTEN10
MSEL10<1:0>
FSEL10<4:0>
0000
FLTEN9
MSEL9<1:0>
FSEL9<4:0>
FLTEN8
MSEL8<1:0>
FSEL8<4:0>
0000
31:16 FLTEN15
15:0
MSEL15<1:0>
FSEL15<4:0>
FLTEN14
MSEL14<1:0>
FSEL14<4:0>
0000
FLTEN13
MSEL13<1:0>
FSEL13<4:0>
FLTEN12
MSEL12<1:0>
FSEL12<4:0>
0000
31:16 FLTEN19
15:0
MSEL19<1:0>
FSEL19<4:0>
FLTEN18
MSEL18<1:0>
FSEL18<4:0>
0000
15:0
MSEL17<1:0>
FSEL17<4:0>
FLTEN16
MSEL16<1:0>
FSEL16<4:0:
0000
FLTEN17
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
PIC32MX5XX/6XX/7XX
Preliminary
B050
C1VEC
31/15
All Resets
Bits
B020
B040
CAN1 REGISTER SUMMARY FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX575F256L, PIC32MX575F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L
DEVICES(1)
Bit Range
 2010 Microchip Technology Inc.
TABLE 4-45:
Virtual Address
(BF88_#)
B120 C1FLTCON6
B130 C1FLTCON7
B340
C1RXFn
(n = 0-31)
C1FIFOBA
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
20/4
19/3
18/2
17/1
16/0
MSEL23<1:0>
FSEL23<4:0>
FLTEN22
MSEL22<1:0>
FSEL22<4:0>
FLTEN21
MSEL21<1:0>
FSEL21<4:0>
FLTEN20
MSEL20<1:0>
FSEL20<4:0>
0000
31:16 FLTEN27
MSEL27<1:0>
FSEL27<4:0>
FLTEN26
MSEL26<1:0>
FSEL26<4:0>
0000
15:0
0000
FLTEN25
MSEL25<1:0>
FSEL25<4:0>
FLTEN24
MSEL24<1:0>
FSEL24<4:0>
0000
31:16 FLTEN31
MSEL31<1:0>
FSEL31<4:0>
FLTEN30
MSEL30<1:0>
FSEL30<4:0>
0000
15:0
MSEL29<1:0>
FSEL29<4:0>
FLTEN28
MSEL28<1:0>
FSEL28<4:0>
FLTEN29
31:16
SID<10:0>
-—
15:0
Preliminary
—
—
—
—
FRESET
UINC
DONLY
—
31:16
—
—
—
—
—
TXNFULLIE TXHALFIE TXEMPTYIE
15:0
—
—
—
—
—
TXNFULLIF TXHALFIF TXEMPTYIF
C1FIFOUAn 31:16
(n = 0-31)
15:0
B380
C1FIFOCIn 31:16
(n = 0-31)
15:0
—
0000
EID<17:16>
xxxx
xxxx
0000
C1FIFOBA<31:0>
15:0
B370
EXID
EID<15:0>
31:16
—
Legend:
Note
1:
21/5
15:0
—
C1FIFOINTn
(n = 0-31)
22/6
31:16 FLTEN23
C1FIFOCONn 31:16
B350
(n = 0-31)
15:0
B360
23/7
All Resets
Bit Range
Register
Name
Bits
B110 C1FLTCON5
B140
CAN1 REGISTER SUMMARY FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX575F256L, PIC32MX575F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L
DEVICES(1) (CONTINUED)
0000
—
—
—
—
—
—
FSIZE<4:0>
—
—
—
TXEN
TXABAT
TXLARB
TXERR
—
—
—
—
RXOVFLIE RXFULLIE RXHALFIE
RXN
0000
EMPTYIE
—
—
—
—
RXOVFLIF RXFULLIF RXHALFIF
RXN
0000
EMPTYIF
TXREQ
RTREN
0000
TXPRI<1:0>
0000
0000
C1FIFOUA<31:0>
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C1FIFOCI<4:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
0000
0000
PIC32MX5XX/6XX/7XX
DS61156C-page 98
TABLE 4-45:
 2010 Microchip Technology Inc.
Virtual Address
(BF88_#)
Register
Name
C000
C2CON
C010
C2CFG
C040
C060
C070
C080
C0A0
C0B0
C0B0
C2VEC
C2TREC
C2FSTAT
C2RXOVF
C2TMR
C2RXM0
C2RXM1
C2RXM2
C2RXM3
C0C0 C2FLTCON0
C0D0 C2FLTCON1
C0E0 C2FLTCON2
DS61156C-page 99
C0F0 C2FLTCON3
Legend:
Note
1:
30/14
31:16
—
15:0
ON
31:16
—
15:0 SEG2PHTS
29/13
28/12
—
—
—
ABAT
—
SIDLE
—
BUSY
—
—
—
—
—
—
SAM
27/11
26/10
25/9
24/8
23/7
—
—
—
—
—
—
—
—
WAKFIL
—
REQOP<2:0>
SEG1PH<2:0>
22/6
21/5
OPMOD<2:0>
PRSEG<2:0>
20/4
19/3
CANCAP
—
18/2
17/1
16/0
—
—
—
DNCNT<4:0>
—
—
SJW<1:0>
0400
0000
SEG2PH<2:0>
0000
BRP<5:0>
0000
31:16
IVRIE
WAKIE
CERRIE
SERRIE
RBOVIE
—
—
—
—
—
—
—
MODIE
CTMRIE
RBIE
TBIE
15:0
IVRIF
WAKIF
CERRIF
SERRIF
RBOVIF
—
—
—
—
—
—
—
MODIF
CTMRIF
RBIF
TBIF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
TXBO
TXBP
TXWARN
RXWARN
EWARN
0000
FIFOIP24
FIFOIP23
FIFOIP22
FIFOIP21
FIFOIP20
FIFOIP19
FIFOIP18
FIFOIP17 FIFOIP16 0000
FIFOIP7
FIFOIP6
FIFOIP5
FIFOIP4
FIFOIP3
FIFOIP2
FIFOIP1
15:0
FILHIT<4:0>
—
ICOD<6:0>
TEC<7:0>
0000
REC<7:0>
31:16 FIFOIP31
FIFOIP30 FIFOIP29 FIFOIP28
FIFOIP27
FIFOIP26
FIFOIP25
15:0
FIFOIP14 FIFOIP13 FIFOIP12
FIFOIP11
FIFOIP10
FIFOIP9
FIFOIP15
RXBP
FIFOIP8
0000
0000
FIFOIP0
0000
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25
RXOVF24
RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10
RXOVF8
RXOVF7
31:16
RXOVF9
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0
CANTS<15:0>
15:0
0000
CANTSPRE<15:0>
31:16
0000
SID<10:0>
15:0
-—
MIDE
—
EID<17:16>
xxxx
-—
MIDE
—
EID<17:16>
xxxx
-—
MIDE
—
EID<17:16>
xxxx
-—
MIDE
—
EID<17:16>
xxxx
EID<15:0>
31:16
xxxx
SID<10:0>
15:0
EID<15:0>
31:16
xxxx
SID<10:0>
15:0
EID<15:0>
31:16
xxxx
SID<10:0>
15:0
0000
EID<15:0>
xxxx
31:16
FLTEN3
MSEL3<1:0>
FSEL3<4:0>
FLTEN2
MSEL2<1:0>
FSEL2<4:0>
0000
15:0
FLTEN1
MSEL1<1:0>
FSEL1<4:0>
FLTEN0
MSEL0<1:0>
FSEL0<4:0>
0000
31:16
FLTEN7
MSEL7<1:0>
FSEL7<4:0>
FLTEN6
MSEL6<1:0>
FSEL6<4:0>
0000
15:0
FLTEN5
MSEL5<1:0>
FSEL5<4:0>
FLTEN4
MSEL4<1:0>
FSEL4<4:0>
0000
31:16 FLTEN11
MSEL11<1:0>
FSEL11<4:0>
FLTEN10
MSEL10<1:0>
FSEL10<4:0>
0000
15:0
FLTEN9
MSEL9<1:0>
FSEL9<4:0>
FLTEN8
MSEL8<1:0>
FSEL8<4:0>
0000
31:16 FLTEN15
MSEL15<1:0>
FSEL15<4:0>
FLTEN14
MSEL14<1:0>
FSEL14<4:0>
0000
15:0
MSEL13<1:0>
FSEL13<4:0>
FLTEN12
MSEL12<1:0>
FSEL12<4:0>
0000
FLTEN13
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
PIC32MX5XX/6XX/7XX
Preliminary
C050
C2INT
31/15
All Resets
Bits
C020
C030
CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bit Range
 2010 Microchip Technology Inc.
TABLE 4-46:
Virtual Address
(BF88_#)
C110 C2FLTCON5
C120 C2FLTCON6
C130 C2FLTCON7
Preliminary
C340
C2RXFn
(n = 0-31)
C2FIFOBA
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
20/4
19/3
18/2
17/1
16/0
MSEL19<1:0>
FSEL19<4:0>
FLTEN18
MSEL18<1:0>
FSEL18<4:0>
0000
FLTEN17
MSEL17<1:0>
FSEL17<4:0>
FLTEN16
MSEL16<1:0>
FSEL16<4:0:
0000
31:16 FLTEN23
MSEL23<1:0>
FSEL23<4:0>
FLTEN22
MSEL22<1:0>
FSEL22<4:0>
0000
15:0
FLTEN21
MSEL21<1:0>
FSEL21<4:0>
FLTEN20
MSEL20<1:0>
FSEL20<4:0>
0000
31:16 FLTEN27
MSEL27<1:0>
FSEL27<4:0>
FLTEN26
MSEL26<1:0>
FSEL26<4:0>
0000
15:0
FLTEN25
MSEL25<1:0>
FSEL25<4:0>
FLTEN24
MSEL24<1:0>
FSEL24<4:0>
0000
31:16 FLTEN31
MSEL31<1:0>
FSEL31<4:0>
FLTEN30
MSEL30<1:0>
FSEL30<4:0>
0000
15:0
MSEL29<1:0>
FSEL29<4:0>
FLTEN28
MSEL28<1:0>
FSEL28<4:0>
FLTEN29
31:16
SID<10:0>
-—
15:0
31:16
15:0
0000
—
FRESET
UINC
DONLY
—
31:16
—
—
—
—
—
TXNFULLIE TXHALFIE TXEMPTYIE
15:0
—
—
—
—
—
TXNFULLIF TXHALFIF TXEMPTYIF
C380
xxxx
0000
—
C2FIFOCIn 31:16
(n = 0-31)
15:0
0000
EID<17:16>
C2FIFOBA<31:0>
—
C2FIFOUAn 31:16
(n = 0-31)
15:0
—
xxxx
—
C370
EXID
EID<15:0>
—
Legend:
Note
1:
21/5
15:0
—
C2FIFOINTn
(n = 0-31)
22/6
31:16 FLTEN19
C2FIFOCONn 31:16
C350
(n = 0-31)
15:0
C360
23/7
All Resets
Bit Range
Register
Name
Bits
C100 C2FLTCON4
C140
CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
—
—
—
—
—
—
FSIZE<4:0>
—
—
—
TXEN
TXABAT
TXLARB
TXERR
—
—
—
—
RXOVFLIE RXFULLIE RXHALFIE
RXN
0000
EMPTYIE
—
—
—
—
RXOVFLIF RXFULLIF RXHALFIF
RXN
0000
EMPTYIF
TXREQ
RTREN
0000
TXPRI<1:0>
0000
0000
C2FIFOUA<31:0>
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C2FIFOCI<4:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
0000
0000
PIC32MX5XX/6XX/7XX
DS61156C-page 100
TABLE 4-46:
 2010 Microchip Technology Inc.
Virtual Address
(BF88_#)
Register
Name
9000
ETHCON1
9010
ETHCON2
9020
9030
9040
Preliminary
9050
9060
9070
9080
9090
90A0
ETHTXST
ETHRXST
ETHHT0
ETHHT1
ETHPMM0
ETHPMM1
ETHPMCS
ETHPMO
ETHRXFC
 2010 Microchip Technology Inc.
90D0
ETHIEN
ETHIRQ
Legend:
Note
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
15:0
ON
FRZ
SIDL
—
—
—
TXRTS
RXEN
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
31:16
21/5
20/4
19/3
18/2
17/1
AUTOFC
—
—
MANFC
—
—
—
16/0
—
—
—
—
—
—
—
—
0000
—
—
—
—
0000
—
—
—
—
0000
RXBUFSZ<6:0>
BUFCDEC 0000
TXSTADDR<31:16>
15:0
0000
TXSTADDR<15:2>
31:16
RXSTADDR<31:16>
15:0
31:16
0000
0000
HT<63:32>
15:0
31:16
0000
0000
PMM<31:0>
15:0
31:16
0000
0000
PMM<63:32>
15:0
—
—
—
—
—
—
—
15:0
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CRC
ERREN
CRC
OKEN
RUNT
ERREN
RUNTEN
UCEN
NOT
MEEN
MCEN
BCEN
0000
PMCS<15:0>
—
—
—
—
—
—
—
15:0
—
—
—
—
—
0000
0000
31:16
—
—
—
—
15:0
HTEN
MPEN
—
NOTPM
31:16
—
—
—
—
—
—
—
—
RXFWM<7:0>
15:0
—
—
—
—
—
—
—
—
RXEWM<7:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
RX
BUSEIE
FW
MARKIE
RX
DONEIE
PK
TPENDIE
PMMODE<3:0>
0000
0000
PMO<15:0>
—
0000
0000
HT<31:0>
15:0
0000
0000
RXSTADDR<15:2>
31:16
31:16
22/6
PTV<15:0>
31:16
31:16
23/7
All Resets
Bit Range
Bits
90B0 ETHRXWM
90C0
ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
0000
0000
—
—
—
—
RX
ACTIE
—
TX
DONEIE
TX
ABORTIE
RX
BUFNAIE
15:0
—
TX
BUSEIE
—
—
—
EW
MARKIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
TXBUSE
RXBUSE
—
—
—
EWMARK
FWMARK
RXDONE
PKTPEND
RXACT
—
TXDONE
TXABORT
RXBUFNA
—
0000
RX
0000
OVFLWIE
—
0000
RXOVFLW 0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
Reset values default to the factory programmed value.
PIC32MX5XX/6XX/7XX
DS61156C-page 101
TABLE 4-47:
Virtual Address
(BF88_#)
Register
Name
90E0
ETHSTAT
ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
Preliminary
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
9100
31:16
ETH
RXOVFLOW 15:0
—
—
—
—
—
—
—
9110
31:16
ETH
FRMTXOK 15:0
—
9120
31:16
ETH
SCOLFRM 15:0
—
9130
31:16
ETH
MCOLFRM 15:0
—
9140
31:16
ETH
FRMRXOK 15:0
—
31:16
—
9150
9160
ETH
FCSERR
23/7
22/6
21/5
20/4
—
BUSY
TXBUSY
RXBUSY
—
—
—
—
—
—
18/2
17/1
16/0
—
—
—
—
0000
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RXPAUSE
PASSALL
—
—
BUFCNT<7:0>
—
—
—
—
—
—
—
—
0000
FRMTXOKCNT<15:0>
—
—
—
—
—
—
—
—
SCOLFRMCNT<15:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
SOFT
RESET
SIM
RESET
—
—
RESET
RMCS
RESET
RFUN
RESET
TMCS
RESET
TFUN
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
EXCESS
DFR
BP
NOBKOFF
NOBKOFF
—
—
LONGPRE
PUREPRE
AUTOPAD
VLANPAD
PAD
ENABLE
CRC
ENABLE
—
—
—
ALGNERRCNT<15:0>
 2010 Microchip Technology Inc.
9210
EMACx
CFG2
9220
EMACx
IPGT
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
9230
EMACx
IPGR
31:16
—
—
—
—
—
—
—
—
—
15:0
—
9240
EMACx
CLRT
31:16
—
—
15:0
—
—
9250
EMACx
MAXF
31:16
—
—
NB2BIPKTGP1<6:0>
—
—
—
—
—
CWINDOW<5:0>
—
—
—
—
—
15:0
—
LOOPBACK TXPAUSE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
DELAYCRC HUGEFRM LENGTHCK FULLDPLX 4082
—
—
—
—
—
—
—
—
—
—
—
—
0000
0C12
RETX<3:0>
—
0000
0012
NB2BIPKTGP2<6:0>
—
0000
RXENABLE 800D
B2BIPKTGP<6:0>
—
MACMAXF<15:0>
0000
0000
—
—
0000
0000
—
9200
0000
0000
FCSERRCNT<15:0>
—
0000
0000
FRMRXOKCNT<15:0>
—
0000
0000
MCOLFRMCNT<15:0>
—
0000
0000
31:16
ETH
ALGNERR 15:0
Legend:
0000
RXOVFLWCNT<15:0>
EMACx
CFG1
Note
19/3
All Resets
Bit Range
Bits
—
—
0000
370F
—
0000
05EE
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
Reset values default to the factory programmed value.
PIC32MX5XX/6XX/7XX
DS61156C-page 102
TABLE 4-47:
Virtual Address
(BF88_#)
Register
Name
9260
EMACx
SUPP
ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
31:16
—
—
—
15:0
—
—
—
—
—
—
—
RESET
RMII
—
31:16
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
All Resets
Bits
Bit Range
 2010 Microchip Technology Inc.
TABLE 4-47:
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
0000
—
SPEED
RMII
—
—
—
—
—
—
—
—
1000
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
TESTBP
—
—
—
—
—
—
—
—
—
—
—
EMACx
TEST
9280
EMACx
MCFG
15:0
RESET
MGMT
—
—
—
—
—
—
—
—
—
9290
EMACx
MCMD
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCAN
READ
0000
92A0
EMACx
MADR
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
92B0
EMACx
MWTD
31:16
—
—
—
—
—
—
—
—
—
—
—
92C0
EMACx
MRDD
31:16
—
—
—
—
—
—
—
92D0
EMACx
MIND
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
LINKFAIL
NOTVALID
SCAN
9300
EMACx
SA0(2)
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9310
EMACx
SA1(2)
31:16
—
—
—
9320
EMACx
SA2(2)
31:16
—
—
—
Legend:
Note
PHYADDR<4:0>
—
—
—
—
15:0
CLKSEL<3:0>
—
NOPRE
—
—
—
—
—
—
—
—
—
—
REGADDR<4:0>
0100
—
—
15:0
—
—
—
—
—
—
—
STNADDR4<7:0>
—
—
—
—
—
—
—
—
STNADDR2<7:0>
—
—
—
—
—
—
STNADDR1<7:0>
xxxx
xxxx
STNADDR3<7:0>
—
0000
MIIMBUSY 0000
STNADDR5<7:0>
—
0000
0000
STNADDR6<7:0>
—
0000
0000
MRDD<15:0>
15:0
0000
SCANINC 0020
MWTD<15:0>
15:0
15:0
—
TESTPAUSE SHRTQNTA 0000
xxxx
xxxx
xxxx
xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
Reset values default to the factory programmed value.
DS61156C-page 103
PIC32MX5XX/6XX/7XX
Preliminary
9270
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 104
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
5.0
FLASH PROGRAM MEMORY
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 5. “Flash Program Memory” (DS61121) in the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
PIC32MX5XX/6XX/7XX devices contain an internal
Flash program memory for executing user code. There
are three methods by which the user can program this
memory:
1.
2.
3.
Run-Time Self Programming (RTSP)
EJTAG Programming
In-Circuit Serial Programming™ (ICSP™)
RTSP is performed by software executing from either
Flash or RAM memory. Information about RTSP
techniques is available in Section 5. “Flash Program
Memory” (DS61121) in the “PIC32MX Family
Reference Manual”.
EJTAG is performed using the EJTAG port of the
device and an EJTAG capable programmer.
ICSP is performed using a serial data connection to the
device and allows much faster programming times than
RTSP.
The EJTAG and ICSP methods are described in the
“PIC32MX
Flash
Programming
Specification”
(DS61145), which can be downloaded from the
Microchip web site.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 105
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 106
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
6.0
RESETS
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 7. “Resets”
(DS61118) in the “PIC32MX Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
FIGURE 6-1:
The Reset module combines all Reset sources and
controls the device Master Reset signal, SYSRST. The
following is a list of device Reset sources:
•
•
•
•
•
•
POR: Power-on Reset
MCLR: Master Clear Reset Pin
SWR: Software Reset
WDTR: Watchdog Timer Reset
BOR: Brown-out Reset
CMR: Configuration Mismatch Reset
A simplified block diagram of the Reset module is
shown in Figure 6-1.
SYSTEM RESET BLOCK DIAGRAM
MCLR
Glitch Filter
Sleep or Idle
WDTR
WDT
Time-out
Voltage
Regulator
Enabled
VDD
MCLR
Power-up
Timer
POR
Brown-out
Reset
BOR
SYSRST
VDD Rise
Detect
Configuration
Mismatch
Reset
CMR
SWR
Software Reset
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 107
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 108
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
7.0
INTERRUPT CONTROLLER
The PIC32MX5XX/6XX/7XX interrupt module includes
the following features:
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Interrupt
Controller” (DS61108) in the “PIC32MX
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to
4.0 “Memory Organization” in this data
sheet for device-specific register and bit
information.
PIC32MX5XX/6XX/7XX devices generate interrupt
requests in response to interrupt events from peripheral
modules. The interrupt control module exists externally
to the CPU logic and prioritizes the interrupt events
before presenting them to the CPU.
•
•
•
•
•
Up to 96 Interrupt Sources
Up to 64 Interrupt Vectors
Single and Multi-Vector mode Operations
Five External Interrupts with Edge Polarity Control
Interrupt Proximity Timer
Module Freeze in Debug mode
Seven User-Selectable Priority Levels for each
Vector
Four User-Selectable Subpriority Levels within
each Priority
Dedicated Shadow Set for User-Selectable
Priority Level
Software can Generate any Interrupt
User-Configurable Interrupt Vector Table Location
User-Configurable Interrupt Vector Spacing
INTERRUPT CONTROLLER MODULE
Interrupt Requests
FIGURE 7-1:
•
•
•
•
•
•
•
Vector Number
Interrupt Controller
Priority Level
CPU Core
Shadow Set Number
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 109
PIC32MX5XX/6XX/7XX
TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION
Interrupt Source(1)
IRQ
Vector
Number
Interrupt Bit Location
Flag
Enable
Priority
Sub-Priority
IEC0<0>
IPC0<4:2>
IPC0<1:0>
Highest Natural Order Priority
CT – Core Timer Interrupt
0
0
IFS0<0>
CS0 – Core Software Interrupt 0
1
1
IFS0<1>
IEC0<1>
IPC0<12:10>
IPC0<9:8>
CS1 – Core Software Interrupt 1
2
2
IFS0<2>
IEC0<2>
IPC0<20:18>
IPC0<17:16>
INT0 – External Interrupt 0
3
3
IFS0<3>
IEC0<3>
IPC0<28:26>
IPC0<25:24>
T1 – Timer1
4
4
IFS0<4>
IEC0<4>
IPC1<4:2>
IPC1<1:0>
IC1 – Input Capture 1
5
5
IFS0<5>
IEC0<5>
IPC1<12:10>
IPC1<9:8>
OC1 – Output Compare 1
6
6
IFS0<6>
IEC0<6>
IPC1<20:18>
IPC1<17:16>
INT1 – External Interrupt 1
7
7
IFS0<7>
IEC0<7>
IPC1<28:26>
IPC1<25:24>
T2 – Timer2
8
8
IFS0<8>
IEC0<8>
IPC2<4:2>
IPC2<1:0>
IC2 – Input Capture 2
9
9
IFS0<9>
IEC0<9>
IPC2<12:10>
IPC2<9:8>
OC2 – Output Compare 2
10
10
IFS0<10>
IEC0<10>
IPC2<20:18>
IPC2<17:16>
INT2 – External Interrupt 2
11
11
IFS0<11>
IEC0<11>
IPC2<28:26>
IPC2<25:24>
T3 – Timer3
12
12
IFS0<12>
IEC0<12>
IPC3<4:2>
IPC3<1:0>
IC3 – Input Capture 3
13
13
IFS0<13>
IEC0<13>
IPC3<12:10>
IPC3<9:8>
OC3 – Output Compare 3
14
14
IFS0<14>
IEC0<14>
IPC3<20:18>
IPC3<17:16>
INT3 – External Interrupt 3
15
15
IFS0<15>
IEC0<15>
IPC3<28:26>
IPC3<25:24>
T4 – Timer4
16
16
IFS0<16>
IEC0<16>
IPC4<4:2>
IPC4<1:0>
IC4 – Input Capture 4
17
17
IFS0<17>
IEC0<17>
IPC4<12:10>
IPC4<9:8>
OC4 – Output Compare 4
18
18
IFS0<18>
IEC0<18>
IPC4<20:18>
IPC4<17:16>
INT4 – External Interrupt 4
19
19
IFS0<19>
IEC0<19>
IPC4<28:26>
IPC4<25:24>
T5 – Timer5
20
20
IFS0<20>
IEC0<20>
IPC5<4:2>
IPC5<1:0>
IC5 – Input Capture 5
21
21
IFS0<21>
IEC0<21>
IPC5<12:10>
IPC5<9:8>
OC5 – Output Compare 5
22
22
IFS0<22>
IEC0<22>
IPC5<20:18>
IPC5<17:16>
SPI1E – SPI1 Fault
23
23
IFS0<23>
IEC0<23>
IPC5<28:26>
IPC5<25:24>
SPI1RX – SPI1 Receive Done
24
23
IFS0<24>
IEC0<24>
IPC5<28:26>
IPC5<25:24>
SPI1TX – SPI1 Transfer Done
25
23
IFS0<25>
IEC0<25>
IPC5<28:26>
IPC5<25:24>
26
24
IFS0<26>
IEC0<26>
IPC6<4:2>
IPC6<1:0>
27
24
IFS0<27>
IEC0<27>
IPC6<4:2>
IPC6<1:0>
28
24
IFS0<28>
IEC0<28>
IPC6<4:2>
IPC6<1:0>
U1AE – UART1A Error
SPI1AE – SPI1A Fault
I2C1AB – I2C1A Bus Collision Event
U1ARX – UART1A Receiver
SPI1ARX – SPI1A Receive Done
I2C1AS – I2C1A Slave Event
U1ATX – UART1A Transmitter
SPI1ATX – SPI1A Transfer Done
I2C1AM – I2C1A Master Event
I2C1B – I2C1 Bus Collision Event
29
25
IFS0<29>
IEC0<29>
IPC6<12:10>
IPC6<9:8>
I2C1S – I2C1 Slave Event
30
25
IFS0<30>
IEC0<30>
IPC6<12:10>
IPC6<9:8>
I2C1M – I2C1 Master Event
31
25
IFS0<31>
IEC0<31>
IPC6<12:10>
IPC6<9:8>
CN – Input Change Interrupt
32
26
IFS1<0>
IEC1<0>
IPC6<20:18>
IPC6<17:16>
AD1 – ADC1 Convert Done
33
27
IFS1<1>
IEC1<1>
IPC6<28:26>
IPC6<25:24>
PMP – Parallel Master Port
34
28
IFS1<2>
IEC1<2>
IPC7<4:2>
IPC7<1:0>
Note 1:
Not all interrupt sources are available on all devices. See Table 1 for the list of available peripherals.
DS61156C-page 110
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Bit Location
IRQ
Vector
Number
Flag
Enable
Priority
CMP1 – Comparator Interrupt
35
29
IFS1<3>
IEC1<3>
IPC7<12:10>
IPC7<9:8>
CMP2 – Comparator Interrupt
36
30
IFS1<4>
IEC1<4>
IPC7<20:18>
IPC7<17:16>
U2AE – UART2A Error
SPI2AE – SPI2A Fault
I2C2AB – I2C2A Bus Collision Event
37
31
IFS1<5>
IEC1<5>
IPC7<28:26>
IPC7<25:24>
U2ARX – UART2A Receiver
SPI2ARX – SPI2A Receive Done
I2C2AS – I2C2A Slave Event
38
31
IFS1<6>
IEC1<6>
IPC7<28:26>
IPC7<25:24>
U2ATX – UART2A Transmitter
SPI2ATX – SPI2A Transfer Done
IC2AM – I2C2A Master Event
39
31
IFS1<7>
IEC1<7>
IPC7<28:26>
IPC7<25:24>
U3AE – UART3A Error
SPI3AE – SPI3A Fault
I2C3AB – I2C3A Bus Collision Event
40
32
IFS1<8>
IEC1<8>
IPC8<4:2>
IPC8<1:0>
U3ARX – UART3A Receiver
SPI3ARX – SPI3A Receive Done
I2C3AS – I2C3A Slave Event
41
32
IFS1<9>
IEC1<9>
IPC8<4:2>
IPC8<1:0>
U3ATX – UART3A Transmitter
SPI3ATX – SPI3A Transfer Done
IC3AM – I2C3A Master Event
42
32
IFS1<10>
IEC1<10>
IPC8<4:2>
IPC8<1:0>
Interrupt Source(1)
Sub-Priority
I2C2B – I2C2 Bus Collision Event
43
33
IFS1<11>
IEC1<11>
IPC8<12:10>
IPC8<9:8>
I2C2S – I2C2 Slave Event
44
33
IFS1<12>
IEC1<12>
IPC8<12:10>
IPC8<9:8>
I2C2M – I2C2 Master Event
45
33
IFS1<13>
IEC1<13>
IPC8<12:10>
IPC8<9:8>
FSCM – Fail-Safe Clock Monitor
46
34
IFS1<14>
IEC1<14>
IPC8<20:18>
IPC8<17:16>
RTCC – Real-Time Clock
47
35
IFS1<15>
IEC1<15>
IPC8<28:26>
IPC8<25:24>
DMA0 – DMA Channel 0
48
36
IFS1<16>
IEC1<16>
IPC9<4:2>
IPC9<1:0>
DMA1 – DMA Channel 1
49
37
IFS1<17>
IEC1<17>
IPC9<12:10>
IPC9<9:8>
DMA2 – DMA Channel 2
50
38
IFS1<18>
IEC1<18>
IPC9<20:18>
IPC9<17:16>
DMA3 – DMA Channel 3
51
39
IFS1<19>
IEC1<19>
IPC9<28:26>
IPC9<25:24>
DMA4 – DMA Channel 4
52
40
IFS1<20>
IEC1<20>
IPC10<4:2>
IPC10<1:0>
DMA5 – DMA Channel 5
53
41
IFS1<21>
IEC1<21> IPC10<12:10>
DMA6 – DMA Channel 6
54
42
IFS1<22>
IEC1<22> IPC10<20:18> IPC10<17:16>
DMA7 – DMA Channel 7
55
43
IFS1<23>
IEC1<23> IPC10<28:26> IPC10<25:24>
FCE – Flash Control Event
56
44
IFS1<24>
IEC1<24>
IPC11<4:2>
IPC10<9:8>
IPC11<1:0>
USB – USB Interrupt
57
45
IFS1<25>
IEC1<25> IPC11<12:10>
CAN1 – Control Area Network 1
58
46
IFS1<26>
IEC1<26> IPC11<20:18> IPC11<17:16>
CAN2 – Control Area Network 2
59
47
IFS1<27>
IEC1<27> IPC11<28:26> IPC11<25:24>
ETH – Ethernet Interrupt
60
48
IFS1<28>
IEC1<28>
IPC12<4:2>
IPC12<1:0>
IC1E – Input Capture 1 Error
61
5
IFS1<29>
IEC1<29>
IPC1<12:10>
IPC1<9:8>
IC2E – Input Capture 2 Error
62
9
IFS1<30>
IEC1<30>
IPC2<12:10>
IPC2<9:8>
IC3E – Input Capture 3 Error
63
13
IFS1<31>
IEC1<31>
IPC3<12:10>
IPC3<9:8>
IC4E – Input Capture 4 Error
64
17
IFS2<0>
IEC2<0>
IPC4<12:10>
IPC4<9:8>
IC4E – Input Capture 5 Error
65
21
IFS2<1>
IEC2<1>
IPC5<12:10>
IPC5<9:8>
PMPE – Parallel Master Port Error
66
28
IFS2<2>
IEC2<2>
IPC7<4:2>
IPC7<1:0>
U1BE – UART1B Error
67
49
IFS2<3>
IEC2<3>
IPC12<12:10>
IPC12<9:8>
Note 1:
IPC11<9:8>
Not all interrupt sources are available on all devices. See Table 1 for the list of available peripherals.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 111
PIC32MX5XX/6XX/7XX
TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Bit Location
IRQ
Vector
Number
Flag
Enable
Priority
U1BRX – UART1B Receiver
68
49
IFS2<4>
IEC2<4>
IPC12<12:10>
IPC12<9:8>
U1BTX – UART1B Transmitter
69
49
IFS2<5>
IEC2<5>
IPC12<12:10>
IPC12<9:8>
Interrupt Source(1)
Sub-Priority
U2BE – UART2B Error
70
50
IFS2<6>
IEC2<6>
IPC12<20:18> IPC12<17:16>
U2BRX – UART2B Receiver
71
50
IFS2<7>
IEC2<7>
IPC12<20:18> IPC12<17:16>
U2BTX – UART2B Transmitter
72
50
IFS2<8>
IEC2<8>
IPC12<20:18> IPC12<17:16>
U3BE – UART3B Error
73
51
IFS2<9>
IEC2<9>
IPC12<28:26> IPC12<25:24>
U3BRX – UART3B Receiver
74
51
IFS2<10>
IEC2<10> IPC12<28:26> IPC12<25:24>
U3BTX – UART3B Transmitter
75
51
IFS2<11>
IEC2<11> IPC12<28:26> IPC12<25:24>
(Reserved)
—
—
—
—
—
—
Lowest Natural Order Priority
Note 1:
Not all interrupt sources are available on all devices. See Table 1 for the list of available peripherals.
DS61156C-page 112
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
8.0
OSCILLATOR
CONFIGURATION
The PIC32MX5XX/6XX/7XX oscillator system has the
following modules and features:
• A Total of Four External and Internal Oscillator
Options as Clock Sources
• On-Chip PLL with User-Selectable Input Divider,
Multiplier and Output Divider to Boost Operating
Frequency on Select Internal and External
Oscillator Sources
• On-Chip User-Selectable Divisor Postscaler on
Select Oscillator Sources
• Software-Controllable Switching Between
Various Clock Sources
• A Fail-Safe Clock Monitor (FSCM) that Detects
Clock Failure and Permits Safe Application
Recovery or Shutdown
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 6. “Oscillator
Configuration”
(DS61112) in the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
FIGURE 8-1:
• Dedicated On-Chip PLL for USB Peripheral
PIC32MX5XX/6XX/7XX FAMILY CLOCK DIAGRAM
USB PLL
UFIN
div x
OSC1
C1(3)
C2(3)
OSC2(4)
UFRCEN
FUPLLEN
XT, HS, EC
To Internal
Logic
4 MHz FIN 5 MHz
XTPLL, HSPLL,
FIN
ECPLL, FRCPLL
div x
div y
PLL
Enable
RS(1)
div 2
UFIN 4 MHz
FUPLLDIV<2:0>
Primary Oscillator
(POSC)
RF(2)
XTAL
USB Clock (48 MHz)
PLL x24
div 2
PLL Input Divider
FPLLIDIV<2:0>
ADC
FRC
Oscillator
8 MHz typical
div 16
TUN<5:0>
Postscaler
LPRC
Oscillator
PBDIV<2:0>
PLL Output Divider
PLLODIV<2:0>
PLL Multiplier
PLLMULT<2:0>
COSC<2:0>
FRCDIV<2:0>
Postscaler Peripherals
div x
PBCLK
FRC
CPU and Select Peripherals
FRC/16
FRCDIV
LPRC
31.25 kHz typical
Secondary Oscillator (SOSC)
SOSCO
32.768 kHz
SOSC
SOSCEN and FSOSCEN
Clock Control Logic
Fail-Safe
Clock
Monitor
SOSCI
Notes:
1.
2.
3.
4.
A series resistor, RS, may be required for AT strip cut crystals.
The internal feedback resistor, RF, is typically in the range of 2 to 10 M
Refer to Section 6. “Oscillator Configuration” (DS61112) in the
“PIC32MX Family Reference Manual” for help in determining the best
oscillator components.
PBCLK out is available on the OSC2 pin in certain clock modes.
 2010 Microchip Technology Inc.
Preliminary
FSCM INT
FSCM Event
NOSC<2:0>
COSC<2:0>
OSWEN
FSCMEN<1:0>
WDT, PWRT
Timer1, RTCC
DS61156C-page 113
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 114
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
PREFETCH CACHE
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
Cache” (DS61119) in the “PIC32MX
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to
4.0 “Memory Organization” in this data
sheet for device-specific register and bit
information.
FIGURE 9-1:
9.1
•
•
•
•
•
•
•
•
16 Fully Associative Lockable Cache Lines
16-Byte Cache Lines
Up to Four Cache Lines Allocated to Data
Two Cache Lines with Address Mask to Hold
Repeated Instructions
Pseudo LRU Replacement Policy
All Cache Lines are Software Writable
16-Byte Parallel Memory Fetch
Predictive Instruction Prefetch
CTRL
Tag Logic
CTRL
Features
PREFETCH MODULE BLOCK DIAGRAM
FSM
BMX/CPU
Prefetch cache increases performance for applications
executing out of the cacheable program Flash memory
regions by implementing instruction caching, constant
data caching and instruction prefetching.
Cache Line
Bus Ctrl
BMX/CPU
9.0
Cache Ctrl
Prefetch Ctrl
Cache
Line
Address
Encode
Hit LRU
Miss LRU
RDATA
Hit Logic
PreFetch
Prefetch
Pre-Fetch
CTRL
RDATA
PreFetch
Prefetch
Pre-Fetch
Tag
PFM
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 115
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 116
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
10.0
DIRECT MEMORY ACCESS
(DMA) CONTROLLER
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 31. “Direct
Memory Access (DMA) Controller”
(DS61117) in the “PIC32MX Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The PIC32MX Direct Memory Access (DMA) controller
is a bus master module useful for data transfers
between different devices without CPU intervention.
The source and destination of a DMA transfer can be
any of the memory mapped modules existent in the
PIC32MX (such as Peripheral Bus (PBUS) devices:
SPI, UART, I2C™, etc.) or memory itself.
Following are some of the key features of the DMA
controller module:
• Four Identical Channels, each Featuring:
- Auto-Increment Source and Destination
Address registers
- Source and Destination Pointers
- Memory to memory and memory to
peripheral transfers
FIGURE 10-1:
DMA BLOCK DIAGRAM
INT Controller
Peripheral Bus
• Automatic Word-Size Detection:
- Transfer granularity, down to byte level
- Bytes need not be word-aligned at source
and destination
• Fixed Priority Channel Arbitration
• Flexible DMA Channel Operating modes:
- Manual (software) or automatic (interrupt)
DMA requests
- One-Shot or Auto-Repeat Block Transfer
modes
- Channel-to-channel chaining
• Flexible DMA Requests:
- A DMA request can be selected from any of
the peripheral interrupt sources
- Each channel can select any (appropriate)
observable interrupt as its DMA request
source
- A DMA transfer abort can be selected from
any of the peripheral interrupt sources
- Pattern (data) match transfer termination
• Multiple DMA Channel Status Interrupts:
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half full
- DMA transfer aborted due to an external
event
- Invalid DMA address generated
• DMA Debug Support Features:
- Most recent address accessed by a DMA
channel
- Most recent DMA channel to transfer data
• CRC Generation Module:
- CRC module can be assigned to any of the
available channels
- CRC module is highly configurable
System IRQ
Address Decoder
SE
L
Channel 0 Control
I0
Channel 1 Control
I1
Y
Bus Interface
Device Bus + Bus Arbitration
I2
Global Control
(DMACON)
Channel n Control
In
L
SE
Channel Priority
Arbitration
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 117
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 118
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
11.0
USB ON-THE-GO (OTG)
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 27. “USB OnThe-Go (OTG)” (DS61126) in the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The Universal Serial Bus (USB) module contains
analog and digital components to provide a USB 2.0
full-speed and low-speed embedded host, full-speed
device or OTG implementation with a minimum of
external components. This module in Host mode is
intended for use as an embedded host and therefore
does not implement a UHCI or OHCI controller.
The USB module consists of the clock generator, the
USB voltage comparators, the transceiver, the Serial
Interface Engine (SIE), a dedicated USB DMA controller, pull-up and pull-down resistors, and the register
interface. A block diagram of the PIC32MX USB OTG
module is presented in Figure 11-1.
 2010 Microchip Technology Inc.
The clock generator provides the 48 MHz clock
required for USB full-speed and low-speed communication. The voltage comparators monitor the voltage on
the VBUS pin to determine the state of the bus. The
transceiver provides the analog translation between
the USB bus and the digital logic. The SIE is a state
machine that transfers data to and from the endpoint
buffers and generates the hardware protocol for data
transfers. The USB DMA controller transfers data
between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the
need for external signaling components. The register
interface allows the CPU to configure and
communicate with the module.
The PIC32MX USB module includes the following
features:
•
•
•
•
•
•
•
•
•
USB Full-Speed Support for Host and Device
Low-Speed Host Support
USB OTG Support
Integrated Signaling Resistors
Integrated Analog Comparators for VBUS
Monitoring
Integrated USB Transceiver
Transaction Handshaking Performed by
Hardware
Endpoint Buffering Anywhere in System RAM
Integrated DMA to Access System RAM and
Flash
Note:
Preliminary
IMPORTANT! The implementation and
use of the USB specifications, as well as
other third party specifications or technologies, may require licensing; including,
but not limited to, USB Implementers
Forum, Inc. (also referred to as USB-IF).
The user is fully responsible for investigating and satisfying any applicable licensing
obligations.
DS61156C-page 119
PIC32MX5XX/6XX/7XX
FIGURE 11-1:
PIC32MX5XX/6XX/7XX FAMILY USB INTERFACE DIAGRAM
USBEN
FRC
Oscillator
8 MHz Typical
USB Suspend
CPU Clock Not POST
Sleep
TUN<5:0>(4)
Primary Oscillator
(POST)
Div x
OSC1
UFIN(5)
Div 2
FUPLLEN(6)
FUPLLIDIV(6)
UFRCEN(3)
To Clock Generator for Core and Peripherals
USB Suspend
OSC2
(PB Out)(1)
Sleep or Idle
USB Module
USB
Voltage
Comparators
SRP Charge
Bus
PLL
SRP Discharge
48 MHz USB Clock(7)
Full Speed Pull-up
D+(2)
Registers
and
Control
Interface
Host Pull-down
SIE
Transceiver
Low Speed Pull-up
D-(2)
DMA
System
RAM
Host Pull-down
ID Pull-up
ID(8)
Vibes(8)
VUSB
Note 1:
2:
3:
4:
5:
6:
7:
8:
DS61156C-page 120
Transceiver Power 3.3V
PB clock is only available on this pin for select EC modes.
Pins can be used as digital inputs when USB is not enabled.
This bit field is contained in the OSCCON register.
This bit field is contained in the OSCTRM register.
USB PLL UFIN requirements: 4 MHz.
This bit field is contained in the DEVCFG2 register.
A 48 MHz clock is required for proper USB operation.
Pins can be used as GPIO when the USB module is disabled.
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
12.0
I/O PORTS
General purpose I/O pins are the simplest of peripherals. They allow the PIC® MCU to monitor and control
other devices. To add flexibility and functionality, some
pins are multiplexed with alternate function(s). These
functions depend on which peripheral features are on
the device. In general, when a peripheral is functioning,
that pin may not be used as a general purpose I/O pin.
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS61120) in the “PIC32MX Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
Following are some of the key features of this module:
• Individual Output Pin Open-Drain Enable/Disable
• Individual Input Pin Weak Pull-up Enable/Disable
• Monitor Selective Inputs and Generate Interrupt
when Change in Pin State is Detected
• Operation during CPU Sleep and Idle modes
• Fast Bit Manipulation using CLR, SET and INV
Registers
Figure 12-1 shows a block diagram of a typical
multiplexed I/O port.
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
FIGURE 12-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Peripheral Module
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
PIO Module
RD ODC
Data Bus
SYSCLK
D
Q
ODC
CK
EN Q
WR ODC
1
RD TRIS
0
IO Cell
0
1
D
Q
1
TRIS
CK
EN Q
WR TRIS
Output Multiplexers
D
WR LAT
WR PORT
0
Q
IO Pin
LAT
CK
EN Q
RD LAT
1
RD PORT
0
Sleep
Q
Q
D
CK
Q
Q
D
CK
SYSCLK
Synchronization
Peripheral Input
Legend:
Note:
R
Peripheral Input Buffer
R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure
for any specific port/peripheral combination may be different than it is shown here.
 2010 Microchip Technology Inc.
Preliminary
DS61156C - page 121
PIC32MX5XX/6XX/7XX
12.1
Parallel I/O (PIO) Ports
12.1.2
All port pins have three registers (TRIS, LAT and
PORT) that are directly associated with their operation.
TRIS is a Data Direction or Tri-State Control register
that determines whether a digital pin is an input or an
output. Setting a TRISx register bit = 1 configures the
corresponding I/O pin as an input; setting a TRISx
register bit = 0 configures the corresponding I/O pin as
an output. All port I/O pins are defined as inputs after a
device Reset. Certain I/O pins are shared with analog
peripherals and default to analog inputs after a device
Reset.
PORT is a register used to read the current state of the
signal applied to the port I/O pins. Writing to a PORTx
register performs a write to the port’s latch, LATx
register, latching the data to the port’s I/O pins.
LAT is a register used to write data to the port I/O pins.
The LATx Latch register holds the data written to either
the LATx or PORTx registers. Reading the LATx Latch
register reads the last value written to the
corresponding PORT or Latch register.
Not all port I/O pins are implemented on some devices,
therefore, the corresponding PORTx, LATx and TRISx
register bits will read as zeros.
12.1.1
CLR, SET AND INV REGISTERS
Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
To set PORTC bit 0, write to the LATSET register:
LATCSET = 0x0001;
To clear PORTC bit 0, write to the LATCLR register:
LATCCLR = 0x0001;
To toggle PORTC bit 0, write to the LATINV register:
LATCINV = 0x0001;
Note:
Using a PORTxINV register to toggle a bit
is recommended because the operation is
performed in hardware atomically, using
fewer instructions, as compared to the
traditional
read-modify-write
method
shown below:
PORTC ^= 0x0001;
DS61156C - page 122
DIGITAL INPUTS
Pins are configured as digital inputs by setting the corresponding TRIS register bits = 1. When configured as
inputs, they are either TTL buffers or Schmitt Triggers.
Several digital pins share functionality with analog
inputs and default to the analog inputs at POR. Setting
the corresponding bit in the AD1PCFG register = 1
enables the pin as a digital pin.
The maximum input voltage allowed on the input pins
is the same as the maximum VIH specification. Refer to
Section 31.0 “Electrical Characteristics” for VIH
specification details.
Note:
12.1.3
Analog levels on any pin that is defined as
a digital input (including the ANx pins) may
cause the input buffer to consume current
that exceeds the device specifications.
ANALOG INPUTS
Certain pins can be configured as analog inputs used
by the ADC and comparator modules. Setting the corresponding bits in the AD1PCFG register = 0 enables
the pin as an analog input pin and must have the corresponding TRIS bit set = 1 (input). If the TRIS bit is
cleared = 0 (output), the digital output level (VOH or
VOL) will be converted. Any time a port I/O pin is configured as analog, its digital input is disabled and the
corresponding PORTx register bit will read ‘0’. The
AD1PCFG register has a default value of ‘0x0000’;
therefore, all pins that share ANx functions are analog
(not digital) by default.
12.1.4
DIGITAL OUTPUTS
Pins are configured as digital outputs by setting the
corresponding TRIS register bits = 0. When configured
as digital outputs, these pins are CMOS drivers or can
be configured as open-drain outputs by setting the corresponding bits in the ODCx Open-Drain Configuration
register.
The open-drain feature allows generation of outputs
higher than VDD (e.g., 5V) on any desired 5V tolerant
pins by using external pull-up resistors. The maximum
open-drain voltage allowed is the same as the
maximum VIH specification.
See the “Pin Diagrams” section for the available pins
and their functionality.
12.1.5
ANALOG OUTPUTS
Certain pins can be configured as analog outputs, such
as the CVREF output voltage used by the comparator
module. Configuring the comparator reference module
to provide this output will present the analog output
voltage on the pin, independent of the TRIS register
setting for the corresponding pin.
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
13.0
TIMER1
This family of PIC32MX devices features one
synchronous/asynchronous 16-bit timer that can operate
as a free-running interval timer for various timing applications and counting external events. This timer can also
be used with the Low-Power Secondary Oscillator
(SOSC) for Real-Time Clock (RTC) applications. The
following modes are supported:
Note 1: This data sheet summarizes the features of
the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS61105) in the “PIC32MX Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
•
•
•
•
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to
4.0 “Memory Organization” in this data
sheet for device-specific register and bit
information.
Synchronous Internal Timer
Synchronous Internal Gated Timer
Synchronous External Timer
Asynchronous External Timer
13.1
Additional Supported Features
• Selectable Clock Prescaler
• Timer Operation during CPU Idle and Sleep mode
• Fast Bit Manipulation using CLR, SET and INV
registers
• Asynchronous mode can be used with the SOSC
to Function as a Real-Time Clock (RTC).
TIMER1 BLOCK DIAGRAM(1)
FIGURE 13-1:
PR1
Equal
16-Bit Comparator
TSYNC (T1CON<2>)
1
Sync
TMR1
Reset
0
T1IF
Event Flag
0
Q
1
TGATE (T1CON<7>)
D
Q
TGATE (T1CON<7>)
TCS (T1CON<1>)
ON (T1CON<15>)
SOSCO/T1CK
x1
SOSCEN
SOSCI
Gate
Sync
PBCLK
10
00
Prescaler
1, 8, 64, 256
2
TCKPS<1:0>
(T1CON<5:4>)
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in
Configuration Word, DEVCFG1.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 123
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 124
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
14.0
TIMER2/3, TIMER4/5
Two 32-bit synchronous timers are available by
combining Timer2 with Timer3 and Timer4 with Timer5.
The 32-bit timers can operate in three modes:
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS61105) of the “PIC32MX Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
• Synchronous Internal 32-Bit Timer
• Synchronous Internal 32-Bit Gated Timer
• Synchronous External 32-Bit Timer
Note:
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to
4.0 “Memory Organization” in this data
sheet for device-specific register and bit
information.
14.1
In this chapter, references to registers,
TxCON, TMRx and PRx, use ‘x’ to represent Timer2 through 5 in 16-bit modes. In
32-bit modes, ‘x’ represents Timer2 or 4;
‘y’ represents Timer3 or 5.
Additional Supported Features
• Selectable Clock Prescaler
• Timers Operational during CPU Idle
• Time Base for Input Capture and Output Compare
modules (Timer2 and Timer3 only)
• ADC Event Trigger (Timer3 only)
• Fast Bit Manipulation using CLR, SET and INV
registers
This family of PIC32MX devices features four
synchronous 16-bit timers (default) that can operate as
a free-running interval timer for various timing applications and counting external events. The following
modes are supported:
• Synchronous Internal 16-Bit Timer
• Synchronous Internal 16-Bit Gated Timer
• Synchronous External 16-Bit Timer
FIGURE 14-1:
TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT)
Sync
TMRx
ADC Event
Trigger(1)
Equal
Comparator x 16
PRx
Reset
TxIF
Event Flag
0
1
TGATE (TxCON<7>)
Q
TGATE (TxCON<7>)
D
Q
TCS (TxCON<1>)
ON (TxCON<15>)
TxCK(2)
x1
Gate
Sync
PBCLK
10
00
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
3
TCKPS (TxCON<6:4>)
Note 1: ADC event trigger is available on Timer3 only.
2: TxCK pins are not available on 64-pin devices.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 125
PIC32MX5XX/6XX/7XX
FIGURE 14-2:
TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)(1)
Reset
TMRy
MS Half Word
ADC Event
Trigger(3)
Equal
Sync
LS Half Word
32-Bit Comparator
PRy
TyIF Event
Flag
TMRx
PRx
0
1
TGATE (TxCON<7>)
Q
D
TGATE (TxCON<7>)
Q
TCS (TxCON<1>)
ON (TxCON<15>)
TxCK(2)
x1
Gate
Sync
PBCLK
10
00
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
3
TCKPS (TxCON<6:4>)
Note 1: In this diagram, the use of “x’ in registers, TxCON, TMRx, PRx, TxCK, refers to either Timer2 or Timer4; the use of
‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5.
2: TxCK pins are not available on 64-pin devices.
3: ADC event trigger is available only on the Timer2/3 pair.
DS61156C-page 126
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
15.0
INPUT CAPTURE
2.
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 15. “Input
Capture” (DS61122) of the “PIC32MX
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
3.
4.
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base,
or two 16-bit timers (Timer2 and Timer3) together to
form a 32-bit timer. The selected timer can use either
an internal or external clock.
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
Other operational features include:
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The input capture module captures the 16-bit or 32-bit
value of the selected Time Base registers when an
event occurs at the ICx pin. The following events cause
capture events:
1.
Capture timer value on every edge (rising and
falling)
Capture timer value on every edge (rising and
falling), specified edge first.
Prescaler Capture Event modes
- Capture timer value on every 4th rising
edge of input at ICx pin
- Capture timer value on every 16th rising
edge of input at ICx pin
• Device Wake-up from Capture Pin during CPU
Sleep and Idle modes
• Interrupt on Input Capture Event
• 4-Word FIFO Buffer for Capture Values
Interrupt Optionally Generated after 1, 2, 3 or 4
Buffer Locations are Filled
• Input Capture can also be used to Provide
Additional Sources of External Interrupts
Simple Capture Event modes
- Capture timer value on every falling edge of
input at ICx pin
- Capture timer value on every rising edge of
input at ICx pin
FIGURE 15-1:
INPUT CAPTURE BLOCK DIAGRAM
ICx Input
Timer3 Timer2
ICTMR
0
1
C32
FIFO Control
ICxBUF<31:16>
Prescaler
1, 4, 16
ICM<2:0>
ICxBUF<15:0>
Edge Detect
ICM<2:0>
FEDGE
ICBNE
ICOV
ICxCON
ICI<1:0>
Interrupt
Event
Generation
Data Space Interface
Interrupt
 2010 Microchip Technology Inc.
Preliminary
Peripheral Data Bus
DS61156C-page 127
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 128
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
16.0
OUTPUT COMPARE
The Output Compare module (OCMP) is used to generate a single pulse or a train of pulses in response to
selected time base events. For all modes of operation,
the OCMP module compares the values stored in the
OCxR and/or the OCxRS registers to the value in the
selected timer. When a match occurs, the OCMP
module generates an event based on the selected
mode of operation.
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 16. “Output
Capture” (DS61111) in the “PIC32MX
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
The following are some of the key features:
• Multiple Output Compare Modules in a Device
• Programmable Interrupt Generation on Compare
Event
• Single and Dual Compare modes
• Single and Continuous Output Pulse Generation
• Pulse-Width Modulation (PWM) mode
• Hardware-Based PWM Fault Detection and
Automatic Output Disable
• Programmable Selection of 16-Bit or 32-Bit Time
Bases
• Can Operate from Either of Two Available 16-Bit
Time Bases or a Single 32-Bit Time Base
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
FIGURE 16-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit
OCxIF(1)
OCxRS(1)
Output
Logic
OCxR(1)
3
OCM<2:0>
Mode Select
Comparator
0
OCTSEL
1
16
0
S
R
Q
OCx(1)
Output Enable
OCFA or OCFB(2)
1
16
TMR Register Inputs
from Time Bases(3)
Period Match Signals
from Time Bases(3)
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels,
1 through 5.
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.
3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 129
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 130
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
17.0
SERIAL PERIPHERAL
INTERFACE (SPI)
The SPI module is a synchronous serial interface that
is useful for communicating with external peripherals
and other microcontroller devices. These peripheral
devices may be Serial EEPROMs, Shift registers, display drivers, A/D Converters, etc. The PIC32MX SPI
module is compatible with Motorola® SPI and SIOP
interfaces.
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a comprehensive reference source. To complement
the information in this data sheet, refer to
Section 23. “Serial Peripheral Interface
(DS61106) in the “PIC32MX
(SPI)”
Family Reference Manual”, which is available from the Microchip web site
(www.microchip.com/PIC32).
Following are some of the key features of this module:
•
•
•
•
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
•
•
•
•
FIGURE 17-1:
Master and Slave modes Support
Four Different Clock Formats
Enhanced Framed SPI Protocol Support
User-Configurable 8-Bit, 16-Bit and 32-Bit Data
Width
Separate SPI FIFO Buffers for Receive and
Transmit
- FIFO buffers act as 4/8/16-level deep FIFOs
based on 32/16/8-bit data width
Programmable Interrupt Event on Every 8-Bit,
16-Bit and 32-Bit Data Transfer
Operation during CPU Sleep and Idle mode
Fast Bit Manipulation using CLR, SET and INV
Registers
SPI MODULE BLOCK DIAGRAM
Internal
Data Bus
SPIxBUF
Read
Write
SPIxRXB FIFO
FIFOs Share Address SPIxBUF
SPIxTXB FIFO
Transmit
Receive
SPIxSR
SDIx
bit 0
SDOx
SSx/FSYNC
Slave Select
and Frame
Sync Control
Shift
Control
Clock
Control
Edge
Select
PBCLK
Baud Rate
Generator
SCKx
Enable Master Clock
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 131
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 132
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
18.0
INTER-INTEGRATED CIRCUIT
(I2C™)
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 24. “InterIntegrated Circuit” (DS61116) in the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
 2010 Microchip Technology Inc.
The I2C module provides complete hardware support
for both Slave and Multi-Master modes of the I2C serial
communication standard. Figure 18-1 shows the I2C
module block diagram.
Each I2C module has a 2-pin interface: the SCLx pin is
clock and the SDAx pin is data.
Each I2C module offers the following key features:
• I2C Interface Supporting both Master and Slave
Operation
• I2C Slave mode Supports 7 and 10-Bit Address
• I2C Master mode Supports 7 and 10-Bit Address
• I2C Port allows Bidirectional Transfers between
Master and Slaves
• Serial Clock Synchronization for I2C Port can be
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control)
• I2C Supports Multi-Master Operation; Detects Bus
Collision and Arbitrates Accordingly
• Provides Support for Address Bit Masking
Preliminary
DS61156C-page 133
PIC32MX5XX/6XX/7XX
FIGURE 18-1:
I2C™ BLOCK DIAGRAM (X = 1 OR 2)
Internal
Data Bus
I2CxRCV
SCLx
Read
Shift
Clock
I2CxRSR
LSB
SDAx
Address Match
Match Detect
Write
I2CxMSK
Write
Read
I2CxADD
Read
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
Control Logic
I2CxSTAT
Collision
Detect
Read
Write
I2CxCON
Acknowledge
Generation
Read
Clock
Stretching
Write
I2CxTRN
LSB
Read
Shift Clock
Reload
Control
Write
BRG Down Counter
I2CxBRG
Read
PBCLK
DS61156C-page 134
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
19.0
Note
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 21. “Universal
Asynchronous Receiver Transmitter
(DS61107) in the “PIC32MX
(UART)”
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The UART module is one of the serial I/O modules
available in PIC32MX5XX/6XX/7XX family devices.
The UART is a full-duplex, asynchronous communication channel that communicates with peripheral
devices and personal computers through protocols,
such as RS-232, RS-485, LIN 1.2 and IrDA®. The
module also supports the hardware flow control option,
with UxCTS and UxRTS pins, and also includes an
IrDA encoder and decoder.
FIGURE 19-1:
The primary features of the UART module are:
•
•
•
•
•
•
•
•
•
•
•
•
•
Full-Duplex, 8-Bit or 9-Bit Data Transmission
Even, Odd or No Parity Options (for 8-bit data)
One or Two Stop Bits
Hardware Auto-Baud Feature
Hardware Flow Control Option
Fully Integrated Baud Rate Generator (BRG) with
16-Bit Prescaler
Baud Rates Ranging from 76 bps to 20 Mbps at
80 MHz
8-Level Deep First-In-First-Out (FIFO) Transmit
Data Buffer
8-Level Deep FIFO Receive Data Buffer
Parity, Framing and Buffer Overrun Error
Detection
Support for Interrupt Only on Address Detect
(9th bit = 1)
Separate Transmit and Receive Interrupts
Loopback mode for Diagnostic Support
• LIN 1.2 Protocol Support
• IrDA Encoder and Decoder with 16x Baud Clock
Output for External IrDA Encoder/Decoder
Support
Figure 19-1 shows a simplified block diagram of the
UART.
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
BCLKx
UxRTS
Hardware Flow Control
Note:
UxCTS
UARTx Receiver
UxRX
UARTx Transmitter
UxTX
Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 135
PIC32MX5XX/6XX/7XX
Figure 19-2 and Figure 19-3 illustrate typical receive
and transmit timing for the UART module.
FIGURE 19-2:
UART RECEPTION
Char 1
Char 2-4
Char 5-10
Char 11-13
Read to
UxRXREG
UxRX
Start 1
Stop
Start 2
Start 5
Stop 4
Stop 10 Start 11
Stop 13
RIDLE
Cleared by
Software
OERR
Cleared by
Software
UxRXIF
URXISEL = 00
Cleared by
Software
UxRXIF
URXISEL = 01
UxRXIF
URXISEL = 10
FIGURE 19-3:
TRANSMISSION (8-BIT OR 9-BIT DATA)
8 into TxBUF
Write to
UxTXREG
TSR
Pull from Buffer
BCLK/16
(Shift Clock)
UxTX
Start
Bit 0
Bit 1
Stop
Start
Bit 1
UxTXIF
UTXISEL = 00
UxTXIF
UTXISEL = 01
UxTXIF
UTXISEL = 10
DS61156C-page 136
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
20.0
PARALLEL MASTER PORT
(PMP)
Key features of the PMP module include:
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 13. “Parallel
Master Port (PMP)” (DS61128) in the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The PMP is a parallel 8-bit/16-bit input/output module
specifically designed to communicate with a wide
variety of parallel devices, such as communications
peripherals, LCDs, external memory devices and
microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP module is
highly configurable.
FIGURE 20-1:
•
•
•
•
•
•
•
•
•
•
•
•
8-Bit, 16-Bit Interface
Up to 16 Programmable Address Lines
Up to Two Chip Select Lines
Programmable Strobe Options
- Individual read and write strobes, or
- Read/write strobe with enable strobe
Address Auto-Increment/Auto-Decrement
Programmable Address/Data Multiplexing
Programmable Polarity on Control Signals
Parallel Slave Port Support
- Legacy addressable
- Address support
- 4-byte deep auto-incrementing buffer
Programmable Wait States
Operates during CPU Sleep and Idle modes
Fast Bit Manipulation using CLR, SET and INV
Registers
Freeze Option for In-Circuit Debugging
Note:
On 64-pin devices, data pins, PMD<15:8>,
are not available.
PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
Address Bus
Data Bus
PIC32MX5XX/6XX/7XX
Parallel
Master Port
Control Lines
PMA<0>
PMALL
PMA<1>
PMALH
Flash
EEPROM
SRAM
Up to 16-Bit Address
PMA<13:2>
PMA<14>
PMCS1
PMA<15>
PMCS2
PMRD
PMRD/PMWR
Microcontroller
PMWR
PMENB
PMD<7:0>
PMD<15:8>(1)
Note 1:
LCD
FIFO
Buffer
16/8-Bit Data (with or without multiplexed addressing)
On 64-pin devices, data pins, PMD<15:8>, are not available in 16-Bit Master modes.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 137
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 138
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
21.0
REAL-TIME CLOCK AND
CALENDAR (RTCC)
Following are some of the key features of this module:
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 29. “Real-Time
Clock
and
Calendar
(RTCC)”
(DS61125) in the “PIC32MX Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The PIC32MX RTCC module is intended for applications in which accurate time must be maintained for
extended periods of time with minimal or no CPU
intervention.
Low-power
optimization
provides
extended battery lifetime while keeping track of time.
FIGURE 21-1:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Time: Hours, Minutes and Seconds
24-Hour Format (Military Time)
Visibility of One Half Second Period
Provides Calendar: Weekday, Date, Month and
Year
Alarm Intervals are Configurable for Half of a
Second, One Second, 10 Seconds, One Minute,
10 Minutes, One Hour, One Day, One Week, One
Month and One Year
Alarm Repeat with Decrementing Counter
Alarm with Indefinite Repeat: Chime
Year Range: 2000 to 2099
Leap Year Correction
BCD Format for Smaller Firmware Overhead
Optimized for Long-Term Battery Operation
Fractional Second Synchronization
User Calibration of the Clock Crystal Frequency
with Auto-Adjust
Calibration Range: 0.66 Seconds Error per
Month
Calibrates up to 260 ppm of Crystal Error
Requirements: External 32.768 kHz Clock Crystal
Alarm Pulse or Seconds Clock Output on
RTCC Pin
RTCC BLOCK DIAGRAM
32.768 kHz Input
from Secondary
Oscillator (SOSC)
RTCC Prescalers
0.5s
YEAR, MTH, DAY
RTCVAL
RTCC Timer
Alarm
Event
WKDAY
HR, MIN, SEC
Comparator
MTH, DAY
Compare Registers
with Masks
ALRMVAL
WKDAY
HR, MIN, SEC
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
Seconds Pulse
RTCC Pin
RTCOE
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 139
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 140
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
22.0
10-BIT ANALOG-TO-DIGITAL
CONVERTER (ADC)
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 17. “10-Bit
Analog-to-Digital Converter (ADC)”
(DS61104) in the “PIC32MX Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The PIC32MX5XX/6XX/7XX 10-bit Analog-to-Digital
(A/D) Converter (or ADC) includes the following
features:
• Successive Approximation Register (SAR)
Conversion
• Up to 1 Msps Conversion Speed
• Up to 16 Analog Input Pins
• External Voltage Reference Input Pins
FIGURE 22-1:
• One Unipolar, Differential Sample and Hold
Amplifier (SHA)
• Automatic Channel Scan mode
• Selectable Conversion Trigger Source
• 16-word Conversion Result Buffer
• Selectable Buffer Fill modes
• Eight Conversion Result Format Options
• Operation during CPU Sleep and Idle modes
A block diagram of the 10-bit ADC is shown in
Figure 22-1. The 10-bit ADC has up to 16 analog input
pins, designated AN0-AN15. In addition, there are two
analog input pins for external voltage reference
connections. These voltage reference inputs may be
shared with other analog input pins and may be
common to other analog module references.
The analog inputs are connected through two multiplexers (MUXs) to one SHA. The analog input MUXs
can be switched between two sets of analog inputs
between conversions. Unipolar differential conversions
are possible on all channels, other than the pin used as
the reference, using a reference input pin (see
Figure 22-1).
The Analog Input Scan mode sequentially converts
user-specified channels. A control register specifies
which analog input channels will be included in the
scanning sequence.
The 10-bit ADC is connected to a 16-word result buffer.
Each 10-bit result is converted to one of eight 32-bit
output formats when it is read from the result buffer.
ADC1 MODULE BLOCK DIAGRAM
VREF+(1)
AVDD
VREF-(1)
AVSS
VCFG<2:0>
AN0
ADC1BUF0
ADC1BUF1
AN15
S/H
Channel
Scan
VREFH
VREFL
ADC1BUF2
+
CH0SB<4:0>
CH0SA<4:0>
SAR ADC
-
CSCNA
AN1
ADC1BUFE
VREFL
ADC1BUFF
CH0NA
CH0NB
Alternate
Input Selection
Note
1:
VREF+, VREF- inputs can be multiplexed with other analog inputs.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 141
PIC32MX5XX/6XX/7XX
FIGURE 22-2:
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
ADRC
FRC
Div 2
0
TAD
ADCS<7:0>
1
8
TPB
ADC Conversion
Clock Multiplier
2, 4,..., 512
DS61156C-page 142
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
23.0
CONTROLLER AREA
NETWORK (CAN)
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 34. “Controller
Area Network (CAN)” in the “PIC32MX
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The Controller Area Network (CAN) module supports
the following key features:
• Standards Compliance:
- Full CAN 2.0B compliance
- Programmable bit rate up to 1 Mbps
• Message Reception and Transmission:
- 32 message FIFOs
- Each FIFO can have up to 32 messages for a
total of 1024 messages
- FIFO can be a transmit message FIFO or a
receive message FIFO
- User-defined priority levels for message
FIFOs used for transmission
- 32 acceptance filters for message filtering
- Four acceptance filter mask registers for
message filtering
- Automatic response to remote transmit request
- DeviceNet™ addressing support
• Additional Features:
- Loopback, Listen All Messages and Listen
Only modes for self-test, system diagnostics
and bus monitoring
- Low-power operating modes
- CAN module is a bus master on the
PIC32MX system bus
- Use of DMA is not required
- Dedicated time-stamp timer
- Dedicated DMA channels
- Data Only Message Reception mode
Figure 23-1 illustrates the general structure of the CAN
module.
FIGURE 23-1:
PIC32MX CAN MODULE BLOCK DIAGRAM
CxTX
32 Filters
4 Masks
CPU
CxRX
CAN Module
Up to 32 Message Buffers
System Bus
Message
Buffer Size
2 or 4 Words
System RAM
Message Buffer 31
Message Buffer 31
Message Buffer 31
Message Buffer 1
Message Buffer 0
Message Buffer 1
Message Buffer 0
Message Buffer 1
Message Buffer 0
FIFO1
FIFO31
FIFO0
CAN Message FIFO (up to 32 FIFOs)
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 143
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 144
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
24.0
ETHERNET CONTROLLER
Following are some of the key features of this module:
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 35. “Ethernet
Controller” in the “PIC32MX Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
•
•
•
•
•
•
•
•
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The Ethernet controller is a bus master module that
interfaces with an off-chip Physical Layer (PHY) to
implement a complete Ethernet node in a system.
Figure 24-1 shows a block diagram of the Ethernet
controller.
ETHERNET CONTROLLER BLOCK DIAGRAM
TX
FIFO
FIGURE 24-1:
•
•
Supports 10/100 Mbps Data Transfer Rates
Supports Full-Duplex and Half-Duplex Operation
Supports RMII and MII PHY Interface
Supports MIIM PHY Management Interface
Supports both Manual and Automatic Flow Control
RAM Descriptor-Based DMA Operation for Both
Receive and Transmit Path
Fully Configurable Interrupts
Configurable Receive Packet Filtering
- CRC Check
- 64-Byte Pattern Match
- Broadcast, Multicast and Unicast packets
- Magic Packet™
- 64-Bit Hash Table
- Runt Packet
Supports Packet Payload Checksum Calculation
Supports Various Hardware Statistics Counters
TX DMA
TX BM
TX Bus
Master
TX Function
TX Flow Control
System Bus
MII/RMII
IF
RX
FIFO
RX DMA
RX Flow
Control
RX BM
External
PHY
MAC
RX Bus
Master
RX Filter
RX Function
Checksum
Fast Peripheral
Bus
DMA
Control
Registers
Ethernet DMA
MIIM
IF
MAC Control
and
Configuration
Registers
Host IF
Ethernet Controller
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 145
PIC32MX5XX/6XX/7XX
Table 24-1, Table 24-2, Table 24-3 and Table 24-4
show four interfaces and the associated pins that can
be used with the Ethernet Controller.
TABLE 24-1:
MII MODE DEFAULT
INTERFACE SIGNALS
(FMIIEN = 1, FETHIO = 1)
Pin Name
Pin Name
Description
EMDC
Management Clock
EMDIO
Management IO
ETXCLK
Transmit Clock
ETXEN
Transmit Enable
ETXD0
Transmit Data
ETXD1
Transmit Data
ETXD2
Transmit Data
ETXD3
Transmit Data
ETXERR
Transmit Error
ERXCLK
Receive Clock
ERXDV
Receive Data Valid
ERXD0
Receive Data
ERXD1
Receive Data
ERXD2
Receive Data
ERXD3
Receive Data
ERXERR
Receive Error
ECRS
Carrier Sense
ECOL
Collision Indication
TABLE 24-3:
Management Clock
AEMDIO
Management IO
AETXCLK
Transmit Clock
AETXEN
Transmit Enable
AETXD0
Transmit Data
AETXD1
Transmit Data
AETXD2
Transmit Data
AETXD3
Transmit Data
AETXERR
Transmit Error
AERXCLK
Receive Clock
AERXDV
Receive Data Valid
AERXD0
Receive Data
AERXD1
Receive Data
AERXD2
Receive Data
AERXD3
Receive Data
AERXERR
Receive Error
AECRS
Carrier Sense
AECOL
Collision Indication
Note 1:
RMII MODE DEFAULT
INTERFACE SIGNALS
(FMIIEN = 0, FETHIO = 1)
Pin Name
MII Alternate Interface is not available on
64-pin devices.
Pin Name
Description
Description
AEMDC
TABLE 24-4:
TABLE 24-2:
MII MODE ALTERNATE
INTERFACE SIGNALS
(FMIIEN = 1, FETHIO = 0)(1)
AEMDC
RMII MODE ALTERNATE
INTERFACE SIGNALS
(FMIIEN = 0, FETHIO = 0)
Description
Management Clock
EMDC
Management Clock
AEMDIO
Management IO
EMDIO
Management IO
AETXEN
Transmit Enable
ETXEN
Transmit Enable
AETXD0
Transmit Data
ETXD0
Transmit Data
AETXD1
Transmit Data
ETXD1
Transmit Data
AEREFCLK
Reference Clock
EREFCLK
Reference Clock
AECRSDV
Carrier Sense – Receive Data Valid
ECRSDV
Carrier Sense – Receive Data Valid
AERXD0
Receive Data
ERXDV
Receive Data Valid
AERXD1
Receive Data
ERXD0
Receive Data
AERXERR
Receive Error
ERXD1
Receive Data
ERXERR
Receive Error
DS61156C-page 146
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
25.0
COMPARATOR
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this
data sheet, refer to Section 19.
“Comparator”
(DS61110) in the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
FIGURE 25-1:
The PIC32MX5XX/6XX/7XX analog comparator
module contains two comparators that can be
configured in a variety of ways.
Following are some of the key features of this module:
• Selectable Inputs Available Include:
- Analog inputs multiplexed with I/O pins
- On-chip internal absolute Voltage Reference
(IVREF)
- Comparator Voltage Reference (CVREF)
• Outputs can be Inverted
• Selectable Interrupt Generation
A block diagram of the comparator module is shown in
Figure 25-1.
COMPARATOR BLOCK DIAGRAM
Comparator 1
CREF
ON
C1IN+(1)
CPOL
COUT (CM1CON)
C1OUT (CMSTAT)
CVREF(2)
C1OUT
CCH<1:0>
C1
C1IN-
COE
C1IN+
C2IN+
IVREF(2)
Comparator 2
CREF
ON
C2IN+
CPOL
COUT (CM2CON)
C2OUT (CMSTAT)
CVREF(2)
C2OUT
CCH<1:0>
C2
C2IN-
COE
C2IN+
C1IN+
IVREF(2)
Note 1:
2:
On devices with a USB module, and when the module is enabled, this pin is controlled by the USB module,
and therefore, is not available as a comparator input.
Internally connected.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 147
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 148
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
26.0
COMPARATOR VOLTAGE
REFERENCE (CVREF)
The CVREF module is a 16-tap, resistor ladder network
that provides a selectable reference voltage. Although
its primary purpose is to provide a reference for the
analog comparators, it also may be used independently
of them.
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a comprehensive reference source. To complement
the information in this data sheet, refer to
Section 20. “Comparator Voltage
(DS61109) in the
Reference (CVREF)”
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
A block diagram of the module is shown in Figure 26-1.
The resistor ladder is segmented to provide two ranges
of voltage reference values and has a power-down
function to conserve power when the reference is not
being used. The module’s supply reference can be provided from either device VDD/VSS or an external
voltage reference. The CVREF output is available for
the comparators and typically available for pin output.
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
FIGURE 26-1:
VREF+
AVDD
The comparator voltage reference has the following
features:
• High and low range selection
• Sixteen output levels available for each range
• Internally connected to comparators to conserve
device pins
• Output can be connected to a pin
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
8R
CVRSS = 0
CVR<3:0>
R
CVREN
CVREF
R
R
16-to-1 MUX
R
16 Steps
R
CVREFOUT
CVRCON<CVROE>
R
R
CVRR
VREFAVSS
 2010 Microchip Technology Inc.
8R
CVRSS = 1
CVRSS = 0
Preliminary
DS61156C-page 149
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 150
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
27.0
POWER-SAVING FEATURES
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a comprehensive reference source. To complement
the information in this data sheet, refer to
Section 10. “Power-Saving Features”
(DS61130) in the “PIC32MX Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be available on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
This section describes power-saving features for the
PIC32MX5XX/6XX/7XX. The PIC32MX devices offer a
total of nine methods and modes, organized into two
categories, that allow the user to balance power
consumption with device performance. In all of the
methods and modes described in this section, power
saving is controlled by software.
27.1
Power Saving with CPU Running
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency, lowering the PBCLK and by individually disabling modules.
These methods are grouped into the following
categories:
• FRC Run mode: the CPU is clocked from the FRC
clock source with or without postscalers.
• LPRC Run mode: the CPU is clocked from the
LPRC clock source.
• SOSC Run mode: the CPU is clocked from the
SOSC clock source.
In addition, the Peripheral Bus Scaling mode is available
where peripherals are clocked at the programmable
fraction of the CPU clock (SYSCLK).
27.2
CPU Halted Methods
The device supports two power-saving modes, Sleep
and Idle, both of which Halt the clock to the CPU. These
modes operate with all clock sources, as listed below:
• POSC Idle mode: the system clock is derived from
the POSC. The system clock source continues to
operate.
Peripherals continue to operate, but can
optionally be individually disabled.
• FRC Idle mode: the system clock is derived from
the FRC with or without postscalers.
Peripherals continue to operate, but can
optionally be individually disabled.
 2010 Microchip Technology Inc.
• SOSC Idle mode: the system clock is derived from
the SOSC.
Peripherals continue to operate, but can
optionally be individually disabled.
• LPRC Idle mode: the system clock is derived from
the LPRC.
Peripherals continue to operate, but can optionally be individually disabled. This is the lowest
power mode for the device with a clock running.
• Sleep mode: the CPU, the system clock source
and any peripherals that operate from the system
clock source are Halted.
Some peripherals can operate in Sleep using
specific clock sources. This is the lowest power
mode for the device.
27.3
Power-Saving Operation
Peripherals and the CPU can be Halted or disabled to
further reduce power consumption.
27.3.1
SLEEP MODE
Sleep mode has the lowest power consumption of the
device power-saving operating modes. The CPU and
most peripherals are Halted. Select peripherals can
continue to operate in Sleep mode and can be used to
wake the device from Sleep. See the individual peripheral module sections for descriptions of behavior in
Sleep.
Sleep mode includes the following characteristics:
• The CPU is Halted.
• The system clock source is typically shut down.
See Section 27.3.3 “Peripheral Bus Scaling
Method” for specific information.
• There can be a wake-up delay based on the
oscillator selection.
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode.
• The BOR circuit, if enabled, remains operative
during Sleep mode.
• The WDT, if enabled, is not automatically cleared
prior to entering Sleep mode.
• Some peripherals can continue to operate at
limited functionality in Sleep mode. These peripherals include I/O pins that detect a change in the
input signal, WDT, ADC, UART and peripherals
that use an external clock input or the internal
LPRC oscillator (e.g., RTCC, Timer1 and Input
Capture).
• I/O pins continue to sink or source current in the
same manner as they do when the device is not in
Sleep.
• The USB module can override the disabling of the
Posc or FRC. Refer to the USB section for
specific details.
• Modules can be individually disabled by software
prior to entering Sleep in order to further reduce
consumption.
Preliminary
DS61156C-page 151
PIC32MX5XX/6XX/7XX
The processor will exit, or ‘wake-up’, from Sleep on one
of the following events:
The processor will wake or exit from Idle mode on the
following events:
• On any interrupt from an enabled source that is
operating in Sleep. The interrupt priority must be
greater than the current CPU priority.
• On any form of device Reset.
• On a WDT time-out.
If the interrupt priority is lower than or equal to the
current priority, the CPU will remain Halted, but the
PBCLK will start running and the device will enter into
Idle mode.
• On any interrupt event for which the interrupt
source is enabled. The priority of the interrupt
event must be greater than the current priority of
the CPU. If the priority of the interrupt event is
lower than or equal to current priority of the CPU,
the CPU will remain Halted and the device will
remain in Idle mode.
• On any form of device Reset
• On a WDT time-out interrupt
27.3.2
27.3.3
IDLE MODE
In Idle mode, the CPU is Halted but the System Clock
(SYSCLK) source is still enabled. This allows peripherals to continue operation when the CPU is Halted.
Peripherals can be individually configured to Halt when
entering Idle by setting their respective SIDL bit.
Latency, when exiting Idle mode, is very low due to the
CPU oscillator source remaining active.
Notes: Changing the PBCLK divider ratio
requires recalculation of peripheral timing.
For example, assume the UART is configured for 9600 baud with a PB clock ratio of
1:1 and a POSC of 8 MHz. When the PB
clock divisor of 1:2 is used, the input
frequency to the baud clock is cut in half;
therefore, the baud rate is reduced to 1/2
its former value. Due to numeric truncation
in calculations (such as the baud rate divisor), the actual baud rate may be a tiny
percentage different than expected. For
this reason, any timing calculation
required for a peripheral should be performed with the new PB clock frequency
instead of scaling the previous value
based on a change in the PB divisor ratio.
Oscillator start-up and PLL lock delays
are applied when switching to a clock
source that was disabled and that uses a
crystal and/or the PLL. For example,
assume the clock source is switched from
POSC to LPRC just prior to entering Sleep
in order to save power. No oscillator startup delay would be applied when exiting
Idle. However, when switching back to
POSC, the appropriate PLL and or oscillator start-up/lock delays would be applied.
The device enters Idle mode when the SLPEN
(OSCCON<4>) bit is clear and a WAIT instruction is
executed.
DS61156C-page 152
PERIPHERAL BUS SCALING
METHOD
Most of the peripherals on the device are clocked using
the PBCLK. The peripheral bus can be scaled relative to
the SYSCLK to minimize the dynamic power consumed
by the peripherals. The PBCLK divisor is controlled by
PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to
PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals
using PBCLK are affected when the divisor is changed.
Peripherals, such as the interrupt controller, DMA, bus
matrix and prefetch cache, are clocked directly from
SYSCLK. As a result, they are not affected by PBCLK
divisor changes.
Most of the peripherals on the device are clocked using
the PBCLK. The peripheral bus can be scaled relative to
the SYSCLK to minimize the dynamic power consumed
by the peripherals. The PBCLK divisor is controlled by
PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to
PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals
using PBCLK are affected when the divisor is changed.
Peripherals such as USB, interrupt controller, DMA, bus
matrix and prefetch cache are clocked directly from
SYSCLK. As a result, they are not affected by PBCLK
divisor changes
Changing the PBCLK divisor affects:
• The CPU to peripheral access latency. The CPU
has to wait for next PBCLK edge for a read to
complete. In 1:8 mode, this results in a latency of
one to seven SYSCLKs.
• The power consumption of the peripherals. Power
consumption is directly proportional to the frequency at which the peripherals are clocked. The
greater the divisor, the lower the power consumed
by the peripherals.
To minimize dynamic power, the PB divisor should be
chosen to run the peripherals at the lowest frequency
that provides acceptable system performance. When
selecting a PBCLK divider, peripheral clock requirements, such as baud rate accuracy, should be taken
into account. For example, the UART peripheral may
not be able to achieve all baud rate values at some
PBCLK divider depending on the SYSCLK value.
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
28.0
SPECIAL FEATURES
Note:
This data sheet summarizes the features of
the PIC32MX5XX/6XX/7XX family family of
devices. It is not intended to be a comprehensive reference source. To complement
the information in this data sheet, refer to
the related section in the “PIC32MX Family
Reference Manual” (DS61132), which is
available from the Microchip web site
(www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
•
•
•
•
Flexible Device Configuration
Watchdog Timer
JTAG Interface
In-Circuit Serial Programming™ (ICSP™)
28.1
Configuration Bits
The Configuration bits can be programmed to select
various device configurations.
REGISTER 28-1:
DEVCFG0: DEVICE CONFIGURATION WORD 0
r-0
r-1
r-1
R/P-1
r-1
r-1
r-1
R/P-1
—
—
—
CP
—
—
—
BWP
bit 31
bit 24
r-1
r-1
r-1
r-1
—
—
—
—
R/P-1
R/P-1
R/P-1
R/P-1
PWP<7:4>
bit 23
bit 16
R/P-1
R/P-1
R/P-1
R/P-1
PWP<3:0>
r-1
r-1
r-1
r-1
—
—
—
—
bit 15
bit 8
r-1
r-1
r-1
r-1
R/P-1
r-1
—
—
—
—
ICESEL
—
R/P-1
R/P-1
DEBUG<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
P = Programmable bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r = Reserved bit
bit 31
Reserved: Write ‘0’
bit 30-29
Reserved: Write ‘1’
bit 28
CP: Code-Protect bit
Prevents boot and program Flash memory from being read or modified by an external
programming device.
1 = Protection is disabled
0 = Protection is enabled
bit 27-25
Reserved: Write ‘1’
bit 24
BWP: Boot Flash Write-Protect bit
Prevents boot Flash memory from being modified during code execution.
1 = Boot Flash is writable
0 = Boot Flash is not writable
bit 23-20
Reserved: Write ‘1’
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 153
PIC32MX5XX/6XX/7XX
REGISTER 28-1:
DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)
bit 19-12
PWP<7:0>: Program Flash Write-Protect bits
Prevents selected program Flash memory pages from being modified during code execution.
The PWP bits represent the one’s compliment of the number of write-protected program Flash
memory pages.
11111111 = Disabled
11111110 = 0xBD00_0FFF
11111101 = 0xBD00_1FFF
11111100 = 0xBD00_2FFF
11111011 = 0xBD00_3FFF
11111010 = 0xBD00_4FFF
11111001 = 0xBD00_5FFF
11111000 = 0xBD00_6FFF
11110111 = 0xBD00_7FFF
11110110 = 0xBD00_8FFF
11110101 = 0xBD00_9FFF
11110100 = 0xBD00_AFFF
11110011 = 0xBD00_BFFF
11110010 = 0xBD00_CFFF
11110001 = 0xBD00_DFFF
11110000 = 0xBD00_EFFF
11101111 = 0xBD00_FFFF
•
•
•
01111111 = 0xBD07_FFFF
bit 11-4
Reserved: Write ‘1’
bit 3
ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit
1 = PGEC2/PGED2 pair is used
0 = PGEC1/PGED1 pair is used
bit 2
Reserved: Write ‘1’
bit 1-0
DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)
11 = Debugger is disabled
10 = Debugger is enabled
01 = Reserved (same as ‘11’ setting)
00 = Reserved (same as ‘11’ setting)
DS61156C-page 154
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 28-2:
DEVCFG1: DEVICE CONFIGURATION WORD 1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
bit 31
bit 24
R/P-1
r-1
r-1
FWDTEN
—
—
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
WDTPS<4:0>
bit 23
bit 16
R/P-1
R/P-1
R/P-1
FCKSM<1:0>
R/P-1
FPBDIV<1:0>
r-1
R/P-1
—
OSCIOFNC
R/P-1
R/P-1
POSCMOD<1:0>
bit 15
bit 8
R/P-1
r-1
R/P-1
r-1
r-1
IESO
—
FSOSCEN
—
—
R/P-1
R/P-1
R/P-1
FNOSC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
P = Programmable bit
bit 31-24
Reserved: Write ‘1’
bit 23
FWDTEN: Watchdog Timer Enable bit
1 = The WDT is enabled and cannot be disabled by software
0 = The WDT is not enabled; it can be enabled in software
bit 22-21
Reserved: Write ‘1’
bit 20-16
WDTPS<4:0>: Watchdog Timer Postscale Select bits
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
All other combinations not shown result in operation = 10100
r = Reserved bit
Note 1: Do not disable POSC (POSCMOD = 11) when using this oscillator source.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 155
PIC32MX5XX/6XX/7XX
REGISTER 28-2:
DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED)
bit 15-14
FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 13-12
FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits
11 = PBCLK is SYSCLK divided by 8
10 = PBCLK is SYSCLK divided by 4
01 = PBCLK is SYSCLK divided by 2
00 = PBCLK is SYSCLK divided by 1
bit 11
Reserved: Write ‘1’
bit 10
OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for
the External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11 or 00)
0 = CLKO output disabled
bit 9-8
POSCMOD<1:0>: Primary Oscillator Configuration bits
11 = Primary oscillator disabled
10 = HS Oscillator mode selected
01 = XT Oscillator mode selected
00 = External Clock mode selected
bit 7
IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled)
0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled)
bit 6
Reserved: Write ‘1’
bit 5
FSOSCEN: Secondary Oscillator Enable bit
1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator
bit 4-3
Reserved: Write ‘1’
bit 2-0
FNOSC<2:0>: Oscillator Selection bits
000 = Fast RC Oscillator (FRC)
001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)
010 = Primary Oscillator (XT, HS, EC)(1)
011 = Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL)
100 = Secondary Oscillator (SOSC)
101 = Low-Power RC Oscillator (LPRC)
110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler
111 = Fast RC Oscillator with divide-by-N (FRCDIV)
Note 1: Do not disable POSC (POSCMOD = 11) when using this oscillator source.
DS61156C-page 156
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 28-3:
DEVCFG2: DEVICE CONFIGURATION WORD 2
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
bit 31
bit 24
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
R/P-1
R/P-1
R/P-1
FPLLODIV<2:0>
bit 23
bit 16
R/P-1
r-1
r-1
r-1
r-1
UPLLEN
—
—
—
—
R/P-1
R/P-1
R/P-1
UPLLIDIV<2:0>
bit 15
bit 8
r-1
R/P-1
—
R/P-1
R/P-1
r-1
FPLLMULT<2:0>
R/P-1
—
R/P-1
R/P-1
FPLLIDIV<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
P = Programmable bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31-19
Reserved: Write ‘1’
bit 18-16
FPLLODIV<2:0>: Default Postscaler for PLL bits
111 = PLL output divided by 256
110 = PLL output divided by 64
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 1
bit 15
UPLLEN: USB PLL Enable bit
1 = Enable USB PLL
0 = Disable and bypass USB PLL
bit 14-11
Reserved: Write ‘1’
bit 10-8
UPLLIDIV<2:0>: PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
bit 7
Reserved: Write ‘1’
 2010 Microchip Technology Inc.
Preliminary
r = Reserved bit
DS61156C-page 157
PIC32MX5XX/6XX/7XX
REGISTER 28-3:
DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED)
bit 6-4
FPLLMULT<2:0>: PLL Multiplier bits
111 = 24x multiplier
110 = 21x multiplier
101 = 20x multiplier
100 = 19x multiplier
011 = 18x multiplier
010 = 17x multiplier
001 = 16x multiplier
000 = 15x multiplier
bit 3
Reserved: Write ‘1’
bit 2-0
FPLLIDIV<2:0>: PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
DS61156C-page 158
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 28-4:
DEVCFG3: DEVICE CONFIGURATION WORD 3
R/P-1
R/P-1
r-1
r-1
r-1
R/P-1
R/P-1
R/P-1
FVBUSONIO
FUSBIDIO
—
—
—
FCANIO
FETHIO
FMIIEN
bit 31
bit 24
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
R/P-1
R/P-1
R/P-1
FSRSSEL<2:0>
bit 23
bit 16
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
USERID<15:8>
bit 15
bit 8
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
USERID<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
P = Programmable bit
r = Reserved bit
bit 31
FVBUSONIO: USB VBUS_ON Selection bit
1 = VBUSON pin is controlled by the USB module
0 = VBUSON pin is controlled by the port function
bit 30
FUSBIDIO: USB USBID Selection bit
1 = USBID pin is controlled by the USB module
0 = USBID pin is controlled by the port function
bit 29-27
Reserved: Write ‘1’
bit 26
FCANIO: CAN I/O Pin Selection bit
1 = Default CAN I/O Pins
0 = Alternate CAN I/O Pins
bit 25
FETHIO: Ethernet I/O Pin Selection bit
1 = Default Ethernet I/O Pins
0 = Alternate Ethernet I/O Pins
bit 24
FMIIEN: Ethernet MII Enable bit
1 = MII is enabled
0 = RMII is enabled
bit 23-19
Reserved: Write ‘1’
bit 18-16
FSRSSEL<2:0>: SRS Select bits
111 = Assign Interrupt Priority 7 to a shadow register set
110 = Assign Interrupt Priority 6 to a shadow register set
•
•
•
001 = Assign Interrupt Priority 1 to a shadow register set
000 = All interrupt priorities are assigned to a shadow register set
bit 15-0
USERID<15:0>: This is a 16-bit value that is user-defined and is readable via ICSP™ and JTAG
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 159
PIC32MX5XX/6XX/7XX
REGISTER 28-5:
R
DEVID: DEVICE AND REVISION ID REGISTER
R
R
R
R
VER<3:0>(1)
R
R
DEVID<27:24>
R
(1)
bit 31
bit 24
R
R
R
R
R
R
R
R
(1)
DEVID<23:16>
bit 23
bit 16
R
R
R
R
R
DEVID<15:8>
R
R
R
(1)
bit 15
bit 8
R
R
R
R
R
R
R
R
DEVID<7:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
P = Programmable bit
bit 31-28
VER<3:0>: Revision Identifier bits(1)
bit 27-0
DEVID<27:0>: Device ID(1)
Note 1:
r = Reserved bit
See the “PIC32MX Flash Programming Specification” (DS61145) for a list of Revision and Device ID values.
DS61156C-page 160
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
28.2
Watchdog Timer (WDT)
This section describes the operation of the WDT and
Power-up Timer of the PIC32MX5XX/6XX/7XX.
The WDT, when enabled, operates from the internal
Low-Power Oscillator (LPRC) clock source and can be
used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in
software. Various WDT time-out periods can be
selected using the WDT postscaler. The WDT can also
be used to wake the device from Sleep or Idle mode.
FIGURE 28-1:
The following are some of the key features of the WDT
module:
• Configuration or software controlled
• User-configurable time-out period
• Can wake the device from Sleep or Idle
WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM
PWRT Enable
WDT Enable
LPRC
Control
PWRT Enable
1:64 Output
LPRC
Oscillator
PWRT
1
Clock
25-Bit Counter
WDTCLR = 1
WDT Enable
Wake
WDT Enable
Reset Event
25
0
1
WDT Counter Reset
Device Reset
NMI (Wake-up)
Power Save
Decoder
FWDTPS<4:0>(DEVCFG1<20:16>)
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 161
PIC32MX5XX/6XX/7XX
28.3
On-Chip Voltage Regulator
28.3.3
POWER-UP REQUIREMENTS
All PIC32MX5XX/6XX/7XX devices’ core and digital
logic are designed to operate at a nominal 1.8V. To
simplify system designs, most devices in the
PIC32MX5XX/6XX/7XX family incorporate an on-chip
regulator providing the required core logic voltage from
VDD.
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, VDDCORE must
never exceed VDD by 0.3 volts.
A low-ESR capacitor (such as tantalum) must be connected to the VCAP/VDDCORE pin (see Figure 28-2).
This helps to maintain the stability of the regulator.
The recommended value for the filter capacitor is
provided in Section 31.1 “DC Characteristics”.
FIGURE 28-2:
Note:
28.3.1
3.3V(1)
PIC32MX
VDD
It is important that the low-ESR capacitor
is placed as close as possible to the
VCAP/VDDCORE pin.
VCAP/VDDCORE
ON-CHIP REGULATOR AND POR
It takes a fixed delay for the on-chip regulator to generate
an output. During this time, designated as TPU, code execution is disabled. TPU is applied every time the device
resumes operation after any power-down, including
Sleep mode.
CEFC(2)
(10 F typ)
Note 1:
If the regulator is disabled, a separate Power-up Timer
(PWRT) is automatically enabled. The PWRT adds a
fixed delay of TPWRT at device start-up. See
Section 31.0 “Electrical Characteristics” for more
information on TPU AND TPWRT.
28.3.2
CONNECTIONS FOR THE
ON-CHIP REGULATOR
2:
VSS
These are typical operating voltages. Refer
to Section 31.1 “DC Characteristics” for
the full operating ranges of VDD and
VDDCORE.
It is important that the low-ESR capacitor
is placed as close as possible to the
VCAP/VDDCORE pin.
ON-CHIP REGULATOR AND BOR
PIC32MX5XX/6XX/7XX devices also have a simple
brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the
regulator Reset circuitry will generate a Brown-out
Reset. This event is captured by the BOR flag bit
(RCON<1>). The brown-out voltage levels are specific
in Section 31.1 “DC Characteristics”.
DS61156C-page 162
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
28.4
Programming and Diagnostics
PIC32MX5XX/6XX/7XX devices provide a complete
range of programming and diagnostic features that can
increase the flexibility of any application using them.
These features allow system designers to include:
• Simplified field programmability using two-wire
In-Circuit Serial Programming™ (ICSP™)
interfaces
• Debugging using ICSP
• Programming and debugging capabilities using
the EJTAG extension of JTAG
• JTAG boundary scan testing for device and board
diagnostics
FIGURE 28-3:
PIC32MX devices incorporate two programming and
diagnostic modules, and a trace controller, that provide
a range of functions to the application developer.
BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS
PGEC1
PGED1
ICSP™
Controller
PGEC2
PGED2
ICESEL
TDI
TDO
JTAG
Controller
TCK
Core
TMS
JTAGEN
DEBUG<1:0>
TRCLK
TRD0
TRD1
Instruction Trace
Controller
TRD2
TRD3
DEBUG<1:0>
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 163
PIC32MX5XX/6XX/7XX
REGISTER 28-6:
DDPCON: DEBUG DATA PORT CONTROL REGISTER
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
—
—
—
—
—
—
—
—
bit 31
bit 24
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
—
—
—
—
—
—
—
—
bit 23
bit 16
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
—
—
—
—
—
—
—
—
bit 15
bit 8
r-0
r-0
r-0
r-0
R/W-1
R/W-0
r-0
r-0
—
—
—
—
JTAGEN
TROEN
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31-4
Reserved: Write ‘0’; ignore read
bit 3
JTAGEN: JTAG Port Enable bit
1 = Enable the JTAG port
0 = Disable the JTAG port
bit 2
TROEN: Trace Output Enable bit
1 = Enable the trace port
0 = Disable the trace port
bit 1-0
Reserved: Write ‘1’; ignore read
DS61156C-page 164
P = Programmable bit
Preliminary
r = Reserved bit
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
29.0
INSTRUCTION SET
The PIC32MX5XX/6XX/7XX family instruction set
complies with the MIPS32 Release 2 instruction set
architecture. PIC32MX does not support the following
features:
• Core Extend Instructions
• Coprocessor 1 Instructions
• Coprocessor 2 Instructions
Note:
Refer to “MIPS32® Architecture for Programmers Volume II: The MIPS32®
Instruction Set” at www.mips.com for more
information.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 165
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 166
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
30.0
DEVELOPMENT SUPPORT
30.1
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 167
PIC32MX5XX/6XX/7XX
30.2
MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
30.3
HI-TECH C for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple
platforms.
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
30.4
30.5
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
30.6
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS61156C-page 168
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
30.7
MPLAB SIM Software Simulator
30.9
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
30.8
MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including
low-cost, full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
 2010 Microchip Technology Inc.
MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
30.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
Preliminary
DS61156C-page 169
PIC32MX5XX/6XX/7XX
30.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
30.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a breakpoint, the file registers can be examined and modified.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
30.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
DS61156C-page 170
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
31.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC32MX5XX/6XX/7XX electrical characteristics. Additional information will be
provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC32MX5XX/6XX/7XX devices are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these or any other
conditions, above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias.............................................................................................................. .-40°C to +85°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3) ......................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD  2.3V (Note 3) ........................................ -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3) ............................. -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.0V
Maximum current out of VSS pin(s) .......................................................................................................................300 mA
Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 2) ....................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions,
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 31-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 171
PIC32MX5XX/6XX/7XX
31.1
DC Characteristics
TABLE 31-1:
OPERATING MIPS VS. VOLTAGE
Characteristic
Temp. Range
(in °C)
PIC32MX5XX/6XX/7XX
2.3-3.6V
-40°C to +85°C
80 MHz (Note 1)
DC5
Note 1:
Max. Frequency
VDD Range
(in Volts)
40 MHz maximum for PIC32MX 40 MHz family variants.
TABLE 31-2:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min.
Typical
Max.
Unit
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
PIC32MX5XX/6XX/7XX
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – S IOH)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
I/O Pin Power Dissipation:
I/O = S ({VDD – VOH} x IOH) + S (VOL x IOL))
Maximum Allowed Power Dissipation
TABLE 31-3:
THERMAL PACKAGING CHARACTERISTICS
Characteristics
Symbol Typical
Max.
Unit
Notes
Package Thermal Resistance, 121-Pin XBGA (10x10x1.1 mm)
JA
40
—
°C/W
1
Package Thermal Resistance, 100-Pin TQFP (14x14x1 mm)
JA
43
—
°C/W
1
Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm)
JA
43
—
°C/W
1
Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm)
JA
47
—
°C/W
1
Package Thermal Resistance, 64-Pin QFN (9x9x0,9 mm)
JA
28
—
°C/W
1
Note 1:
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
TABLE 31-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typical
Max.
Units
2.3
—
3.6
V
Conditions
Operating Voltage
DC10
Supply Voltage
VDD
DC12
VDR
RAM Data Retention Voltage
(Note 1)
1.75
—
—
V
DC16
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
1.75
—
1.95
V
DC17
SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.00005
—
0.115
V/s
Note 1:
This is the limit to which VDD can be lowered without losing RAM data.
DS61156C-page 172
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical(3)
Max.
Units
Conditions
Operating Current (IDD)(1,2)
DC20
6
9
mA
Code executing from Flash
—
DC20c
4
—
mA
Code executing from SRAM
—
DC21
37
40
mA
Code executing from Flash
—
DC21c
25
—
mA
Code executing from SRAM
—
DC22
64
70
mA
Code executing from Flash
—
DC22c
61
—
mA
Code executing from SRAM
—
DC23
85
98
mA
Code executing from Flash
—
DC23c
85
—
mA
Code executing from SRAM
—
DC25a
125
150
µA
Note 1:
2:
3:
4:
+25°C
3.3V
4 MHz
25 MHz
(Note 4)
60 MHz
(Note 4)
80 MHz
LPRC (31 kHz)
(Note 4)
A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
The test conditions for IDD measurements are as follows: Oscillator mode = EC+PLL with OSC1 driven by
external square wave from rail-to-rail and PBCLK divisor = 1:8. CPU, Program Flash and SRAM data
memory are operational, Program Flash memory Wait states = 7, program cache and prefetch are disabled and SRAM data memory Wait states = 1. All peripheral modules are disabled (ON bit = 0). WDT and
FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD.
Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
This parameter is characterized, but not tested in manufacturing.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 173
PIC32MX5XX/6XX/7XX
TABLE 31-6:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical(2)
Max.
Units
Conditions
Idle Current (IIDLE): Core Off, Clock On Base Current (Note 1)
DC30
4.5
6.5
mA
4 MHz
DC31
13
15
mA
25 MHz (Note 3)
DC32
28
30
mA
60 MHz (Note 3)
DC33
36
42
mA
DC34
—
40
µA
-40°C
DC34a
—
75
µA
+25°C
DC34b
—
800
µA
+85°C
80 MHz
DC35
35
—
µA
-40°C
DC35a
65
—
µA
+25°C
DC35b
600
—
µA
+85°C
DC36
—
43
µA
-40°C
DC36a
—
106
µA
+25°C
DC36b
—
800
µA
+85°C
Note 1:
2:
3:
2.3V
3.3V
LPRC (31 kHz)
(Note 3)
3.6V
The test conditions for base IDLE current measurements are as follows: System clock is enabled and
PBCLK divisor = 1:8. CPU in Idle mode (CPU core Halted). Only digital peripheral modules are enabled
(ON bit = 1) and being clocked. WDT and FSCM are disabled. All I/O pins are configured as inputs and
pulled to VSS. MCLR = VDD.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
This parameter is characterized, but not tested in manufacturing.
DS61156C-page 174
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-7:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
DC CHARACTERISTICS
Parameter
No.
Typical(2)
Max.
Units
Conditions
Power-Down Current (IPD) (Note 1)
DC40
10
40
A
-40°C
DC40a
36
100
A
+25°C
DC40b
400
720
A
+85°C
DC40c
41
120
A
+25°C
DC40d
22
80
A
-40°C
DC40e
42
120
A
+25°C
DC40g
315
400
A
+70°C
DC40f
410
800
A
+85°C
2.3V
Base Power-Down Current (Note 6)
3.3V
Base Power-Down Current
3.6V
Base Power-Down Current
Module Differential Current
DC41
—
10
A
2.3V
Watchdog Timer Current: IWDT (Notes 3, 6)
DC41c
5
—
A
3.3V
Watchdog Timer Current: IWDT (Note 3)
DC41d
—
20
A
3.6V
Watchdog Timer Current: IWDT (Note 3)
DC42
—
40
A
2.3V
RTCC + Timer1 w/32 kHz Crystal: IRTCC
(Notes 3, 6)
DC42c
23
—
A
DC42e
—
50
A
DC43
—
1300
DC43c
1100
DC43e
—
Note 1:
2:
3:
4:
5:
6:
3.3V
RTCC + Timer1 w/32 kHz Crystal: IRTCC
(Note 3)
3.6V
RTCC + Timer1 w/32 kHz Crystal: IRTCC
(Note 3)
A
2.5V
ADC: IADC (Notes 3, 4, 6)
—
A
3.3V
ADC: IADC (Notes 3, 4)
1300
A
3.6V
ADC: IADC (Notes 3, 4)
Base IPD is measured with all digital peripheral modules and being clocked, CPU clock is disabled. All I/Os
are configured as inputs and pulled low. WDT and FSCM are disabled.
Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The  current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
Data is characterized at +70°C and not tested. Parameter is for design guidance only.
This parameter is characterized, but not tested in manufacturing.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 175
PIC32MX5XX/6XX/7XX
TABLE 31-8:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Param.
Symbol
No.
VIL
DI10
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise
stated)
Operating temperature
-40°C  TA  +85°C for Industrial
Min.
Typical(1)
Max.
Units
with TTL Buffer
VSS
—
0.15 VDD
V
(Note 4)
with Schmitt Trigger Buffer
VSS
—
0.2 VDD
V
(Note 4)
Characteristics
Conditions
Input Low Voltage
I/O Pins:
(2)
DI15
MCLR
VSS
—
0.2 VDD
V
(Note 4)
DI16
OSC1 (XT mode)
VSS
—
0.2 VDD
V
(Note 4)
DI17
OSC1 (HS mode)
VSS
—
0.2 VDD
V
(Note 4)
DI18
SDAx, SCLx
VSS
—
0.3 VDD
V
SMBus disabled
(Note 4)
DI19
SDAx, SCLx
VSS
—
0.8
V
SMBus enabled
(Note 4)
0.8 VDD
—
VDD
V
(Note 4)
VIH
DI20
Input High Voltage
I/O Pins:
with Analog Functions
Digital Only
0.8 VDD
—
V
(Note 4)
0.25 VDD + 0.8V
—
5.5
V
(Note 4)
with Schmitt Trigger Buffer
0.8 VDD
—
5.5
V
(Note 4)
MCLR(2)
0.8 VDD
—
VDD
V
(Note 4)
DI26
OSC1 (XT mode)
0.7 VDD
—
VDD
V
(Note 4)
DI27
OSC1 (HS mode)
0.7 VDD
—
VDD
V
(Note 4)
DI28
SDAx, SCLx
0.7 VDD
—
5.5
V
SMBus disabled
(Note 4)
DI29
SDAx, SCLx
2.1
—
5.5
V
SMBus enabled,
2.3V  VPIN  5.5
(Note 4)
ICNPU
CNxx Pull up Current
50
250
400
A
VDD = 3.3V, VPIN = VSS
IIL
Input Leakage Current
(Note 3)
with TTL Buffer
DI25
DI30
DI50
I/O Ports
—
—
+1
A
VSS  VPIN  VDD,
Pin at high-impedance
DI51
Analog Input Pins
—
—
+1
A
VSS  VPIN  VDD,
Pin at high-impedance
DI55
MCLR(2)
—
—
+1
A
VSS VPIN VDD
DI56
OSC1
—
—
+1
A
VSS VPIN VDD,
XT and HS modes
Note 1:
2:
3:
4:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
This parameter is characterized, but not tested in manufacturing.
DS61156C-page 176
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-9:
DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Param.
Symbol
No.
VOL
Characteristics
I/O Ports
DO16
OSC2/CLKO
DO20
Typical
Max.
Units
Conditions
—
—
0.4
V
—
—
0.4
V
IOL = 6 mA, VDD = 2.3V
—
—
0.4
V
IOL = 3.5 mA, VDD = 3.6V
—
—
0.4
V
IOL = 2.5 mA, VDD = 2.3V
2.4
—
—
V
IOH = -12 mA, VDD = 3.6V
1.4
—
—
V
IOH = -12 mA, VDD = 2.3V
2.4
—
—
V
IOH = -12 mA, VDD = 3.6V
1.4
—
—
V
IOH = -12 mA, VDD = 2.3V
IOL = 7 mA, VDD = 3.6V
Output High Voltage
I/O Ports
DO26
Min.
Output Low Voltage
DO10
VOH
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise
stated)
Operating temperature
-40°C  TA  +85°C for Industrial
OSC2/CLKO
TABLE 31-10: DC CHARACTERISTICS: PROGRAM MEMORY(3)
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
Programming temperature 0°C  TA  +70°C (25°C recommended)
Min.
Typical(1)
Max.
Units
Conditions
Program Flash Memory
D130
EP
Cell Endurance
1000
—
—
D131
VPR
VDD for Read
VMIN
—
3.6
D132
VPEW
VDD for Erase or Write
3.0
—
3.6
D134
TRETD
Characteristic Retention
20
—
—
Year Provided no other specifications
are violated
D135
IDDP
Supply Current during
Programming
—
10
—
mA
TWW
Word Write Cycle Time
20
—
40
s
0°C to +40°C
D136
TRW
Row Write Cycle Time
(Note 2)
(128 words per row)
3
4.5
—
ms
0°C to +40°C
D137
TPE
Page Erase Cycle Time
20
—
—
ms
0°C to +40°C
TCE
Chip Erase Cycle Time
80
—
—
ms
0°C to +40°C
Note 1:
2:
3:
E/W -40°C to +85°C
V
VMIN = Minimum operating
voltage
V
0°C to +40°C
0°C to +40°C
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities
during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads
are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default
Arbitration mode is mode 1 (CPU has lowest priority).
Refer to the “PIC32MX Flash Programming Specification” (DS61145) for operating conditions during
programming and erase cycles.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 177
PIC32MX5XX/6XX/7XX
TABLE 31-11: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
Required Flash Wait States
SYSCLK
Units
0 Wait State
0 to 30
MHz
1 Wait State
31 to 60
2 Wait States
61 to 80
Comments
TABLE 31-12: COMPARATOR SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typical
Max.
Units
Comments
D300
VIOFF
Input Offset Voltage
—
±7.5
±25
mV
AVDD = VDD,
AVSS = VSS
D301
VICM
Input Common Mode Voltage
0
—
VDD
V
AVDD = VDD,
AVSS = VSS
(Note 2)
D302
CMRR
Common Mode Rejection Ratio
55
—
—
dB
Max VICM = (VDD – 1)V
(Note 2)
D303
TRESP
Response Time
—
150
400
ns
AVDD = VDD,
AVSS = VSS
(Notes 1, 2)
D304
ON2OV
Comparator Enabled to Output
Valid
—
—
10
s
Comparator module is
configured before setting
the comparator ON bit.
(Note 2)
Note 1:
2:
Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
These parameters are characterized but not tested.
DS61156C-page 178
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-13: VOLTAGE REFERENCE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
DC CHARACTERISTICS
Param.
No.
Symbol
Characteristics
D310
VRES
Resolution
D311
VRAA
Absolute Accuracy
Typical
Max.
Units
VDD/24
—
VDD/32
LSb
—
—
1/2
LSb
—
—
10
s
—
0.6
—
V
(1)
D312
TSET
Settling Time
D313
VIREF
Internal Voltage Reference
Note 1:
Min.
Comments
Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. This parameter is
characterized, but not tested in manufacturing.
TABLE 31-14: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
DC CHARACTERISTICS
Param.
No.
Symbol
Characteristics
Min.
Typical
Max.
Units
1.62
1.80
1.98
V
D320
VDDCORE Regulator Output Voltage
D321
CEFC
External Filter Capacitor Value
8
10
—
F
D322
TPWRT
Power-up Timer Period
—
64
—
ms
 2010 Microchip Technology Inc.
Preliminary
Comments
Capacitor must be low series
resistance (1 ohm)
DS61156C-page 179
PIC32MX5XX/6XX/7XX
31.2
AC Characteristics and Timing
Parameters
The information contained in this section defines
PIC32MX5XX/6XX/7XX AC characteristics and timing
parameters.
TABLE 31-15: AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
Operating voltage VDD range.
AC CHARACTERISTICS
FIGURE 31-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
RL
CL
Pin
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins
50 pF for OSC2 pin (EC mode)
VSS
TABLE 31-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
Param.
Symbol
No.
Min.
Typical(1)
Characteristics
Max.
Units
Conditions
DO56
CIO
All I/O pins and OSC2
—
—
50
pF
EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C™ mode
Note 1:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 31-2:
EXTERNAL CLOCK TIMING
OS20
OS30
OS31
OSC1
OS30
DS61156C-page 180
Preliminary
OS31
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Min.
Typical(1)
Max.
Units
Conditions
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
4
—
—
50 (Note 3)
50 (Note 5)
MHz
MHz
EC (Note 5)
ECPLL (Note 4)
Oscillator Crystal Frequency
3
—
10
MHz
XT (Note 5)
OS12
4
—
10
MHz
XTPLL
(Notes 4, 5)
OS13
10
—
25
MHz
HS (Note 5)
OS14
10
—
25
MHz
HSPLL
(Notes 4, 5)
OS15
32
32.768
100
kHz
SOSC (Note 5)
—
—
—
—
See parameter
OS10 for FOSC
value
OS10
FOSC
OS11
Characteristics
OS20
TOSC
TOSC = 1/FOSC = TCY (Note 2)
OS30
TOSL,
TOSH
External Clock In (OSC1)
High or Low Time
0.45 x TOSC
—
—
ns
EC (Note 5)
OS31
TOSR,
TOSF
External Clock In (OSC1)
Rise or Fall Time
—
—
0.05 x TOSC
ns
EC (Note 5)
OS40
TOST
Oscillator Start-up Timer Period
(Only applies to HS, HSPLL,
XT, XTPLL and SOSC Clock
Oscillator modes)
—
1024
—
TOSC
(Note 5)
OS41
TFSCM
Primary Clock Fail Safe
Time-out Period
—
2
—
ms
(Note 5)
OS42
GM
External Oscillator
Transconductance
—
12
—
Note 1:
2:
3:
4:
5:
mA/V VDD = 3.3V,
TA = +25°C
(Note 5)
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are not
tested.
Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device
executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min.” values with an
external clock applied to the OSC1/CLKI pin.
40 MHz maximum for PIC32MX 40 MHz family variants.
PLL input requirements: 4 MHZ  FPLLIN  5 MHZ (use PLL prescaler to reduce FOSC). This parameter is
characterized, but tested at 10 MHz only at manufacturing.
This parameter is characterized, but not tested in manufacturing.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 181
PIC32MX5XX/6XX/7XX
TABLE 31-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical(2)
Max.
Units
OS50
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
4
—
5
MHz
OS51
FSYS
On-Chip VCO System
Frequency
60
—
120
MHz
OS52
TLOCK
PLL Start-up Time (Lock Time)
OS53
DCLK
CLKO Stability
(Period Jitter or Cumulative)
Note 1:
2:
—
—
2
ms
-0.25
—
+0.25
%
Conditions
ECPLL, HSPLL, XTPLL,
FRCPLL modes
Measured over 100 ms
period
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 31-19:
INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Param.
No.
Characteristics
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C  TA +85°C for industrial
Min.
Typical
Max.
Units
+2
%
Conditions
Internal FRC Accuracy @ 8.00 MHz (Note 1)
F20
Note 1:
FRC
-2
—
Frequency calibrated at 25°C and 3.3V. The TUN bits can be used to compensate for temperature drift.
TABLE 31-20: INTERNAL RC ACCURACY
AC CHARACTERISTICS
Param.
No.
Characteristics
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
Min.
Typical
Max.
Units
-15
—
+15
%
Conditions
LPRC @ 31.25 kHz (Note 1)
F21
Note 1:
LPRC
Change of LPRC frequency as VDD changes.
DS61156C-page 182
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
DO31
DO32
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-21: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(2)
Min.
Typical(1)
Max.
Units
—
5
15
ns
VDD < 2.5V
Conditions
DO31
TIOR
Port Output Rise Time
—
5
10
ns
VDD > 2.5V
DO32
TIOF
Port Output Fall Time
—
5
15
ns
VDD < 2.5V
—
5
10
ns
VDD > 2.5V
DI35
TINP
INTx Pin High or Low Time
10
—
—
ns
DI40
TRBP
CNx High or Low Time (input)
2
—
—
TSYSCLK
Note 1:
2:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
This parameter is characterized, but not tested in manufacturing.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 183
PIC32MX5XX/6XX/7XX
FIGURE 31-4:
POWER-ON RESET TIMING CHARACTERISTICS
Internal Voltage Regulator Enabled
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
CPU Starts Fetching Code
SY00
(TPU)
(Note 1)
Internal Voltage Regulator Enabled
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
VDD
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
SY00
(TPU)
(Note 1)
SY10
(TOST)
CPU Starts Fetching Code
External VDDCORE Provided
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VDDCORE
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 3)
SY01
(TPWRT)
(Note 1)
Note 1:
CPU Starts Fetching Code
The power-up period will be extended if the power-up sequence completes before the device exits from BOR
(VDD < VDDMIN).
2:
Includes interval voltage regulator stabilization delay.
3:
Power-up Timer (PWRT); only active when the internal voltage regulator is disabled.
DS61156C-page 184
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-5:
EXTERNAL RESET TIMING CHARACTERISTICS
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
MCLR
TMCLR
(SY20)
BOR
TBOR
(SY30)
(TSYSDLY)
SY02
Reset Sequence
CPU Starts Fetching Code
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
(TSYSDLY)
SY02
Reset Sequence
CPU Starts Fetching Code
TOST
(SY10)
TABLE 31-22: RESETS TIMING
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
SY00
TPU
Power-up Period
Internal Voltage Regulator Enabled
—
400
600
s
-40°C to +85°C
SY01
TPWRT
Power-up Period
External VDDCORE Applied
(Power-up timer active)
48
64
80
ms
-40°C to +85°C
SY02
TSYSDLY System Delay Period:
Time Required to Reload Device
Configuration Fuses plus SYSCLK
Delay before First instruction is
Fetched.
—
s +
8 SYSCLK
cycles
—
—
-40°C to +85°C
SY20
TMCLR
MCLR Pulse Width (low)
—
2
—
s
-40°C to +85°C
SY30
TBOR
BOR Pulse Width (low)
—
1
—
s
-40°C to +85°C
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 185
PIC32MX5XX/6XX/7XX
FIGURE 31-6:
TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
OS60
Tx20
TMRx
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
TA10
TA11
TA15
Symbol
TTXH
TTXL
TTXP
Characteristics(2)
TxCK
High Time
TxCK
Low Time
Typical Max. Units
Conditions
Synchronous,
with prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
—
ns
Asynchronous,
with prescaler
10
—
—
ns
Synchronous,
with prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
—
ns
Asynchronous,
with prescaler
10
—
—
ns
[(Greater of 25 ns or
2 TPB)/N] + 30 ns
—
—
ns
VDD > 2.7V
[(Greater of 25 ns or
2 TPB)/N] + 50 ns
—
—
ns
VDD < 2.7V
20
—
—
ns
VDD > 2.7V
(Note 3)
50
—
—
ns
VDD < 2.7V
(Note 3)
32
—
100
kHz
1
TPB
TxCK
Synchronous,
Input Period with prescaler
Asynchronous,
with prescaler
OS60
FT1
TA20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
Note 1:
2:
3:
Min.
SOSC1/T1CK Oscillator
Input Frequency Range
(oscillator enabled by setting
TCS bit (T1CON<1>))
—
Must also meet
parameter TA15
Must also meet
parameter TA15
Timer1 is a Type A.
This parameter is characterized, but not tested in manufacturing.
N = Prescale Value (1, 8, 64, 256)
DS61156C-page 186
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Characteristics(1)
Symbol
Min.
Max. Units
Conditions
TB10
TTXH
TxCK
Synchronous, with
High Time prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns
TB11
TTXL
TxCK
Low Time
Synchronous, with
prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns
TB15
TTXP
TxCK Input Synchronous, with
Period
prescaler
[(Greater of [(25 ns or
2 TPB)/N] + 30 ns
—
ns
VDD > 2.7V
[(Greater of [(25 ns or
2 TPB)/N] + 50 ns
—
ns
VDD < 2.7V
—
1
TPB
TB20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
Note 1:
Must also meet N = prescale
parameter TB15 value
Must also meet (1, 2, 4, 8, 16,
parameter TB15 32, 64, 256)
These parameters are characterized, but not tested in manufacturing.
FIGURE 31-7:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param.
Symbol
No.
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
Characteristics(1)
Min.
Max.
Units
Conditions
IC10
TCCL
ICx Input Low Time
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns
Must also
meet
parameter
IC15.
IC11
TCCH
ICx Input High Time
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns
Must also
meet
parameter
IC15.
IC15
TCCP
ICx Input Period
[(25 ns or 2 TPB)/N]
+ 50 ns
—
ns
Note 1:
These parameters are characterized, but not tested in manufacturing.
 2010 Microchip Technology Inc.
Preliminary
N = prescale
value (1, 4, 16)
DS61156C-page 187
PIC32MX5XX/6XX/7XX
FIGURE 31-8:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM mode)
OC10
OC11
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
OC10
TCCF
OCx Output Fall Time
—
—
—
ns
See parameter DO32
OC11
TCCR
OCx Output Rise Time
—
—
—
ns
See parameter DO31
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 31-9:
OCx/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCx
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Symbol
Characteristics(1)
Min
Typical(2)
Max
Units
Conditions
OC15
TFD
Fault Input to PWM I/O Change
—
—
50
ns
OC20
TFLT
Fault Input Pulse Width
50
—
—
ns
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
DS61156C-page 188
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-10:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDOx
SP31
SDIx
LSb
SP30
MSb In
LSb In
Bit 14 - - - -1
SP40 SP41
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2) Max.
Units
Conditions
SP10
TSCL
SCKx Output Low Time
(Note 3)
TSCK/2
—
—
ns
SP11
TSCH
SCKx Output High Time
(Note 3)
TSCK/2
—
—
ns
SP20
TSCF
SCKx Output Fall Time
(Note 4)
—
—
—
ns
See parameter DO32
SP21
TSCR
SCKx Output Rise Time
(Note 4)
—
—
—
ns
See parameter DO31
SP30
TDOF
SDOx Data Output Fall Time
(Note 4)
—
—
—
ns
See parameter DO32
SP31
TDOR
SDOx Data Output Rise Time
(Note 4)
—
—
—
ns
See parameter DO31
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
15
ns
VDD > 2.7V
—
—
20
ns
VDD < 2.7V
SP40
TDIV2SCH,
TDIV2SCL
Setup Time of SDIx Data Input
to SCKx Edge
10
—
—
ns
SP41
TSCH2DIL,
TSCL2DIL
Hold Time of SDIx Data Input
to SCKx Edge
10
—
—
ns
Note 1:
2:
3:
4:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 189
PIC32MX5XX/6XX/7XX
FIGURE 31-11:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11
SCKX
(CKP = 1)
SP10
SP21
SP20
SP20
SP21
SP35
MSb
SDOX
LSb
Bit 14 - - - - - -1
SP30,SP31
SDIX
MSb In
SP40
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°Cfor Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typ.(2)
Max.
Units
—
—
ns
Conditions
SP10
TSCL
SCKx Output Low Time (Note 3)
TSCK/2
SP11
TSCH
SCKx Output High Time (Note 3)
TSCK/2
—
—
ns
SP20
TSCF
SCKx Output Fall Time (Note 4)
—
—
—
ns
See parameter DO32
SP21
TSCR
SCKx Output Rise Time (Note 4)
—
—
—
ns
See parameter DO31
SP30
TDOF
SDOx Data Output Fall Time
(Note 4)
—
—
—
ns
See parameter DO32
SP31
TDOR
SDOx Data Output Rise Time
(Note 4)
—
—
—
ns
See parameter DO31
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
15
ns
VDD > 2.7V
—
—
20
ns
VDD < 2.7V
SP36
TDOV2SC, SDOx Data Output Setup to
TDOV2SCL First SCKx Edge
15
—
—
ns
SP40
TDIV2SCH, Setup Time of SDIx Data Input to
TDIV2SCL SCKx Edge
15
—
—
ns
VDD > 2.7V
20
—
—
ns
VDD < 2.7V
TSCH2DIL,
TSCL2DIL
SP41
Note 1:
2:
3:
4:
Hold Time of SDIx Data Input
to SCKx Edge
15
—
—
ns
VDD > 2.7V
20
—
—
ns
VDD < 2.7V
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
DS61156C-page 190
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-12:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
LSb
Bit 14 - - - - - -1
SP51
SP30,SP31
SDIX
Bit 14 - - - -1
MSb In
SP40
LSb In
SP41
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typ.(2)
Max.
Units
SP70
SP71
SP72
SP73
SP30
SP31
SP35
TSCL
TSCH
TSCF
TSCR
TDOF
TDOR
TSCH2DOV,
TSCL2DOV
SCKx Input Low Time (Note 3)
SCKx Input High Time (Note 3)
SCKx Input Fall Time
SCKx Input Rise Time
SDOx Data Output Fall Time (Note 4)
SDOx Data Output Rise Time (Note 4)
SDOx Data Output Valid after
SCKx Edge
SP40
TDIV2SCH,
TDIV2SCL
TSCH2DIL,
TSCL2DIL
Setup Time of SDIx Data Input
to SCKx Edge
Hold Time of SDIx Data Input
to SCKx Edge
TSCK/2
TSCK/2
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
20
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
—
—
ns
175
—
—
ns
5
—
25
ns
SP41
Conditions
See parameter DO32
See parameter DO31
See parameter DO32
See parameter DO31
VDD > 2.7V
VDD < 2.7V
SP50
TSSL2SCH, SSx  to SCKx  or SCKx Input
TSSL2SCL
SP51
TSSH2DOZ SSx  to SDOx Output
High-Impedance (Note 3)
SP52
TSCH2SSH SSx after SCKx Edge
TSCK + 20
—
—
ns
TSCL2SSH
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 40 ns.
Assumes 50 pF load on all SPIx pins.
Note 1:
2:
3:
4:
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 191
PIC32MX5XX/6XX/7XX
FIGURE 31-13:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30,SP31
SDIx
SDI
MSb In
SP40
SP51
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
SP70
TSCL
SCKx Input Low Time (Note 3)
TSCK/2
—
—
ns
SP71
TSCH
SCKx Input High Time (Note 3)
TSCK/2
—
—
ns
SP72
TSCF
SCKx Input Fall Time
—
5
10
ns
SP73
TSCR
SCKx Input Rise Time
—
5
10
ns
SP30
TDOF
SDOx Data Output Fall Time
(Note 4)
—
—
—
ns
See parameter DO32
SP31
TDOR
SDOx Data Output Rise Time
(Note 4)
—
—
—
ns
See parameter DO31
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
SP40
TDIV2SCH, Setup Time of SDIx Data Input
TDIV2SCL to SCKx Edge
SP41
TSCH2DIL,
TSCL2DIL
SP50
TSSL2SCH, SSx  to SCKx  or SCKx  Input
TSSL2SCL
Note 1:
2:
3:
4:
Hold Time of SDIx Data Input
to SCKx Edge
—
—
20
ns
VDD > 2.7V
—
—
30
ns
VDD < 2.7V
10
—
—
ns
10
—
—
ns
175
—
—
ns
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 40 ns.
Assumes 50 pF load on all SPIx pins.
DS61156C-page 192
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2)
Max.
Units
SP51
TSSH2DOZ SSx  to SDOX Output
High-Impedance
(Note 4)
5
—
25
ns
SP52
TSCH2SSH SSx  after SCKx Edge
TSCL2SSH
TSCK +
20
—
—
ns
SP60
TSSL2DOV SDOx Data Output Valid after
SSx Edge
—
—
25
ns
Note 1:
2:
3:
4:
Conditions
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 40 ns.
Assumes 50 pF load on all SPIx pins.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 193
PIC32MX5XX/6XX/7XX
FIGURE 31-14:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 31-1 for load conditions.
FIGURE 31-15:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM25
IM33
SDAx
In
IM40
IM40
IM45
SDAx
Out
Note: Refer to Figure 31-1 for load conditions.
DS61156C-page 194
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
IM10
IM11
IM20
Min.(1)
Max.
Units
TLO:SCL Clock Low Time 100 kHz mode
TPB * (BRG + 2)
—
s
400 kHz mode
TPB * (BRG + 2)
—
s
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
s
Clock High Time 100 kHz mode
TPB * (BRG + 2)
—
s
400 kHz mode
TPB * (BRG + 2)
—
s
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
s
—
300
ns
300
ns
—
100
ns
—
1000
ns
20 + 0.1 CB
300
ns
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode
(Note 2)
100
—
ns
THI:SCL
TF:SCL
Characteristics
SDAx and SCLx 100 kHz mode
Fall Time
400 kHz mode
1 MHz mode
(Note 2)
IM21
TR:SCL
SDAx and SCLx 100 kHz mode
Rise Time
400 kHz mode
1 MHz mode
(Note 2)
IM25
IM26
IM30
IM31
IM33
IM34
TSU:DAT Data Input
Setup Time
THD:DAT Data Input
Hold Time
TSU:STA
Start Condition
Setup Time
THD:STA Start Condition
Hold Time
TSU:STO Stop Condition
Setup Time
THD:STO Stop Condition
Hold Time
Note 1:
2:
20 + 0.1
CB
100 kHz mode
0
—
s
400 kHz mode
0
0.9
s
1 MHz mode
(Note 2)
0
0.3
s
100 kHz mode
TPB * (BRG + 2)
—
s
400 kHz mode
TPB * (BRG + 2)
—
s
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
s
100 kHz mode
TPB * (BRG + 2)
—
s
400 kHz mode
TPB * (BRG + 2)
—
s
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
s
100 kHz mode
TPB * (BRG + 2)
—
s
400 kHz mode
TPB * (BRG + 2)
—
s
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
s
100 kHz mode
TPB * (BRG + 2)
—
ns
400 kHz mode
TPB * (BRG + 2)
—
ns
1 MHz mode
(Note 2)
TPB * (BRG + 2)
—
ns
Conditions
CB is specified to be
from 10 to 400 pF
CB is specified to be
from 10 to 400 pF
Only relevant for
Repeated Start
condition
After this period, the
first clock pulse is
generated
BRG is the value of the I2C™ Baud Rate Generator.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 195
PIC32MX5XX/6XX/7XX
TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
IM40
IM45
IM50
Note 1:
2:
TAA:SCL
Output Valid
From Clock
TBF:SDA Bus Free Time
CB
Min.(1)
Max.
Units
100 kHz mode
—
3500
ns
400 kHz mode
—
1000
ns
1 MHz mode
(Note 2)
—
350
ns
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode
(Note 2)
0.5
—
s
—
400
pF
Characteristics
Bus Capacitive Loading
Conditions
The amount of time the
bus must be free
before a new
transmission can start
BRG is the value of the I2C™ Baud Rate Generator.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS61156C-page 196
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-16:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 31-1 for load conditions.
FIGURE 31-17:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS25
IS33
SDAx
In
IS40
IS40
IS45
SDAx
Out
Note: Refer to Figure 31-1 for load conditions.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 197
PIC32MX5XX/6XX/7XX
TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
IS10
IS11
IS20
IS21
Symbol
TLO:SCL
THI:SCL
TF:SCL
TR:SCL
Characteristics
Clock Low Time
Clock High Time
SDAx and SCLx
Fall Time
SDAx and SCLx
Rise Time
Min.
Max.
Units
100 kHz mode
4.7
—
s
PBCLK must operate at a
minimum of 800 kHz
400 kHz mode
1.3
—
s
PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode
(Note 1)
0.5
—
s
100 kHz mode
4.0
—
s
PBCLK must operate at a
minimum of 800 kHz
400 kHz mode
0.6
—
s
PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode
(Note 1)
0.5
—
s
100 kHz mode
—
400 kHz mode
IS26
IS30
IS31
IS33
Note 1:
TSU:DAT
THD:DAT
TSU:STA
THD:STA
TSU:STO
Data Input
Setup Time
Data Input
Hold Time
Start Condition
Setup Time
Start Condition
Hold Time
Stop Condition
Setup Time
300
ns
300
ns
1 MHz mode
(Note 1)
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode
(Note 1)
100
—
ns
1 MHz mode
(Note 1)
IS25
20 + 0.1
CB
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
1 MHz mode
(Note 1)
0
0.3
s
100 kHz mode
4700
—
s
400 kHz mode
600
—
s
1 MHz mode
(Note 1)
250
—
s
100 kHz mode
4000
—
s
400 kHz mode
600
—
s
1 MHz mode
(Note 1)
250
—
s
100 kHz mode
4000
—
s
400 kHz mode
600
—
s
1 MHz mode
(Note 1)
600
—
s
Conditions
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS61156C-page 198
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
IS34
IS40
Symbol
THD:STO
TAA:SCL
Characteristics
Stop Condition
Hold Time
Min.
Max.
Units
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode
(Note 1)
250
Output Valid From 100 kHz mode
Clock
400 kHz mode
1 MHz mode
(Note 1)
IS45
IS50
Note 1:
TBF:SDA
CB
Bus Free Time
ns
0
3500
ns
0
1000
ns
0
350
ns
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode
(Note 1)
0.5
—
s
—
400
pF
Bus Capacitive Loading
Conditions
The amount of time the bus
must be free before a new
transmission can start
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 199
PIC32MX5XX/6XX/7XX
FIGURE 31-18:
CiTx Pin
(output)
CAN MODULE I/O TIMING CHARACTERISTICS
New Value
Old Value
CA10 CA11
CiRx Pin
(input)
CA20
TABLE 31-34: CAN MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
CA10
TioF
Port Output Fall Time
—
—
—
ns
See parameter D032
CA11
TioR
Port Output Rise Time
—
—
—
ns
See parameter D031
CA20
Tcwf
Pulse Width to Trigger
CAN Wake-up Filter
500
—
—
ns
Note 1:
2:
—
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
DS61156C-page 200
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-35: ETHERNET MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param.
No.
Characteristic
Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for Industrial
Min.
Typical
Max.
Units
Conditions
Device Supply
ET20a
Module VDD Supply
2.5
—
3.6
V
ET20b
Module VDD Supply
2.7
—
3.6
V
MDC Duty Cycle
40
—
60
%
ET2
MDC Period
400
—
—
ns
ET3
MDIO Output Delay
10
—
10
ns
ET4
MDIO Input Delay
0
—
300
ns
For RMII mode only
MIIM Timing Requirements
ET1
MII Timing Requirements
ET5
TX Clock Frequency
—
25
—
MHz
ET6
TX Clock Duty Cycle
35
—
65
%
ET7
ETXDx, ETEN, ETXERR
Delay
0
—
25
ns
ET8
RX Clock Frequency
—
25
—
MHz
ET9
RX Clock Duty Cycle
35
—
65
%
ET10
ERXDx, ERXDV, ERXERR
Delay
10
—
30
ns
RMII Timing Requirements
ET11
Reference Clock Frequency
—
50
—
MHz
ET12
Reference Clock Duty Cycle
35
—
65
%
ET13
ETXDx, ETEN, Delay
2
—
16
ns
ET14
ERXDx, ERXDV, ERXERR
Delay
2
—
16
ns
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 201
PIC32MX5XX/6XX/7XX
TABLE 31-36: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics
Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
Min.
Typical
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of
VDD – 0.3
or 2.5
—
Lesser of
VDD + 0.3
or 3.6
V
AD02
AVSS
Module VSS Supply
VSS
—
VSS + 0.3
V
AVDD
V
(Note 1)
Reference Inputs
AD05
VREFH
Reference Voltage High
AVSS + 2.0
—
2.5
—
3.6
V
VREFH = AVDD (Note 3)
AD06
VREFL
Reference Voltage Low
AVSS
—
VREFH – 2.0
V
(Note 1)
AD07
VREF
Absolute Reference
Voltage (VREFH – VREFL)
2.0
—
AVDD
V
(Note 3)
AD08
IREF
Current Drain
—
250
—
400
3
A
A
ADC operating
ADC off
AD05a
Analog Input
AD12
AD17
VREFL
—
VREFH
V
VINL
VINH-VINL Full-Scale Input Span
Absolute VINL Input
Voltage
AVSS – 0.3
—
AVDD/2
V
VIN
Absolute Input Voltage
AVSS – 0.3
—
AVDD + 0.3
V
Leakage Current
—
+/- 0.001
+/-0.610
A
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
Source Impedance = 10 k
Recommended
Impedance of Analog
Voltage Source
—
—
5K

(Note 1)
RIN
ADC Accuracy – Measurements with External VREF+/VREF-
AD20c Nr
Resolution
AD21c INL
Integral Nonlinearity
> -1
—
<1
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD22c DNL
Differential Nonlinearity
> -1
—
<1
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
(Note 2)
AD23c GERR
Gain Error
> -1
—
<1
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD24n EOFF
Offset Error
> -1
—
<1
LSb VINL = AVSS = 0V,
AVDD = 3.3V
AD25c
Monotonicity
—
—
—
Note 1:
2:
3:
4:
—
10 data bits
bits
—
Guaranteed
These parameters are not characterized or tested in manufacturing.
With no missing codes.
These parameters are characterized, but not tested in manufacturing.
Characterized with a 1 kHz sinewave.
DS61156C-page 202
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-36: ADC MODULE SPECIFICATIONS (CONTINUED)
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics
Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
Min.
Typical
Max.
Units
Conditions
ADC Accuracy – Measurements with Internal VREF+/VREF-
AD20d Nr
Resolution
AD21d INL
Integral Nonlinearity
> -1
—
<1
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD22d DNL
Differential Nonlinearity
> -1
—
<1
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Notes 2, 3)
AD23d GERR
Gain Error
> -4
—
<4
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD24d EOFF
Offset Error
> -2
—
<2
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD25d
Monotonicity
—
—
—
—
Guaranteed
—
10 data bits
bits
(Note 3)
Dynamic Performance
AD31b SINAD
Signal to Noise and
Distortion
55
58.5
—
dB
(Notes 3, 4)
AD34b ENOB
Effective Number of Bits
9.0
9.5
—
bits
(Notes 3, 4)
Note 1:
2:
3:
4:
These parameters are not characterized or tested in manufacturing.
With no missing codes.
These parameters are characterized, but not tested in manufacturing.
Characterized with a 1 kHz sinewave.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 203
PIC32MX5XX/6XX/7XX
TABLE 31-37: 10-BIT CONVERSION RATE PARAMETERS
PIC32MX 10-Bit A/D Converter Conversion Rates(2)
ADC Speed
1 Msps to
400 ksps(1)
Sampling
TAD
RS Max
Minimum Time Min
65 ns
132 ns
500
VDD
Temperature
3.0V to
3.6V
-40°C to
+85°C
ADC Channels Configuration
VREF- VREF+
CHX
ANx
Up to 400 ksps
200 ns
200 ns
5.0 k
2.5V to
3.6V
SHA
ADC
-40°C to
+85°C
VREF- VREF+
or
or
AVSS AVDD
CHX
ANx
SHA
ADC
ANx or VREF-
Up to 300 ksps
200 ns
200 ns
5.0 k
2.5V to
3.6V
-40°C to
+85°C
VREF- VREF+
or
or
AVSS AVDD
CHX
ANx
SHA
ADC
ANx or VREF-
Note 1:
2:
External VREF- and VREF+ pins must be used for correct operation.
These parameters are characterized, but not tested in manufacturing.
DS61156C-page 204
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-38: A/D CONVERSION TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Min.
Typical(1)
Max.
Units
A/D Clock Period(2)
65
—
—
ns
Characteristics
Conditions
Clock Parameters
AD50
TAD
See Table 31-37
Conversion Rate
AD55
TCONV
Conversion Time
—
12 TAD
—
—
AD56
FCNV
Throughput Rate
(Sampling Speed)
—
—
1000
ksps
AVDD = 3.0V to 3.6V
—
—
400
ksps
AVDD = 2.5V to 3.6V
Sample Time
1
—
31
TAD
TSAMP must be  132 ns
—
1.0 TAD
—
—
0.5 TAD
—
1.5 TAD
—
AD57
TSAMP
Timing Parameters
AD60
TPCS
Conversion Start from Sample
Trigger(3)
AD61
TPSS
Sample Start from Setting
Sample (SAMP) bit
AD62
TCSS
Conversion Completion to
Sample Start (ASAM = 1)(3)
—
0.5 TAD
—
—
AD63
TDPU
Time to Stabilize Analog Stage
from A/D Off to A/D On(3)
—
—
2
s
Note 1:
2:
3:
Auto-Convert Trigger
(SSRC<2:0> = 111)
not selected
These parameters are characterized, but not tested in manufacturing.
Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
Characterized by design but not tested.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 205
PIC32MX5XX/6XX/7XX
FIGURE 31-19:
A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)
AD50
ADCLK
Instruction
Execution Set SAMP
Clear SAMP
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
AD61
AD60
AD55
TSAMP
AD55
CONV
ADxIF
Buffer(0)
Buffer(1)
1
2
3
4
5
6
7
8
5
6
7
8
1 – Software sets ADxCON. SAMP to start sampling.
2 – Sampling starts after discharge period. TSAMP is described in the “PIC32MX Family Reference Manual” (DS61132).
3 – Software clears ADxCON. SAMP to start conversion.
4 – Sampling ends, conversion sequence starts.
5 – Convert bit 9.
6 – Convert bit 8.
7 – Convert bit 0.
8 – One TAD for end of conversion.
DS61156C-page 206
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-20:
A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)
AD50
ADCLK
Instruction
Execution
Set ADON
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
TSAMP
AD55
TSAMP
AD55
TCONV
CONV
ADxIF
Buffer(0)
Buffer(1)
1
2
3
4
5
6
7
3
4
5
6
8
3
4
1 – Software sets ADxCON. ADON to start AD operation.
5 – Convert bit 0.
2 – Sampling starts after discharge period.
TSAMP is described in the “PIC32MX
Family Reference Manual” (DS61132).
6 – One TAD for end of conversion.
3 – Convert bit 9.
8 – Sample for time specified by SAMC<4:0>.
7 – Begin conversion of next channel.
4 – Convert bit 8.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 207
PIC32MX5XX/6XX/7XX
FIGURE 31-21:
PARALLEL SLAVE PORT TIMING
CS
PS5
RD
PS6
WR
PS4
PS7
PMD<7:0>
PS1
PS3
PS2
TABLE 31-39: PARALLEL SLAVE PORT REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical
Max.
Units
20
—
—
ns
PS1
TdtV2wrH Data In Valid before WR or CS Inactive
(setup time)
PS2
TwrH2dtI
WR or CS Inactive to Data–In Invalid
(hold time)
40
—
—
ns
PS3
TrdL2dtV
RD and CS Active to Data–Out Valid
—
—
60
ns
PS4
TrdH2dtI
RD Activeor CS Inactive to Data–Out
Invalid
0
—
10
ns
PS5
Tcs
CS Active Time
TPB + 40
—
—
ns
PS6
TWR
WR Active Time
TPB + 25
—
—
ns
PS7
TRD
RD Active Time
TPB + 25
—
—
ns
Note 1:
Conditions
These parameters are characterized, but not tested in manufacturing.
DS61156C-page 208
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-22:
PARALLEL MASTER PORT READ TIMING DIAGRAM
TPB
TPB
TPB
TPB
TPB
TPB
TPB
TPB
PB Clock
PM4
Address
PMA<13:18>
PM6
PMD<7:0>
Data
Data
Address<7:0>
Address<7:0>
PM2
PM7
PM3
PMRD
PM5
PMWR
PM1
PMALL/PMALH
PMCS<2:1>
TABLE 31-40: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical
Max.
Units
PM1
TLAT
PMALL/PMALH Pulse Width
—
1 TPB
—
—
PM2
TADSU
Address Out Valid to PMALL/PMALH
Invalid (address setup time)
—
2 TPB
—
—
PM3
TADHOLD PMALL/PMALH Invalid to Address Out
Invalid (address hold time)
—
1 TPB
—
—
PM4
TAHOLD
PMRD Inactive to Address Out Invalid
(address hold time)
5
—
—
ns
PM5
TRD
PMRD Pulse Width
—
1 TPB
—
—
PM6
TDSU
PMRD or PMENB Active to Data In
Valid (data setup time)
15
—
—
ns
PM7
TDHOLD
PMRD or PMENB Inactive to Data In
Invalid (data hold time)
—
80
—
ns
Note 1:
Conditions
These parameters are characterized, but not tested in manufacturing.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 209
PIC32MX5XX/6XX/7XX
FIGURE 31-23:
PARALLEL MASTER PORT WRITE TIMING DIAGRAM
TPB
TPB
TPB
TPB
TPB
TPB
TPB
TPB
PB Clock
Address
PMA<13:18>
PM2 + PM3
Address<7:0>
PMD<7:0>
Data
PM12
PM13
PMRD
PM11
PMWR
PM1
PMALL/PMALH
PMCS<2:1>
TABLE 31-41: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical
Max.
Units
PM11
TWR
PMWR Pulse Width
—
1 TPB
—
—
PM12
TDVSU
Data Out Valid before PMWR or
PMENB goes Inactive (data setup time)
—
2 TPB
—
—
PM13
TDVHOLD PMWR or PMEMB Invalid to Data Out
Invalid (data hold time)
—
1 TPB
—
—
Note 1:
Conditions
These parameters are characterized, but not tested in manufacturing.
DS61156C-page 210
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-42: OTG ELECTRICAL SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical
Max.
Units
USB313 VUSB
USB Voltage
3.0
—
3.6
V
USB315 VILUSB
Input Low Voltage for USB Buffer
—
—
0.8
V
USB316 VIHUSB
Input High Voltage for USB Buffer
2.0
—
—
V
USB318 VDIFS
Differential Input Sensitivity
—
—
0.2
V
USB319 VCM
Differential Common Mode Range
0.8
—
2.5
V
Conditions
Voltage on bus must
be in this range for
proper USB operation
The difference
between D+ and Dmust exceed this value
while VCM is met
USB320 ZOUT
Driver Output Impedance
28.0
—
44.0

USB321 VOL
Voltage Output Low
0.0
—
0.3
V
14.25 k load
connected to 3.6V
USB322 VOH
Voltage Output High
2.8
—
3.6
V
14.25 k load
connected to ground
Note 1:
These parameters are characterized, but not tested in manufacturing.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 211
PIC32MX5XX/6XX/7XX
FIGURE 31-24:
EJTAG TIMING CHARACTERISTICS
TTCKeye
TTCKhigh
TTCKlow
Trf
TCK
Trf
TMS
TDI
TTsetup TThold
Trf
Trf
TDO
TRST*
TTRST*low
TTDOout
TTDOzstate
Defined
Trf
Undefined
TABLE 31-43: EJTAG TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
Symbol
Description(1)
Min.
Max.
Units
EJ1
TTCKCYC
TCK Cycle Time
25
—
ns
EJ2
TTCKHIGH
TCK High Time
10
—
ns
EJ3
TTCKLOW
TCK Low Time
10
—
ns
EJ4
TTSETUP
TAP Signals Setup Time Before
Rising TCK
5
—
ns
EJ5
TTHOLD
TAP Signals Hold Time After
Rising TCK
3
—
ns
EJ6
TTDOOUT
TDO Output Delay Time From
Falling TCK
—
5
ns
EJ7
TTDOZSTATE TDO 3-State Delay Time From
Falling TCK
—
5
ns
EJ8
TTRSTLOW
TRST Low Time
25
—
ns
EJ9
TRF
TAP Signals Rise/Fall Time, All
Input and Output
—
—
ns
Note 1:
Conditions
These parameters are characterized, but not tested in manufacturing.
DS61156C-page 212
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
32.0
PACKAGING INFORMATION
32.1
Package Marking Information
Example
64-Lead TQFP (10x10x1 mm)
PIC32MX575F
512H-80I/PT
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
e3
0510017
100-Lead TQFP (14x14x1 mm)
Example
PIC32MX575F
512L-80I/PF e3
0510017
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
100-Lead TQFP (12x12x1 mm)
Example
PIC32MX575F
512L-80I/PT e3
0510017
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e) 3
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 213
PIC32MX5XX/6XX/7XX
32.1
Package Marking Information (Continued)
64-Lead QFN (9x9x0.9 mm)
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC32MX575F
512H-80I/MR
e3
0510017
121-Lead XBGA (10x10x1.1 mm)
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
DS61156C-page 214
Example
PIC32MX575F
512H-80I/BG
e3
0510017
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
32.2
Package Details
The following sections give the technical details of the packages.
!"#$%
&
' (
3&'!&"&
4#*!(
!!&
4
%&&#&
&&
255***'
'5
4
D
D1
E
e
E1
N
b
NOTE 1
123
NOTE 2
α
A
φ
c
A2
β
A1
L
L1
6&!
'!7'&!
8"')%7#!
'
77..
8
8
89
:
;
7#&
9 <&
=
/1+
=
##44!!
/
/
&#%%
/
=
/
3&7&
7
/
;
/
3&
&
7
.3
3&
9 ?#&
.
>
1+
/>
9 7&
1+
##4?#&
.
1+
##47&
1+
>
7#4!!
=
7#?#&
)
#%&
>
>
>
#%&1&&'
>
>
>
(
!"#$%&"' ()"&'"!&)&#*&&&#
+'%!&!
&,!-' '!!#.#&"#'#%!
&"!!#%!
&"!!!&$#/''
!#
'!#&
.0/
1+2 1!'!&$& "!**&"&&!
.32 %'!("!"*&"&&(%%'&
"
!!
* +@/1
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 215
PIC32MX5XX/6XX/7XX
!"#$%
&
' (
3&'!&"&
4#*!(
!!&
4
%&&#&
&&
255***'
'5
4
DS61156C-page 216
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
!"#$%
&
' (
3&'!&"&
4#*!(
!!&
4
%&&#&
&&
255***'
'5
4
D
D1
e
E1
E
b
N
α
NOTE 1
1 23
A
NOTE 2
φ
c
β
A2
A1
L
L1
6&!
'!7'&!
8"')%7#!
'
77..
8
8
89
:
7#&
9 <&
=
/1+
=
##44!!
/
/
&#%%
/
=
/
3&7&
7
/
;
/
3&
&
7
.3
3&
9 ?#&
.
>
;1+
/>
9 7&
;1+
##4?#&
.
1+
##47&
1+
>
7#4!!
=
7#?#&
)
#%&
>
>
>
#%&1&&'
>
>
>
(
!"#$%&"' ()"&'"!&)&#*&&&#
+'%!&!
&,!-' '!!#.#&"#'#%!
&"!!#%!
&"!!!&$#/''
!#
'!#&
.0/
1+2 1!'!&$& "!**&"&&!
.32 %'!("!"*&"&&(%%'&
"
!!
* +1
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 217
PIC32MX5XX/6XX/7XX
!"#$%
&
' (
3&'!&"&
4#*!(
!!&
4
%&&#&
&&
255***'
'5
4
DS61156C-page 218
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
## !"#$%
&
' (
3&'!&"&
4#*!(
!!&
4
%&&#&
&&
255***'
'5
4
D
D1
e
E
E1
N
b
NOTE 1
1 23
NOTE 2
α
c
A
φ
L
β
A1
6&!
'!7'&!
8"')%7#!
'
A2
L1
77..
8
8
89
:
7#&
9 <&
=
1+
=
##44!!
/
/
&#%%
/
=
/
3&7&
7
/
;
/
3&
&
7
.3
3&
I
9 ?#&
.
>
1+
/>
9 7&
1+
##4?#&
.
1+
##47&
1+
>
7#4!!
=
7#?#&
)
@
#%&
D
>
>
>
#%&1&&'
E
>
>
>
(
!"#$%&"' ()"&'"!&)&#*&&&#
+'%!&!
&,!-' '!!#.#&"#'#%!
&"!!#%!
&"!!!&$#/''
!#
'!#&
.0/
1+2 1!'!&$& "!**&"&&!
.32 %'!("!"*&"&&(%%'&
"
!!
* +1
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 219
PIC32MX5XX/6XX/7XX
## !"#$%
&
' (
3&'!&"&
4#*!(
!!&
4
%&&#&
&&
255***'
'5
4
DS61156C-page 220
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 221
PIC32MX5XX/6XX/7XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS61156C-page 222
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 223
PIC32MX5XX/6XX/7XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS61156C-page 224
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 225
PIC32MX5XX/6XX/7XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS61156C-page 226
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
APPENDIX A:
MIGRATING FROM
PIC32MX3XX/4XX TO
PIC32MX5XX/6XX/7XX
DEVICES
This appendix provides an overview of considerations
for migrating from PIC32MX3XX/4XX devices to the
PIC32MX5XX/6XX/7XX family of devices. The code
developed for the PIC32MX3XX/4XX devices can be
ported to the PIC32MX5XX/6XX/7XX devices after
making the appropriate changes outlined below.
A.1
DMA
PIC32MX5XX/6XX/7XX devices do
stopping DMA transfers in Idle mode.
A.2
not
A.3
Pin Assignments
PIC32MX5XX/6XX/7XX devices have the same pin
assignment for peripherals as PIC32MX4XX devices
with the following exceptions:
• Pins associated with the UART1 and UART2
modules on PIC32MX4XX devices are now
associated with the UART1A and UART3A
modules, respectively on PIC32MX5XX/6XX/7XX
devices
• Pins associated with the SPI2 module on
PIC32MX4XX devices are now associated with
the SPI2A module on PIC32MX5XX/6XX/7XX
devices
support
Interrupts
PIC32MX5XX/6XX/7XX devices have persistent interrupts for some of the peripheral modules. This means
that the interrupt condition for these peripherals must
be cleared before the interrupt flag can be cleared.
For example, to clear a UART receive interrupt, the
user application must first read the UART Receive register to clear the interrupt condition and then clear the
associated UxIF flag to clear the pending UART interrupt. In other words, the UxIF flag cannot be cleared by
software until the UART Receive register is read.
Table A-1 outlines the peripherals and associated
interrupts that are implemented differently on
PIC32MX5XX/6XX/7XX versus PIC32MX3XX/4XX
devices.
In addition, on the SPI module, the IRQ numbers for the
receive done interrupts were changed from 25 to 24
and the transfer done interrupts were changed from 24
to 25.
TABLE A-1:
PIC32MX3XX/4XX vs. PIC32MX5XX/6XX/7XX INTERRUPT IMPLEMENTATION
DIFFERENCES
Module
Interrupt Implementation
Input Capture
To clear an interrupt source, read the Buffer Result (ICxBUF) register to obtain the number of
capture results in the buffer that are below the interrupt threshold (specified by ICI<1:0> bits).
SPI
Receive and transmit interrupts are controlled by the SRXISEL<1:0> and STXISEL<1:0> bits,
respectively. To clear an interrupt source, data must be written to, or read from, the SPIxBUF
register to obtain the number of data to receive/transmit below the level specified by the
SRXISEL<1:0> and STXISEL<1:0> bits.
UART
TX interrupt will be generated as soon as the UART module is enabled.
Receive and transmit interrupts are controlled by the URXISEL<1:0> and UTXISEL<1:0> bits,
respectively. To clear an interrupt source, data must be read from, or written to, the UxRXREG or
UxTXREG registers to obtain the number of data to receive/transmit below the level specified by
the URXISEL<1:0> and UTXISEL<1:0> bits.
ADC
All samples must be read from the result registers (ADC1BUFx) to clear the interrupt source.
PMP
To clear an interrupt source, read the Parallel Master Port Data Input/Output (PMDIN/PMDOUT)
register.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 227
PIC32MX5XX/6XX/7XX
APPENDIX B: REVISION HISTORY
Revision B (November 2009)
The revision includes the following global update:
Revision A (August 2009)
• Added Note 2 to the shaded table that appears at
the beginning of each chapter. This new note
provides information regarding the availability of
registers and their associated bits
This is the initial revision of this document.
Other major changes are referenced by their respective
chapter/section in Table B-1.
TABLE B-1:
MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, USB, CAN and Added the following devices:
Ethernet 32-Bit Flash
- PIC32MX575F256L
Microcontrollers”
- PIC32MX695F512L
- PIC32MX695F512H
The 100-pin TQFP pin diagrams have been updated to reflect the current pin
name locations (see the “Pin Diagrams” section).
Added the 121-pin Ball Grid Array (XBGA) pin diagram.
Updated Table 1: “PIC32MX Features”
Added the following tables:
- Table 2: “Pin Names: PIC32MX575F256L and PIC32MX575F512L
Devices”,
- Table 3: “Pin Names: PIC32MX675F256L, PIC32MX675F512L and
PIC32MX695F512L Devices”
- Table 4: “Pin Names: PIC32MX775F256L, PIC32MX775F512L,
PIC32MX795F512L and Devices”
Updated the following pins as 5V tolerant:
- 64-pin QFN: Pin 36 (D-/RG3) and Pin 37 (D+/RG2)
- 64-pin TQFP: Pin 36 (D-/RG3) and Pin 37 (D+/RG2)
- 100-pin TQFP: Pin 56 (D-/RG3) and Pin 57 (D+/RG2)
Section 2.0 “Guidelines for Getting Removed the last sentence of Section 2.3.1 “Internal Regulator Mode”.
Started with 32-Bit
Removed Section 2.3.2 “External Regulator Mode”
Microcontrollers”
DS61156C-page 228
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE B-1:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Section 4.0 “Memory
Organization”
Update Description
Updated all register tables to include the Virtual Address and All Resets
columns.
Updated the title of Figure 4-1 to include the PIC32MX575F256L device.
Updated the title of Figure 4-3 to include the PIC32MX695F512L and
PIC32MX695F512H devices. Also changed PIC32MX795F512L to
PIC32MX795F512H.
Updated the title of Table 4-3 to include the PIC32MX695F512H device.
Updated the title of Table 4-5 to include the PIC32MX575F5256L device.
Updated the title of Table 4-6 to include the PIC32MX695F512L device.
Reversed the order of Table 4-11 and Table 4-12.
Reversed the order of Table 4-14 and Table 4-15.
Updated the title of Table 4-15 to include the PIC32MX575F256L and
PIC32MX695F512L devices.
Updated the title of Table 4-45 to include the PIC32MX575F256L device.
Updated the title of Table 4-47 to include the PIC32MX695F512H and
PIC32MX695F512L devices.
Section 12.0 “I/O Ports”
Updated the second paragraph of Section 12.1.2 “Digital Inputs” and
removed Table 12-1.
Section 22.0 “10-Bit Analog-toDigital Converter (ADC)”
Updated the ADC Conversion Clock Period Block Diagram (see Figure 22-2).
Section 28.0 “Special Features”
Removed references to the ENVREG pin in Section 28.3 “On-Chip Voltage
Regulator”.
Updated the first sentence of Section 28.3.1 “On-Chip Regulator and
POR” and Section 28.3.2 “On-Chip Regulator and BOR”.
Updated the Connections for the On-Chip Regulator (see Figure 28-2).
Section 31.0 “Electrical
Characteristics”
Updated the Absolute Maximum Ratings and added Note 3.
Added Thermal Packaging Characteristics for the 121-pin XBGA package
(see Table 31-3).
Updated the Operating Current (IDD) DC Characteristics (see Table 31-5).
Updated the Idle Current (IIDLE) DC Characteristics (see Table 31-6).
Updated the Power-Down Current (IPD) DC Characteristics (see Table 31-7).
Removed Note 1 from the Program Flash Memory Wait State Characteristics
(see Table 31-11).
Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics,
changing SP52 to SP35 between the MSb and Bit 14 on SDOx (see
Figure 31-13).
Section 32.0 “Packaging
Information”
Added the 121-pin XBGA package marking information and package details.
“Product Identification System”
Added the definition for BG (121-lead 10x10x1.1 mm, XBGA).
Added the definition for Speed.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 229
PIC32MX5XX/6XX/7XX
Revision C (February 2010)
The revision includes the following updates, as
described in Table B-2:
TABLE B-2:
MAJOR SECTION UPDATES
Section Name
“High-Performance, USB, CAN
and Ethernet 32-Bit Flash
Microcontrollers”
Update Description
Added the following devices:
•
•
•
•
•
•
PIC32MX675F256H
PIC32MX775F256H
PIC32MX775F512H
PIC32MX675F256L
PIC32MX775F256L
PIC32MX775F512L
Added the following pins:
•
•
•
•
EREFCLK
ECRSDV
AEREFCLK
AECRSDV
Added the EREFCLK and ECRSDV pins to Table 3 and Table 4.
Section 1.0 “Device Overview”
Updated the pin number pinout I/O descriptions for the following pin names in
Table 1-1:
• SCL1A
• TMS
• C1IN-
• SDA1A
• TCK
• C1IN+
• SCL2
• TDI
• C1OUT
• SDA2
• TDO
• C2IN-
• SCL2A
• RTCC
• C2IN+
• SDA2A
• CVREF-
• C2OUT
• SCL3A
• CVREF+
• PMA0
• SDA3A
• CVREFOUT
• PMA1
Added the following pins to the Pinout I/O Descriptions table (Table 1-1):
•
•
•
•
DS61156C-page 230
EREFCLK
ECRSDV
AEREFCLK
AECRSDV
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE B-2:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Section 4.0 “Memory
Organization”
Update Description
Added new devices and updated the virtual and physical memory map values in
Figure 4-1.
Added new devices to Figure 4-2.
Added new devices to the following register maps:
•
•
•
•
•
•
•
•
Table 4-3, Table 4-4, Table 4-6 and Table 4-7 (Interrupt Register Maps)
Table 4-12 (I2C2 Register Map)
Table 4-15 (SPI1 Register Map)
Table 4-24 through Table 4-35 (PORTA-PORTG Register Maps)
Table 4-36 and Table 4-37 (Change Notice and Pull-up Register Maps)
Table 4-45 (CAN1 Register Map)
Table 4-46 (CAN2 Register Map)
Table 4-47 (Ethernet Controller Register Map)
Changed the bits named POSCMD to POSCMOD in Table 4-42 (Device
Configuration Word Summary).
Section 28.0 “Special
Features”
Changed all references of POSCMD to POSCMOD in the Device Configuration
Word 1 register (see Register 28-2).
Appendix A: “Migrating from
PIC32MX3XX/4XX to
PIC32MX5XX/6XX/7XX
Devices”
Added the new section A.3 “Pin Assignments”.
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 231
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 232
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
INDEX
A
D
AC Characteristics ............................................................ 180
10-Bit Conversion Rate Parameters ......................... 204
A/D Conversion Requirements ................................. 205
ADC Specifications ................................................... 202
EJTAG Timing Requirements ................................... 212
Ethernet .................................................................... 201
Internal FRC Accuracy.............................................. 182
Internal RC Accuracy ................................................ 182
OTG Electrical Specifications ................................... 211
Parallel Master Port Read Requirements ................. 209
Parallel Master Port Write ......................................... 210
Parallel Master Port Write Requirements.................. 210
Parallel Slave Port Requirements ............................. 208
PLL Clock Timing...................................................... 182
Assembler
MPASM Assembler................................................... 168
DC Characteristics............................................................ 172
I/O Pin Input Specifications ...................................... 176
I/O Pin Output Specifications.................................... 177
Idle Current (IIDLE) .................................................... 174
Operating Current (IDD) ............................................ 173
Power-Down Current (IPD)........................................ 175
Program Memory...................................................... 177
Temperature and Voltage Specifications.................. 172
Development Support ....................................................... 167
Direct Memory Access (DMA) Controller.......................... 117
B
Block Diagrams
A/D Module ............................................................... 141
Comparator I/O Operating Modes............................. 147
Comparator Voltage Reference ................................ 149
Connections for On-Chip Voltage Regulator............. 162
Core and Peripheral Modules ..................................... 23
DMA .......................................................................... 117
Ethernet Controller.................................................... 145
I2C Circuit ................................................................. 134
Input Capture ............................................................ 127
Interrupt Controller .................................................... 109
JTAG Programming, Debugging and
Trace Ports ....................................................... 163
MCU............................................................................ 39
Output Compare Module........................................... 129
PIC32MX CAN Module ............................................. 143
PMP Pinout and Connections to External
Devices ............................................................. 137
Prefetch Module........................................................ 115
Reset System............................................................ 107
RTCC ........................................................................ 139
SPI Module ............................................................... 131
Timer1....................................................................... 123
Timer2/3/4/5 (16-Bit) ................................................. 125
Typical Multiplexed Port Structure ............................ 121
UART ........................................................................ 135
WDT and Power-up Timer ........................................ 161
Brown-out Reset (BOR)
and On-Chip Voltage Regulator................................ 162
C
C Compilers
MPLAB C18 .............................................................. 168
Clock Diagram .................................................................. 113
Comparator
Specifications............................................................ 178
Comparator Module .......................................................... 147
Comparator Voltage Reference (CVREF ........................... 149
Configuration Bit ............................................................... 153
Controller Area Network (CAN)......................................... 143
CPU Module........................................................................ 35
 2010 Microchip Technology Inc.
E
Electrical Characteristics .................................................. 171
AC............................................................................. 180
Errata .................................................................................. 21
Ethernet Controller............................................................ 145
External Clock
Timer1 Timing Requirements ................................... 186
Timer2, 3, 4, 5 Timing Requirements ....................... 187
Timing Requirements ............................................... 181
F
Flash Program Memory .................................................... 105
RTSP Operation ....................................................... 105
I
I/O Ports ........................................................................... 121
Parallel I/O (PIO) ...................................................... 122
Instruction Set................................................................... 165
Inter-Integrated Circuit (I2C .............................................. 133
Internal Voltage Reference Specifications........................ 179
Interrupt Controller............................................................ 109
IRG, Vector and Bit Location .................................... 110
M
MCU
Architecture Overview ................................................ 40
Coprocessor 0 Registers ............................................ 42
Core Exception Types ................................................ 43
EJTAG Debug Support............................................... 44
Power Management ................................................... 44
MCU Module....................................................................... 39
Memory Maps ............................................................... 46–48
Memory Organization ......................................................... 45
Layout......................................................................... 45
Migration
PIC32MX3XX/4XX to PIC32MX5XX/6XX/7XX......... 227
MPLAB ASM30 Assembler, Linker, Librarian ................... 168
MPLAB Integrated Development
Environment Software .............................................. 167
MPLAB PM3 Device Programmer .................................... 170
MPLAB REAL ICE In-Circuit Emulator System ................ 169
MPLINK Object Linker/MPLIB Object Librarian ................ 168
O
Open-Drain Configuration................................................. 122
Oscillator Configuration .................................................... 113
Output Compare ............................................................... 129
Preliminary
DS61156C-page 233
PIC32MX5XX/6XX/7XX
P
Packaging ......................................................................... 213
Details ....................................................................... 215
Marking ..................................................................... 213
Parallel Master Port (PMP) ............................................... 137
PIC32MX Family USB Interface Diagram ......................... 120
Pinout I/O Descriptions (table) ............................................ 24
Power-on Reset (POR)
and On-Chip Voltage Regulator ................................ 162
Power-Saving Features..................................................... 151
CPU Halted Methods ................................................ 151
Operation .................................................................. 151
with CPU Running..................................................... 151
Prefetch Cache ................................................................. 115
Program Flash Memory
Wait State Characteristics......................................... 178
R
Real-Time Clock and Calendar (RTCC)............................ 139
Register Maps ............................................................. 49–103
Registers
DDPCON (Debug Data Port Control)........................ 164
DEVCFG0 (Device Configuration Word 0 ................. 153
DEVCFG1 (Device Configuration Word 1 ................. 155
DEVCFG2 (Device Configuration Word 2 ................. 157
DEVCFG3 (Device Configuration Word 3 ................. 159
DEVID (Device and Revision ID) .............................. 160
Resets ............................................................................... 107
Revision History ................................................................ 228
Timing Requirements
CLKO and I/O ........................................................... 183
Timing Specifications
CAN I/O Requirements ............................................. 200
I2Cx Bus Data Requirements (Master Mode)........... 195
I2Cx Bus Data Requirements (Slave Mode)............. 198
Input Capture Requirements..................................... 187
Output Compare Requirements................................ 188
Simple OCx/PWM Mode Requirements ................... 188
SPIx Master Mode (CKE = 0) Requirements............ 189
SPIx Master Mode (CKE = 1) Requirements............ 190
SPIx Slave Mode (CKE = 1) Requirements.............. 192
SPIx Slave Mode Requirements (CKE = 0).............. 191
U
UART ................................................................................ 135
USB On-The-Go (OTG) .................................................... 119
V
VCAP/VDDCORE pin............................................................ 162
Voltage Reference Specifications..................................... 179
Voltage Regulator (On-Chip) ............................................ 162
W
Watchdog Timer (WDT).................................................... 161
WWW, On-Line Support ..................................................... 21
S
Serial Peripheral Interface (SPI) ....................................... 131
Software Simulator (MPLAB SIM)..................................... 169
Special Features ............................................................... 153
T
Timer1 Module .................................................................. 123
Timer2/3, Timer4/5 Modules ............................................. 125
Timing Diagrams
10-Bit A/D Conversion (CHPS = 01, SIMSAM = 0,
ASAM = 0, SSRC = 000) .................................. 206
10-Bit A/D Conversion (CHPS = 01, SIMSAM = 0,
ASAM = 1, SSRC = 111, SAMC = 00001)........ 207
CAN I/O..................................................................... 200
EJTAG ...................................................................... 212
External Clock ........................................................... 180
I/O Characteristics .................................................... 183
I2Cx Bus Data (Master Mode) .................................. 194
I2Cx Bus Data (Slave Mode) .................................... 197
I2Cx Bus Start/Stop Bits (Master Mode) ................... 194
I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 197
Input Capture (CAPx)................................................ 187
OCx/PWM ................................................................. 188
Output Compare (OCx) ............................................. 188
Parallel Master Port Read ......................................... 209
Parallel Master Port Write ......................................... 210
Parallel Slave Port .................................................... 208
SPIx Master Mode (CKE = 0).................................... 189
SPIx Master Mode (CKE = 1).................................... 190
SPIx Slave Mode (CKE = 0)...................................... 191
SPIx Slave Mode (CKE = 1)...................................... 192
Timer1, 2, 3, 4, 5 External Clock............................... 186
UART Reception ....................................................... 136
UART Transmission (8-Bit or 9-Bit Data) .................. 136
DS61156C-page 234
Preliminary
 2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PIC32 MX 5XX F 512 H T - 80 I / PT - XXX
Example:
PIC32MX575F256H-80I/PT:
General purpose PIC32MX,
256 KB program memory,
64-pin, Industrial temperature,
TQFP package.
Microchip Brand
Architecture
Product Groups
Flash Memory Family
Program Memory Size (KB)
Pin Count
Tape and Reel Flag (if applicable)
Speed
Temperature Range
Package
Pattern
Flash Memory Family
Architecture
MX = 32-bit RISC MCU core
Product Groups
5XX = General purpose microcontroller family
6XX = General purpose microcontroller family
7XX = General purpose microcontroller family
Flash Memory Family
F
= Flash program memory
Program Memory Size 256 = 256K
512 = 512K
Pin Count
H
L
= 64-pin
= 100-pin
Speed
80
= 80 MHz
Temperature Range
I
= -40°C to +85°C (Industrial)
Package
PT
PT
PF
MR
BG
=
=
=
=
=
Pattern
Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise)
ES = Engineering Sample
64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack)
100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack)
100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack)
64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat)
121-Lead (10x10x1.1 mm) XBGA (Plastic Thin Profile Ball Grid Array)
 2010 Microchip Technology Inc.
Preliminary
DS61156C-page 235
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/05/10
DS61156C-page 236
Preliminary
 2010 Microchip Technology Inc.