PRELIMINARY DATA SHEET For information only Battery Protection MicroSURF™ TS8314 – Bi-directional N-Channel 2.5V Specified MicroSURF™ General Description Taiwan Semiconductor’s new low cost, state of the art MicroSURF™ lateral MOSFET process technology in chipscale bondwireless packaging minimizes PCB space and RDS(ON) plus provides an ultralow Qg X RDS(ON) figure of merit. 130 O D 130 O Features • 6.5A, 20V RDS1(ON) equivalent = 15mΩ at 4.5 Volts MicroSURF™ for Battery Protection • 5.5A, 20V RDS1(ON) equivalent = 22mΩ at 2.5 Volts • Low profile package: less than 0.8mm height when mounted on PCB. Patent Pending G2 S1 S1 • Excellent thermal characteristics. S2 S2 S2 • Integrated gate diodes provide ElectroStatic Discharge (ESD) protection of 4000V Human Body Model (HBM). S1 S1 S1 • Lead free solder bumps available. S2 S2 G1 • Occupies less than 1/5 the area of TSSOP-8. Bottom: Bump Side Absolute Maximum Ratings TA=25°C unless otherwise noted Symbol Parameter VS1S2 VGS IS1S2 PD TJ, TSTG Source1-Source2 Voltage Gate-Source Voltage Source1-Source2 Current – Continuous – Pulsed Power Dissipation (Steady State) Operating and Storage Junction Temperature Range Ratings Units 20 +12 / -0.5 6.5 13 1.3 -55 to +150 V V A W ºC Thermal Characteristics RθJA RθJR Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Balls 82 7 1 °C/W 8/15/03 Rev3 PRELIMINARY DATA SHEET Electrical Characteristics TS8314 Electrical Characteristics TA=25°C unless otherwise specified Symbol Parameter V(BD)S 1S 2 S Source-to-Source Breakdown Voltage IS 1S 2 S Zero Gate Voltage Source Current Test Condition VGS =0V, IS =250µA Min Typ Max 20 Units V VS 1S 2 =20V, VGS =0V, T=150°C 50 µA IGS S Gate-Body Leakage VGS =7V, VS 1S 2 =0V 100 nA IGS S Gate-Body Leakage VGS =12V, VS 1S 2 =0V 10 mA VGS (th ) rS 1S 2(on ) rDS 1(o n) e q uiva le n t VS 1S 2 =VGS , IS =250µA 0.8 1.2 V Source-to-Source On-State Resistance VGS =4.5V, IS =6.5A 26 30 mΩ Source-to-Source On-State Resistance VGS =2.5V, IS =5.5A 38 44 mΩ Source-to-Source On-State Resistance VGS =4.5V, IS =6.5A 13 15 mΩ Drain-to-Source On-State Resistance VGS =2.5V, IS =5.5A 19 22 mΩ Gate Threshold Voltage Cis s Input Capacitance VS 1S 2 =20V, VG =0V, F=1MHZ 1100 pF Cos s Output Capacitance VS 1S 2 =20V, VG =0V, F=1MHZ 400 pF Crs s Reverse Transfer Capacitance VS 1S 2 =20V, VG =0V, F=1MHZ 300 pF Qg Total Gate Charge VGS =5V, IS =8A, VS 1S 2 =10V 15 nC trr Source-Drain Reverse Recovery Time IS =1A, VGS =0V, di/dt=100A/µs 40 ns 0.71 V VS S Diode Forward Voltage IS =1A, VGS =0V 2 8/15/03 Rev3 VGS = 3.5V VGS = 2.5V VGS = 2.0v TS8314 VGS = 4.5V VGS = 1.5V 3 8/15/03 Rev3 TS8314 125ºC 25ºC 0 0.4 0.8 1.2 4 1.6 2.0 8/15/03 Rev3 TS8314 VGS = 2.5v VGS = 4.5v VGS = 10v 5 8/15/03 Rev3 TS8314 125ºC 25ºC 6 8/15/03 Rev3 TS8314 VGS = 5.0v ID = 5A 7 8/15/03 Rev3 TS8314 Ciss Coss Crss 8 8/15/03 Rev3 TS8314 Qg (nC) 9 8/15/03 Rev3 TS8314 Tj = 150ºC Tj = 25ºC 10 8/15/03 Rev3 PRELIMINARY DATA SHEET Dimensional Outline and Pad Layout TS8314 SILICON 0.27mm 0.80mm MAX 1.60mm 0.30mm 0.50mm 2.10mm Bump Ø 0.37mm 0.50mm 0.30mm Bumps are Eutectic solder 63/37 Sn/Pb 11 8/15/03 Rev3 PRELIMINARY DATA SHEET Dimensional Outline and Pad Layout S1 S1 G2 S2 S2 S2 S1 S1 S1 G1 S2 S2 TS8314 Ø 0.25mm Solder Mask Ø ~ 0.35mm D = Drain Pad S = Source Pad G = Gate Pad 0.50mm 0.50mm LAND PATTERN RECOMMENDATION 831XXX MARK ON BACKSIDE OF DIE XXX = Date/Lot Traceability Code 12 8/15/03 Rev3 TS8314 Thermal Resistance Analysis GWS8314 Thermal Analysis 13 8/15/03 Rev3 TS8314 Die Top View -transparent view for clarity. 1.00 in. 1.00 in. Cutaway Detail Drain (top plane) Source (buried plane) 1/4 Symmetry Model FR4 Board modeled as 1.6mm Thick with 2 oz. Copper (0.0712mm) plane for Drain and Source NOT TO SCALE GWS8314 Thermal Analysis 14 Adiabatic Planes 8/15/03 Rev3 Finite Element Model: • Linear Thermal elements. Combination of tetrahedrals, 6 noded prisms and 8 noded bricks • Heat Transfer conditions: • Bottom of FR4 board constrained to 25 degrees C • Power dissipation = 0.4 W per quarter model, in the form of a uniform heat flux at the die junction surface. • Linear Thermal conduction analysis. No convection or radiation included in model. • ~9800K elements. GWS8314 Thermal Analysis 15 8/15/03 Rev3 Material Properties Used for Analysis Material Thickness (mm) K (W/m°C) FR4 Copper Layers (2 oz.) Solder (96.8Sn/2.6Ag/.6Cu) Silicon Via (Composite of Cu and Epoxy) 1.60000 0.07120 0.27000 0.64000 See model 2.5 390 50 150 210 NOTE: 1. Values obtained from http://www.boulder.nist.gov/div853/lead%20free/part2.htm 2. Solder thermal conductivity is best conservative estimate based on composition Model: Taiwan Semiconductor TS8314 Part GWS8314 Thermal Analysis 16 8/15/03 Rev3 Cross Section of FEA Model D S D Thicknesses Si Die (0.64 mm) Solder Bump (0.27 mm) Copper (0.0712 mm) = 2 0Z. (2.8 mils) FR4 (1.60 mm total) S 1.00 in x 1.00 in board Via: 0.25 mm Dia. with 2 OZ copper plated hole, filled with conductive epoxy. Drain Plane Source Plane GWS8314 Thermal Analysis 17 8/15/03 Rev3 Drain Plane (2 OZ Cu) Vias Intermediate FR4 Plane (0.0345mm) Source Plane (2 OZ Cu) FR4 Bulk BREAKDOWN OF FR4 LAYERS USED IN THE FE MODEL. Total Thickness 1.6 mm) This illustration shows the ½ symmetry model. The actual FE model uses ¼ symmetry for efficiency. GWS8314 Thermal Analysis 18 8/15/03 Rev3 FEA Model Detail Temp Restraint Note: ¼ symmetry used. Solder balls use tetrahedral elements. All other elements are either prisms or bricks. Heat flux at Junction GWS8314 Thermal Analysis 19 8/15/03 Rev3 General Result: About 56% of the temp drop occurs in the FR4 layers, while 44% occurs in the solder ball. Detail GWS8314 Thermal Analysis 20 8/15/03 Rev3 Detail FR4: Not including Copper Planes GWS8314 Thermal Analysis 21 8/15/03 Rev3 FR4: source plane Detail GWS8314 Thermal Analysis 22 8/15/03 Rev3 Intermediate FR4 plane Detail GWS8314 Thermal Analysis 23 8/15/03 Rev3 Drain FR4 plane Detail GWS8314 Thermal Analysis 24 8/15/03 Rev3 Top Side Vias from solder balls to source plane Bottom Side GWS8314 Thermal Analysis 25 8/15/03 Rev3 Top side Solder Balls: hottest spots Coolest spots Bottom Side GWS8314 Thermal Analysis 26 8/15/03 Rev3 Top Side Silicon: NOTE: The difference between min and max temperatures is only 1.3°C. Bottom Side GWS8314 Thermal Analysis 27 8/15/03 Rev3 Summary of Results ∆T θ = Power Thermal Resistance calculations: Layer * Junction to bottom of Ball (Average) Ball to bottom of Drain Plane Drain Plane to bottom of Intermediate FR4 Intermediate FR4 to bottom of Source Plane Souce Plane to bottom of FR4 Total Junction to bottom of FR4 ∆T (°C) 10.5000 0.0037 1.3800 0.0120 12.5500 24.4457 Resistance (°C/W) 6.56250 0.00231 0.86250 0.00750 7.84375 15.27856 * temperatures are taken on the hottest spot in each layer and the node directly underneath it on the opposite side junction TJ TFR4 heat FR4 GWS8314 Thermal Analysis 28 8/15/03 Rev3