TI SN65HVD07D

SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
www.ti.com
SLLS533B – MAY 2002 – REVISED MAY 2003
HIGH OUTPUT RS-485 TRANSCEIVERS
FEATURES
D Minimum Differential Output Voltage of 2.5 V
D
D
D
D
D
D
D
D
Into a 54-Ω Load
Open-Circuit, Short-Circuit, and Idle-Bus
Failsafe Receiver
1/8th Unit-Load Option Available (Up to 256
Nodes on the Bus)
Bus-Pin ESD Protection Exceeds 16 kV HBM
Driver Output Slew Rate Control Options
Electrically Compatible With ANSI
TIA/EIA-485-A Standard
Low-Current Standby Mode . . . 1 µA Typical
Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
Pin Compatible With Industry Standard
SN75176
APPLICATIONS
D Data Transmission Over Long or Lossy Lines
D
D
D
D
D
D
or Electrically Noisy Environments
Profibus Line Interface
Industrial Process Control Networks
Point-of-Sale (POS) Networks
Electric Utility Metering
Building Automation
Digital Motor Control
DESCRIPTION
The SN65HVD05, SN75HVD05, SN65HVD06,
SN75HVD06, SN65HVD07, and SN75HVD07 combine
a 3-state differential line driver and differential line
receiver. They are designed for balanced data
transmission
and
interoperate
with
ANSI
TIA/EIA-485-A and ISO 8482E standard-compliant
devices. The driver is designed to provide a differential
output voltage greater than that required by these
standards for increased noise margin. The drivers and
receivers have active-high and active-low enables
respectively, which can be externally connected
together to function as direction control.
The driver differential outputs and receiver differential
inputs connect internally to form a differential input/
output (I/O) bus port that is designed to offer minimum
loading to the bus whenever the driver is disabled or not
powered. These devices feature wide positive and
negative common-mode voltage ranges, making them
suitable for party-line applications.
D OR P PACKAGE
(TOP VIEW)
R
RE
DE
D
DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL OUTPUT CURRENT
V O – Differential Output Voltage – V
4
60 Ω Load
Line
3.5
TA = 25°C
DE at VCC
D at VCC
VCC = 5 V
R
30 Ω Load
Line
3
8
2
7
3
6
4
5
VCC
B
A
GND
LOGIC DIAGRAM
(POSITIVE LOGIC)
5
4.5
1
RE
1
2
2.5
2
DE
1.5
3
6
4
1
D
0.5
7
A
B
0
0
20
40
60
80
100
120
IOD – Differential Output Current – mA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright  2002–2003, Texas Instruments Incorporated
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
www.ti.com
SLLS533B – MAY 2002 – REVISED MAY 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
MARKED AS
DRIVER
OUTPUT SLOPE
CONTROL
PLASTIC
DUAL-IN-LINE
PACKAGE
(PDIP)
SMALL OUTLINE
IC (SOIC)
PACKAGE
SIGNALING
RATE
UNIT
LOAD
40 Mbps
1/2
No
SN65HVD05D
SN65HVD05P
65HVD05
VP05
10 Mbps
1/8
Yes
SN65HVD06D
SN65HVD06P
65HVD06
VP06
PART NUMBER(2)
TA
–40°C
40 C to 85°C
85 C
1 Mbps
1/8
Yes
SN65HVD07D
SN65HVD07P
65HVD07
VP07
40 Mbps
1/2
No
SN75HVD05D
SN75HVD05P
75HVD05
VN05
10 Mbps
1/8
Yes
SN75HVD06D
SN75HVD06P
75HVD06
VN06
1 Mbps
1/8
Yes
SN75HVD07D SN75HVD07P
75HVD07
(1) For the most current specification and package information, refer to our web site at www.ti.com.
(2) The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD05DR).
VN07
–0°C
0 C to 70°C
70 C
PACKAGE DISSIPATION RATINGS (SEE FIGURE 12 AND FIGURE 13)
TA ≤ 25°C
POWER RATING
D(2)
D(3)
710 mW
DERATING FACTOR(1)
ABOVE TA = 25°C
5.7 mW/°C
1282 mW
10.3 mW/°C
821 mW
667 mW
P
1000 mW
8.0 mW/°C
640 mW
520 mW
PACKAGE
TA = 70°C
POWER RATING
TA = 85°C POWER
RATING
455 mW
369 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3
(3) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) (2)
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
Supply voltage range, VCC
–0.3 V to 6 V
Voltage range at A or B
–9 V to 14 V
Input voltage range at D, DE, R or RE
–0.5 V to VCC + 0.5 V
Voltage input range, transient pulse, A and B, through 100 Ω (see Figure 11)
Electrostatic discharge
Human body model(3)
Charged-device model(4)
–50 V to 50 V
A, B, and GND
16 kV
All pins
4 kV
All pins
Continuous total power dissipation
Storage temperature range, Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
1 kV
See Dissipation Rating Table
–65°C to 150°C
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
2
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
www.ti.com
SLLS533B – MAY 2002 – REVISED MAY 2003
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage, VCC
Voltage at any bus terminal (separately or common mode) VI or VIC
High-level input voltage, VIH
D, DE, RE
Low-level input voltage, VIL
D, DE, RE
MAX UNIT
V
12
V
V
0.8
V
12
V
–12
Driver
–100
Receiver
mA
–8
Driver
Low level output current,
Low-level
current IOL
5.5
2
Differential input voltage, VID (see Figure 7)
High level output current,
High-level
current IOH
NOM
4.5
–7(1)
100
Receiver
8
mA
SN65HVD05
SN65HVD06
–40
40
85
°C
C
0
70
°C
C
SN65HVD07
Operating free-air
free air temperature,
temperature TA
SN75HVD05
SN75HVD06
SN75HVD07
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
DRIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted(1)
TEST CONDITIONS
PARAMETER
VIK
|VOD|
Input clamp voltage
II = –18 mA
No Load
∆|VOD|
Change in magnitude of differential
output voltage
VOC(SS)
Steady-state common-mode output
voltage
∆VOC(SS)
Change in steady-state
common-mode output voltage
VOC(PP)
Peak-to-peak
Peak
to peakcommon
commonmode output voltage
IOZ
See Figure 1 and Figure 2
–0.2
0.2
V
2.2
3.3
V
–0.1
0.1
V
See Figure 3
600
500
See Figure 3
See receiver input currents
D
Input current
IOS
C(diff)
Short-circuit output current
–7 V ≤ VO ≤ 12 V
Differential output capacitance
VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
RE at VCC,
Receiver disabled and
D & DE at VCC, No load driver enabled
Receiver disabled and
RE at VCC, D at VCC
driver disabled
DE at 0 V, No load
(standby)
DE
Supply current
mV
900
II
ICC
V
2.2
HVD07
High-impedance output current
UNIT
V
2.5
HVD05
HVD06
MAX
VCC
RL = 54 Ω, See Figure 1
Vtest = –7 V to 12 V, See Figure 2
Differential out
output
ut voltage
MIN TYP(1)
–1.5
RE at 0 V,
D & DE at VCC, No load
–100
0
0
100
–250
Receiver enabled and
driver enabled
250
16
µA
mA
pF
9
15
mA
1
5
µA
9
15
mA
(1) All typical values are at 25°C and with a 5-V supply.
3
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
www.ti.com
SLLS533B – MAY 2002 – REVISED MAY 2003
DRIVER SWITCHING CHARACTERISTICS NIL
over operating free-air temperature range unless otherwise noted
TEST
CONDITIONS
PARAMETER
tPLH
tPHL
Propagation
Pro
agation delay time, low
low-to-high-level
to high level out
output
ut
Propagation
Pro
agation delay time, high
high-to-low-level
to low level out
output
ut
Differential out
output
ut signal rise time
HVD05
6.5
11
27
40
HVD07
250
400
HVD05
6.5
11
HVD06
27
40
HVD07
250
400
HVD06
HVD07
tf
tsk(
sk(p))
tsk(
sk(pp))(2)
tPZH1
Differential out
output
ut signal fall time
Pulse skew (|tPHL – tPLH|)
Part-to-part
Part
to art skew
Propagation
Pro
agation delay time, high
high-impedance-to-high-level
im edance to high level out
output
ut
tPZL1
Propagation
Pro
agation delay time, high
high-impedance-to-low-level
im edance to low level out
output
ut
6
28
55
150
300
450
3.6
6
18
28
55
HVD07
150
300
450
HVD05
2
HVD06
2.5
HVD07
10
HVD05
3.5
HVD06
14
HVD07
100
HVD05
25
45
HVD06
RE at 0 V,
RL = 110 Ω,
Ω
See Figure 5
60
250
HVD05
15
45
RE at 0 V,
RL = 110 Ω,
Ω
See Figure 6
ns
ns
ns
ns
ns
ns
ns
25
HVD07
HVD06
UNIT
250
HVD06
HVD05
Propagation
Pro
agation delay time, low
low-level-to-high-impedance
level to high im edance out
output
ut
3.6
18
2.7
HVD07
tPLZ
2.7
HVD05
HVD05
Propagation
Pro
agation delay time, high
high-level-to-high-impedance
level to high im edance out
output
ut
RL = 54 Ω,
CL = 50 pF,
F,
See Figure 4
HVD06
HVD07
tPHZ
MAX
HVD06
HVD05
tr
MIN TYP(1)
ns
ns
200
14
HVD06
90
HVD07
550
ns
tPZH2
Propagation delay time, standby-to-high-level output
RL = 110 Ω,
RE at 3 V,
See Figure 5
6
µs
tPZL2
Propagation delay time, standby-to-low-level output
RL = 110 Ω,
RE at 3 V,
See Figure 6
6
µs
(1) All typical values are at 25°C and with a 5-V supply.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
4
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
www.ti.com
SLLS533B – MAY 2002 – REVISED MAY 2003
RECEIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
MIN TYP(1)
TEST CONDITIONS
VIT+
Positive-going input threshold
voltage
IO = –8 mA
VIT–
Negative-going input threshold
voltage
IO = 8 mA
–0.2
–1.5
Vhys
VIK
Hysteresis voltage (VIT+ – VIT–)
VOH
VOL
High-level output voltage
II = –18 mA
VID = 200 mV,
Low-level output voltage
VID = –200 mV,
IOH = –8 mA,
IOL = 8 mA,
High-impedance-state output
current
VO = 0 or VCC
RE at VCC
IOZ
Enable-input clamp voltage
HVD05
II
IIH
IIL
High-level input current, RE
C(diff)
Differential input capacitance
ICC
Low-level input current, RE
Supply current
UNIT
–0.01
V
V
35
Other in
input
ut
at 0 V
Bus input current
HVD06,
HVD07
MAX
Other in
input
ut
at 0 V
VA or VB = 12 V
VA or VB = 12 V,
See Figure 7
V
0.4
–1
VCC = 0 V
VCC = 0 V
VA or VB = 12 V
VA or VB = 12 V,
VCC = 0 V
VA or VB = –7 V
VA or VB = –7 V,
V
4
See Figure 7
VA or VB = –7 V
VA or VB = –7 V,
VCC = 0 V
VIH = 2 V
VIL = 0.8 V
VI = 0.4 sin (4E6πt) + 0.5 V,
DE at 0 V
RE at 0 V,
D & DE at 0 V,
Receiver enabled and driver disabled
No load
mV
1
0.23
0.5
0.3
0.5
–0.4
–0.13
–0.4
–0.15
0.06
0.1
0.08
0.13
V
µA
mA
mA
–0.1
–0.05
–0.05
–0.03
–60
–26.4
µA
–60
–27.4
µA
16
pF
5
10
mA
RE at VCC,
DE at 0 V,
D at VCC,
No load
Receiver disabled and driver disabled
(standby)
1
5
µA
RE at 0 V,
D & DE at VCC,
No load
Receiver enabled and driver enabled
9
15
mA
(1) All typical values are at 25°C and with a 5-V supply.
5
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
www.ti.com
SLLS533B – MAY 2002 – REVISED MAY 2003
RECEIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
tPLH
tPHL
Propagation delay time, low-to-high-level output 1/2 UL
HVD05
14.6
25
ns
Propagation delay time, high-to-low-level output 1/2 UL
HVD05
14.6
25
ns
HVD06
55
70
tPLH
Propagation delay time,
time low-to-high-level
low to high level output 1/8 UL
HVD07
55
70
55
70
55
70
HVD06
tPHL
tsk(
sk(p))
tsk(
sk(pp))((2))
Propagation delay time,
time high-to-low-level
high to low level output 1/8 UL
Pulse skew (|tPHL – tPLH|)
Part-to-part
Part
to art skew
tr
tf
Output signal rise time
tPZH1
tPZL1
Output enable time to high level
tPHZ
tPLZ
Output disable time from high level
tPZH2
tPZL2
Propagation delay time, standby-to-high-level output
Output signal fall time
Output enable time to low level
HVD07
VID = –1.5 V to 1.5 V,
CL = 15 pF,
F,
See Figure 8
HVD05
2
HVD06
4.5
HVD07
4.5
HVD05
6.5
HVD06
14
HVD07
14
CL = 15 pF,
F,
See Figure 8
3
2
3
ns
ns
ns
ns
10
CL = 15 pF,
DE at 3 V
V,
See Figure 9
Output disable time from low level
Propagation delay time, standby-to-low-level output
2
ns
10
15
ns
15
CL = 15 pF,
F, DE at 0,
See Figure 10
6
6
µss
(1) All typical values are at 25°C and with a 5-V supply.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
6
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
www.ti.com
SLLS533B – MAY 2002 – REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
VCC
DE
II
375 Ω ±1%
VCC
A
IOA
DE
VOD
0 or 3 V
B
D
54 Ω ±1%
A
VOD
0 or 3 V
IOB
60 Ω ±1%
+ –7 V < V(test)
_ < 12 V
B
VI
375 Ω ±1%
VOB VOA
Figure 2. Driver VOD With Common-Mode
Loading Test Circuit
Figure 1. Driver VOD Test Circuit
and Voltage and Current Definitions
VCC
DE
Input
D
27 Ω ± 1%
A
A
VA
B
VB
VOC(PP)
27 Ω ± 1%
B
CL = 50 pF ±20%
VOC
∆VOC(SS)
VOC
CL Includes Fixture and
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50 Ω
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
3V
VCC
DE
D
Input
Generator
VI
A
B
50 Ω
VOD
RL = 54 Ω
± 1%
1.5 V
CL = 50 pF ±20%
VI
CL Includes Fixture
and Instrumentation
Capacitance
tPLH
1.5 V
0V
tPHL
90%
VOD
≈2V
90%
0V
10%
0V
10%
≈ –2 V
tr
tf
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 4. Driver Switching Test Circuit and Voltage Waveforms
A
3V
D
3V
S1
VO
VI
1.5 V
1.5 V
B
DE
Input
Generator
VI
CL = 50 pF ±20%
50 Ω CL Includes Fixture
and Instrumentation
Capacitance
RL = 110 Ω
± 1%
0.5 V
0V
tPZH(1 & 2)
VOH
VO
2.3 V
tPHZ
≈0V
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
7
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
www.ti.com
SLLS533B – MAY 2002 – REVISED MAY 2003
VCC
RL = 110 Ω
± 1%
A
3V
VI
1.5 V
VI
S1
D
1.5 V
VO
50 Ω
0V
B
DE
Input
Generator
≈3V
tPZL(1 & 2)
tPLZ
CL = 50 pF ±20%
VCC
0.5 V
CL Includes Fixture
and Instrumentation
Capacitance
VO
2.3 V
VOL
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
IA
VA
VA + VB
2
VIC
VB
A
IO
R
VID
B
IB
VO
Figure 7. Receiver Voltage and Current Definitions
A
Input
Generator
R
VI
50 Ω
1.5 V
0V
B
3V
VO
CL = 15 pF ±20%
RE
CL Includes Fixture
and Instrumentation
Capacitance
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
1.5 V
VI
1.5 V
0V
tPLH
VO
tPHL
90% 90%
1.5 V
10%
tr
Figure 8. Receiver Switching Test Circuit and Voltage Waveforms
8
tf
VOH
1.5 V
10% V
OL
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
www.ti.com
SLLS533B – MAY 2002 – REVISED MAY 2003
A
D
0 V or 3 V
Generator: PRR = 100 kHz,
50% Duty Cycle,
tr <6 ns, tf <6 ns, Zo = 50 Ω
3V
B
DE
RE
Input
Generator
VI
50 Ω
A
VCC
VO
S1
R
1 kΩ ± 1%
B
CL = 15 pF ±20%
CL Includes Fixture and
Instrumentation Capacitance
3V
VI
1.5 V
1.5 V
0V
tPZH(1)
tPHZ
VOH –0.5 V
VOH
1.5 V
D at 3 V
S1 to B
VO
≈0V
tPZL(1)
tPLZ
VCC
VO
1.5 V
VOL +0.5 V
D at 0 V
S1 to A
VOL
Figure 9. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
9
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
www.ti.com
SLLS533B – MAY 2002 – REVISED MAY 2003
Generator: PRR = 100 kHz,
50% Duty Cycle,
tr <6 ns, tf <6 ns, Zo = 50 Ω
DE
0V
RE
Input
Generator
VI
50 Ω
A
A
VCC
VO
S1
B
0 V or 1.5 V
R
B
1 kΩ ± 1%
1.5 V or 0 V
CL = 15 pF ±20%
CL Includes Fixture and
Instrumentation Capacitance
3V
VI
1.5 V
0V
tPZH(2)
A at 1.5 V
B at 0 V
S1 to B
VOH
1.5 V
VO
GND
tPZL(2)
A at 0 V
B at 1.5 V
S1 to A
VCC
1.5 V
VO
VOL
Figure 10. Receiver Enable Time From Standby (Driver Disabled)
0 V or 3 V
A
RE
R
Pulse Generator,
15 µs Duration,
1% Duty Cycle
tr, tf ≤ 100 ns
100 Ω
± 1%
B
D
+
_
DE
3 V or 0 V
NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 11. Test Circuit, Transient Over Voltage Test
10
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
www.ti.com
SLLS533B – MAY 2002 – REVISED MAY 2003
FUNCTION TABLES
DRIVER
INPUT
ENABLE
D
DE
A
B
H
L
X
Open
X
H
H
L
H
Open
H
L
Z
H
Z
L
H
Z
L
Z
OUTPUTS
RECEIVER
DIFFERENTIAL INPUTS
ENABLE
OUTPUT
VID = VA – VB
VID ≤ –0.2 V
–0.2 V < VID < –0.01 V
–0.01 V ≤ VID
X
Open Circuit
Short Circuit
X
RE
R
L
L
L
H
L
L
Open
L
?
H
Z
H
H
Z
H = high level; L = low level; Z = high impedance; X = irrelevant;
? = indeterminate
11
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
www.ti.com
SLLS533B – MAY 2002 – REVISED MAY 2003
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Inputs
DE Input
VCC
VCC
100 kΩ
1 kΩ
1 kΩ
Input
Input
100 kΩ
9V
9V
A Input
B Input
VCC
VCC
16 V
100 kΩ
16 V
R3
R1
R3
Input
Input
16 V
R2
R1
100 kΩ
16 V
A and B Outputs
R2
R Output
VCC
VCC
16 V
5Ω
Output
Output
9V
16 V
SN65HVD05
SN65HVD06
SN65HVD07
12
R1/R2
9 kΩ
36 kΩ
36 kΩ
R3
45 kΩ
180 kΩ
180 kΩ
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
www.ti.com
SLLS533B – MAY 2002 – REVISED MAY 2003
TYPICAL CHARACTERISTICS
HVD06
HVD05
MAXIMUM RECOMMENDED STILL-AIR
OPERATING TEMPERATURE
vs
SIGNALING RATE
(D – PACKAGE)
85
Maximum Recommended Still-Air
Operating Temperature – T A ( °C)
Maximum Recommended Still-Air
Operating Temperature – T A ( °C)
MAXIMUM RECOMMENDED STILL-AIR
OPERATING TEMPERATURE
vs
SIGNALING RATE
(D – PACKAGE)
ÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓ
High K Board
25
Low K Board
1
10
Signaling Rate – Mbps
ÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓÓ
ÓÓÓÓÓÓÓÓÓÓÓÓÓ
85
High K Board
25
Low K Board
1
40
10
Signaling Rate – Mbps
Figure 12
120
HVD06
RMS SUPPLY CURRENT
vs
SIGNALING RATE
120
RL = 54 Ω
CL = 50 pF
VCC = 5 V
I CC – RMS Supply Current – mA
I CC – RMS Supply Current – mA
HVD05
RMS SUPPLY CURRENT
vs
SIGNALING RATE
TA = 25°C
RE at VCC
DE at VCC
110
Figure 13
100
90
80
70
60
50
RL = 54 Ω
CL = 50 pF
VCC = 5 V
TA = 25°C
RE at VCC
DE at VCC
100
80
60
40
40
30
0
5
10
15
20
25
Signaling Rate – Mbps
Figure 14
30
35
40
0
2.5
5
7.5
10
Signaling Rate – Mbps
Figure 15
13
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
www.ti.com
SLLS533B – MAY 2002 – REVISED MAY 2003
HVD07
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
RMS SUPPLY CURRENT
vs
SIGNALING RATE
100
250
RL = 54 Ω
CL = 50 pF
VCC = 5 V
TA = 25°C
RE at VCC
DE at VCC
200
I I – Bus Input Current – µ A
I CC – RMS Supply Current – mA
110
90
80
70
60
TA = 25°C
DE at 0 V
VCC = 5 V
150
100
HVD05
50
0
HVD06
HVD07
–50
–100
50
–150
40
100
400
700
Signaling Rate – kbps
–200
–7 –6–5 –4–3 –2–1 0 1 2 3 4 5 6 7 8 9 10 11 12
VI – Bus Input Voltage – V
1000
Figure 16
Figure 17
DRIVER HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
DRIVER LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
160
TA = 25°C
DE at VCC
D at VCC
VCC = 5 V
–20
–40
I OL– Driver Low-Level Output Current – mA
I OH – Driver High-Level Output Current – mA
0
–60
–80
–100
–120
–140
–160
0
0.5
1
1.5
2
2.5
3
3.5
4
VO – High-Level Output Voltage – V
Figure 18
14
4.5
5
TA = 25°C
DE at VCC
D at 0 V
VCC = 5 V
140
120
100
80
60
40
20
0
0
0.5
1 1.5 2
2.5 3 3.5 4 4.5
VO – Low-Level Output Voltage – V
Figure 19
5
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
www.ti.com
SLLS533B – MAY 2002 – REVISED MAY 2003
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
4
TA = 25°C
DE at VCC
D at VCC
RL = 54 Ω
60
I O – Driver Output Current – mA
3.6
3.4
3.2
3
2.8
2.6
2.4
50
40
30
20
10
2.2
2
–40
0
–15
10
35
60
TA – Free-Air Temperature – °C
85
0
0.6
1.2 1.8 2.4
3
3.6 4.2
VCC – Supply Voltage – V
Figure 20
4.8
5.4
Figure 21
DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL OUTPUT CURRENT
5
4.5
VO – Differential Output Voltage – V
VOD – Differential Output Voltage – V
3.8
70
DE at VCC
D at VCC
VCC = 5 V
RL = 54 Ω
4
60 Ω Load
Line
3.5
TA = 25°C
DE at VCC
D at VCC
VCC = 5 V
30 Ω Load
Line
3
2.5
2
1.5
1
0.5
0
0
20
40
60
80
100
IOD – Differential Output Current – mA
120
Figure 22
15
SN65HVD05, SN65HVD06, SN65HVD07
SN75HVD05, SN75HVD06, SN75HVD07
www.ti.com
SLLS533B – MAY 2002 – REVISED MAY 2003
APPLICATION INFORMATION
RT
RT
Device
HVD05
HVD06
HVD07
Number of Devices on Bus
64
256
256
NOTE: The line should be terminated at both ends with its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept as short
as possible.
Figure 23. Typical Application Circuit
16
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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