QorIQ Multicore Processor Development P3041 Development System development and performance evaluation The P3041DS offers significant flexibility in before the customer’s board is ready. allocating its 18 SerDes lanes to various functions. Its base configuration supports The P3041 processor is based upon the two RGMII ports, two PCI Express x4 slots e500mc core, built on Power Architecture® (two lanes per slot), a x4 slot for Freescale’s technology, offering speeds of 1200–1500 MHz. It has a three-level cache hierarchy with 32 KB of instruction and data cache per core, 128 KB of unified backside L2 cache per Overview optional SGMII-PEX-RISER, a x4 slot for Freescale’s optional XAUI-RISER, the Aurora high-speed debug port and two SATA ports. It can also be configured to support up to four core and 1 MB of shared frontside CoreNet platform cache fronting the memory controller. PCI Express slots of widths up to x8. The P3041DS is a flexible development I/Os include 18 SerDes lanes running at up to The P3041DS memory system supports system supporting the quad-core P3041 5 GHz, multiplexed across four PCI Express 2 GB of DDR3 at 1333 MHz. It has 128 MB of device. With its 1.5 GHz P3041 and rich Gen2 controllers, one 10 gigabit Ethernet (GE) NOR flash, 1 GB of NAND flash, a 256 KB I2C input/output (I/O) mix, the board is intended XAUI interface, four 1 GE SGMII interfaces, EEPROM as well as 16 MB of flash and 128 for development of P3041 in networking and four 2.5 Gbps SGMII interfaces, two Serial KB EEPROM of SPI-based memory. It also Ethernet-centric applications, such as control RapidIO (version 1.3 with features of version includes two USB 2.0 receptacles and an SD plane and mixed control plane/data plane 2.1) interfaces, two SATA 2.0 interfaces and card slot. in switches, routers, base station network the high-speed Aurora debug interface. It has interface cards, aerospace and defense and a 64-bit DDR3 and DDR3L (low power) DRAM factory automation. interface with 8-bit ECC support running at The P3041DS can help shorten your time to market. The board, which exercises most capabilities of the device, can serve as a reference for the customer’s hardware development. It can also be used as a debug tool to check behaviors on the board compared to behaviors seen on customer boards. It can be used for software ® a data rate up to 1333 MHz. It includes two USB 2.0 interfaces (including PHY), two dual universal asynchronous receiver/transmitters (DUARTs), an SD/MMC interface, a 32-bit local bus, four I2C and SPI. It also includes the accelerator blocks collectively known as the Data Path Acceleration Architecture (DPAA) that offload various tasks from the core, including routine packet handling, security algorithm calculation and pattern matching. The P3041DS is pre-loaded with an Embedded Linux Essentials for QorIQ Processors with Data Path Acceleration development kit. This kit includes a 2.6.x.x SMP Linux kernel, hugetlbfs for applications with a large memory footprint, user space DPAA for high-performance packet handling, u-boot, the GCC tool chain and Mentor System Builder, among many other features. P3041DS P3041DS Control Board Control: Switches, RST Center System Control Logic FPGA ATX PS 8-bit PromJet Emulator NOR Flash NAND Flash JTAG Set Secondary PSes Three Power Pools Supported by Three Independent, Programmable Regulations VDD_CA Regulators VDD_CB Platform Serdes DDR3 Regulator 1.5v/1.35v 16-bit 16-bit 8-bit I2C • P3041, 1.5 GHz core with 1333 MHz DDR3 data rate • Multiple SysClk inputs for generating various device frequencies Bank1 8 Slot 7 x2 PCIe #3 x2 Slot 4 x2 PCIe #2 x2/x4 or SRIO1 x4 or SRIO2 x2 or SGMII [1:2] or SGMII [1:4] Slot 6 SRIO1 x2 or SGMII [3:4] x1 Bank3 14, 15 x2 Bank1 9 Bank3 16, 17 Bank2 10, 11, x4 12, 13 Freescale Technology Processor Bank1 4, 5 PCIe #1 x2/x4/x8 or SRIO2 x4 x2 x2 SATA 1/2 P3041DS Board Features Bank1 2, 3 DUART SGMIII (1:4) or XAUI #1 or SGMII #5 DDR3 µDIMM x2 Bank1 0, 1 Bank1 6, 7 2 Slot 1 Flash/RCW, RTC/PWR Center/ Thermometer Monitor DDR3 SPI MMC USB x2 x2 SYS/PEX Clocks 3 P3041 Local Bus 16/8-bit SPI Flash 4/8-bit SD/MMC USB 2.0 10/100/1G RGMII COP Legacy Connection PCIe #4 x1 or PCIe #2 x1 PCIe #3 x1/x4 or SGMII [1:4] or XAUI #1 DUART • Six x4 PCI Express slots • Two DUARTs SGMII-PEX-RISER option cards SATA Slot 3 Aurora PCI Express • Can support Freescale’s XAUI-RISER and Slot 5 Slot 2 Debug • JTAG/COP • Aurora high-speed connector • Two vertical SATA connectors Other Memory USB 2.0 • 2 GB unbuffered DDR3 240-pin µDIMM • Two High-Speed USB controllers • IEEE® 1588 connector for Symmetricom option card • One Type A and one MicroAB receptacle • Temperature sensor module with ECC (72-bit bus), 1333 MHz data rate • 128 MB NOR flash Ethernet • 1 GB NAND flash • Supports two 10/100/1000 ports with no • SPI-based 128 MB flash • SPI-based 128 KB EEPROM • SD connector to interface with an SD memory card • Eight general-purpose I/Os add-in cards • dTSEC4 and dTSEC5 as RGMII to Vitesse VSC8244 PHY • Optional SGMII-PEX-RISER expands 10/100/1000 port count to five • 10 GE supported with optional XAUIRISER card For more information, visit freescale.com/QorIQ Freescale, the Freescale logo and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. Document Number: P3041DSFS / REV 0