TI SN65LVDS9637DGN

SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
www.ti.com
SLLS262N – JULY 1997 – REVISED MARCH 2004
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
The SN55LVDS32, SN65LVDS32, SN65LVDS3486,
and SN65LVDS9637 are differential line receivers
that implement the electrical characteristics of
low-voltage differential signaling (LVDS). This
signaling technique lowers the output voltage levels
of 5-V differential standard levels (such as
EIA/TIA-422B) to reduce the power, increase the
switching speeds, and allow operation with a 3.3-V
supply rail. Any of the four differential receivers
provides a valid logical output state with a ±100-mV
differential
input
voltage
within
the
input
common-mode
voltage
range.
The
input
common-mode voltage range allows 1 V of ground
potential difference between two LVDS nodes.
The intended application of these devices and
signaling technique is both point-to-point and
multidrop (one driver and multiple receivers) data
transmission over controlled impedance media of
approximately 100 Ω. The transmission media may
be printed-circuit board traces, backplanes, or cables.
The ultimate rate and distance ofdata transfer
depends on the attenuation characteristics of the
media and the noise coupling to the environment.
The
SN65LVDS32,
SN65LVDS3486,
and
SN65LVDS9637 are characterized for operation from
–40°C to 85°C. The SN55LVDS32 is characterized
for operation from –55°C to 125°C.
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4B
4A
4Y
G
3Y
3A
3B
VCC
3
2
1
20 19
4B
NC
SN55LVDS32FK
(TOP VIEW)
1Y
4
18 4A
G
5
17 4Y
NC
6
16 NC
2Y
7
15 G
2A
8
14 3Y
9
10 11 12 13
3A
DESCRIPTION
16
2
3B
•
1
NC
•
•
•
1B
1A
1Y
G
2Y
2A
2B
GND
1B
•
•
•
SN55LVDS32 . . . J OR W
SN65LVDS32 . . . D OR PW
(Marked as LVDS32 or 65LVDS32)
(TOP VIEW)
1A
•
•
Meet or Exceed the Requirements of ANSI
TIA/EIA-644 Standard
Operate With a Single 3.3-V Supply
Designed for Signaling Rate of up to 400
Mbps
Differential Input Thresholds ±100 mV Max
Typical Propagation Delay Time of 2.1 ns
Power Dissipation 60 mW Typical Per
Receiver at 200 MHz
Bus-Terminal ESD Protection Exceeds 8 kV
Low-Voltage TTL (LVTTL) Logic Output Levels
Pin Compatible With AM26LS32, MC3486, and
µA9637
Open-Circuit Fail-Safe
2B
•
GND
FEATURES
SN65LVDS3486D (Marked as LVDS3486)
(TOP VIEW)
1B
1A
1Y
1,2EN
2Y
2A
2B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4B
4A
4Y
3,4EN
3Y
3A
3B
SN65LVDS9637D (Marked as DK637 or LVDS37)
SN65LVDS9637DGN (Marked as L37)
SN65LVDS9637DGK (Marked as AXF)
(TOP VIEW)
VCC
1Y
2Y
GND
1
8
2
7
3
6
4
5
1A
1B
2A
2B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2004, Texas Instruments Incorporated
SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
www.ti.com
SLLS262N – JULY 1997 – REVISED MARCH 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
–40°C to 85°C
MSOP
CHIP CARRIER
(FK)
CERAMIC DIP
(J)
FLAT PACK
(W)
—
—
—
—
SN65LVDS3486D
—
—
—
—
SN65LVDS9637D
SN65LVDS9637DGN
—
—
—
—
SN65LVDS9637DGK
—
—
—
SNJ55LVDS32J
SNJ55LVDS32W
SN55LVDS32W
(D)
(PW)
SN65LVDS32D
SN65LVDS32PW
–55°C to
125°C
—
—
’LVDS32 logic diagram
(positive logic)
G
G
1A
1B
—
SN65LVDS3486D logic diagram
(positive logic)
4
1A
12
1B
2
1,2EN
3
1Y
1
SNJ55LVDS32FK
2
3
1
1B
4
4A
4B
1Y
3
2Y
5
5
2B
2Y
2B
2Y
2B
3B
2
7
6
6
5
7
3A
8
2A
7
2A
1A
1Y
2A
6
SN65LVDS9637D logic diagram
(positive logic)
3A
10
11
9
3B
3Y
10
11
9
3Y
12
3,4EN
14
13
15
4Y
4A
4B
14
13
15
4Y
FUNCTION TABLES
SN55LVDS32, SN65LVDS32 (1)
(1)
2
SN65LVDS3486 (1)
ENABLES
DIFFERENTIAL INPUT
A, B
G
G
OUTPUT
Y
DIFFERENTIAL INPUT
A, B
ENABLE
EN
OUTPUT
Y
VID ≥ 100 mV
H
X
X
L
H
H
VID ≥ 100 mV
H
H
–100 mV < VID < 100 mV
H
X
X
L
?
?
–100 mV < VID < 100 mV
H
?
VID ≤ –100 mV
H
X
X
L
L
L
VID ≤ –100 mV
H
L
X
L
H
Z
X
L
Z
Open
H
X
X
L
H
H
Open
H
H
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
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SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
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SLLS262N – JULY 1997 – REVISED MARCH 2004
logic symbols†
SN55LVDS32, SN65LVDS32
G
G
4
SN65LVDS3486
≥1
4
1, 2EN
EN
12
2
1A
1A
1B
2A
2B
3A
3B
4A
4B
†
6
2A
3
1
5
6
2Y
7
10
12
3, 4EN
3Y
9
14
4A
14
13
4Y
15
11
9
3B
13
15
4B
1Y
2Y
EN
10
3A
11
5
7
2B
1Y
3
1
1B
2
EN
3Y
4Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Function Table
SN65LVDS9637
DIFFERENTIAL INPUT
A, B
OUTPUT
Y
VID ≥ 100 mV
H
–100 mV < VID < 100 mV
?
VID ≤ –100 mV
L
Open
H
H = high level, L = low level, ? = indeterminate
logic symbol†
SN65LVDS9637
1A
1B
2A
2B
†
8
7
6
5
2
3
1Y
2Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
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SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
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SLLS262N – JULY 1997 – REVISED MARCH 2004
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
EQUIVALENT OF EACH A OR B INPUT
EQUIVALENT OF G, G, 1,2EN OR
3,4EN INPUTS
VCC
VCC
300 kΩ
TYPICAL OF ALL OUTPUTS
VCC
300 kΩ
50 Ω
5Ω
Input
Y Output
A Input
B Input
7V
7V
7V
7V
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VCC
Supply voltage range (2)
VI
Input voltage range
–0.5 V to 4 V
Enables and output
–0.5 V to VCC + 0.5 V
A or B
–0.5 V to 4 V
Continuous total power dissipation
See Dissipation Rating Table
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Tstg
(1)
(2)
260°C
Storage temperature range
–65°C to 150°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
DISSIPATION RATING TABLE
(1)
(2)
4
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D (8)
725 mW
5.8 mW/°C
464 mW
377 mW
—
D (16)
950 mW
7.6 mW/°C
608 mW
494 mW
—
—
DGK
425 mW
3.4 mW/°C
272 mW
221 mW
DGN (2)
2.14 W
17.1 mW/°C
1.37 W
1.11 W
—
FK
1375 mW
11.0 mW/°C
880 mW
715 mW
275 mW
J
1375 mW
11.0 mW/°C
880 mW
715 mW
275 mW
PW (16)
774 mW
6.2 mW/°C
496 mW
402 mW
—
W
1000 mW
8.0 mW/°C
640 mW
520 mW
200 mW
This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
The PowerPAD™ must be soldered to a thermal land on the printed-circuit board. See the application note PowerPAD Thermally
Enhanced Package (SLMA002)
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SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
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SLLS262N – JULY 1997 – REVISED MARCH 2004
RECOMMENDED OPERATING CONDITIONS
MIN NOM
VCC
Supply voltage
VIH
High-level input voltage
G, G, 1,2EN, or 3,4EN
3
VIL
Low-level input voltage
G, G, 1,2EN, or 3,4EN
|VID|
Magnitude of differential input voltage
VIC
Common-mode input voltage (see Figure 1)
MAX
3.3
3.6
2
V
V
0.1
|
ID
2
UNIT
|V
0.8
V
0.6
V
|V
2.4 |
ID
2
V
VCC– 0.8
Operating free-air
temperature
SN65 prefix
–40
85
SN55 prefix
–55
125
°C
COMMON-MODE INPUT VOLTAGE RANGE
vs
DIFFERENTIAL INPUT VOLTAGE
2.5
VIC - Common-Mode Input Voltage Range - V
TA
2
Max at VCC > 3.15 V
Max at VCC = 3 V
1.5
1
0.5
Min
0
0
0.1
0.2
0.3
0.4
0.5
VID - Differential Input Voltage - V
0.6
Figure 1. VIC Versus VID and VCC
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SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
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SLLS262N – JULY 1997 – REVISED MARCH 2004
SN55LVDS32 ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VITH+ Positive-going differential input voltage threshold
See Figure 2, Table 1, and
(2)
VITH– Negative-going differential input voltage threshold (3)
See Figure 2, Table 1, and
(2)
VOH
High-level output voltage
IOH = –8 mA
VOL
Low-level output voltage
IOL = 8 mA
mV
–100
mV
V
0.4
No load
ICC
Supply current
II
Input current (A or B inputs)
II(OFF
Power-off input current (A or B inputs)
VCC = 0,
IIH
High-level input current (EN, G, or G inputs)
IIL
Low-level input current (EN, G, or G inputs)
IOZ
High-impedance output current
VO = 0 or VCC
(1)
(2)
(3)
UNIT
100
2.4
Enabled,
10
18
0.25
0.5
–2
–10
–20
–1.2
–3
Disabled
VI = 0
VI = 2.4 V
)
TYP (1) MAX
VI = 2.4 V
6
V
mA
µA
20
µA
VIH = 2 V
10
µA
VIL = 0.8 V
10
µA
±12
µA
All typical values are at TA = 25°C and with VCC = 3.3 V.
|VITH| = 200 mV for operation at –55°C
The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the
negative-going differential input voltage threshold only.
SN55LVDS32 SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output
1.3
2.3
6
ns
tPHL
Propagation delay time, high-to-low-level output
1.4
2.2
6.1
ns
tsk(o)
Channel-to-channel output skew (1)
tr
tf
0.1
ns
Output signal rise time, 20% to 80%
0.6
ns
Output signal fall time, 80% to 20%
0.7
tPHZ
Propagation delay time, high-level-to-high-impedance output
6.5
12
ns
tPLZ
Propagation delay time, low-level-to-high-impedance output
5.5
12
ns
tPZH
Propagation delay time, high-impedance-to-high-level output
8
14
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
3
12
ns
(1)
6
CL = 10 pF, See Figure 3
See Figure 4
tsk(o) is the maximum delay time difference between drivers on the same device.
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SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
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SLLS262N – JULY 1997 – REVISED MARCH 2004
SN65LVDSxxxx ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN65LVDS32
SN65LVDS3486
SN65LVDS9637
MIN
VIT+
Positive-going differential input voltage threshold
See Figure 2 and Table 1
VIT-
Negative-going differential input voltage threshold (2)
See Figure 2 and Table 1
VOH
High-level output voltage
VOL
Low-level output voltage
ICC
SN65LVDS9637
MAX
100
IOH = –8 mA
2.4
IOH = –4 mA
2.8
mV
V
10
18
Disabled
0.25
0.5
No load
5.5
10
–2
–10
–20
–1.2
–3
VI = 0
Input current (A or B inputs)
II(OFF)
Power-off input current (A or B inputs)
VCC = 0, VI = 3.6 V
IIH
High-level input current (EN, G, or G inputs)
VIH = 2 V
IIL
Low-level input current (EN, G, or G inputs)
VIL = 0.8 V
IOZ
High-impedance output current
VO = 0 or VCC
VI = 2.4 V
mV
0.4
Enabled, No load
II
(1)
(2)
UNIT
–100
IOL = 8 mA
SN65LVDS32, SN65LVDS3486
Supply current
TYP (1)
6
V
mA
µA
20
µA
10
µA
10
µA
±10
µA
All typical values are at TA = 25°C and with VCC = 3.3 V.
The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the
negative-going differential input voltage threshold only.
SN65LVDSxxxx SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN65LVDS32
SN65LVDS3486
SN65LVDS9637
UNIT
MIN
TYP
MAX
tPLH
Propagation delay time, low-to-high-level output
1.5
2.1
3
ns
tPHL
Propagation delay time, high-to-low-level output
1.5
2.1
3
ns
tsk(p)
Pulse skew (|tPHL - tPLH|)
0
0.4
ns
tsk(o)
Channel-to-channel output skew (1)
0.1
0.3
ns
1
ns
CL = 10 pF, See Figure 3
skew (2)
tsk(pp)
Part-to-part
tr
Output signal rise time, 20% to 80%
0.6
ns
tf
Output signal fall time, 80% to 20%
0.7
ns
tPHZ
Propagation delay time, high-level-to-high-impedance output
6.5
12
ns
tPLZ
Propagation delay time, low-level-to-high-impedance output
5.5
12
ns
tPZH
Propagation delay time, high-impedance-to-high-level output
8
12
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
3
12
ns
(1)
(2)
See Figure 4
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, same temperature, and have identical packages and test circuits.
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SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
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SLLS262N – JULY 1997 – REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
A
Y
VID
B
(VIA + VIB)/2
VIA
VIC
VO
VIB
Figure 2. Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages
8
Resulting Differential
Input Voltage
Resulting Common-Mode
Input Voltage
VIA(V)
VIB(V)
VID(mV)
VIC(V)
1.25
1.15
100
1.2
1.15
1.25
–100
1.2
2.4
2.3
100
2.35
2.3
2.4
–100
2.35
0.1
0
100
0.05
0
0.1
–100
0.05
1.5
0.9
600
1.2
0.9
1.5
–600
1.2
2.4
1.8
600
2.1
1.8
2.4
–600
2.1
0.6
0
600
0.3
0
0.6
–600
0.3
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SLLS262N – JULY 1997 – REVISED MARCH 2004
VID
VIA
CL = 10 pF
VIB
VO
VIA
1.4 V
VIB
1V
VID
0.4 V
0
-0.4 V
tPHL
tPLH
80%
VO
20%
VOH
80%
1.4 V
VOL
20%
tf
tr
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition
rate(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns.
B.
CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Figure 3. Timing Test Circuit and Waveforms
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SLLS262N – JULY 1997 – REVISED MARCH 2004
B
1.2 V
500 Ω
A
Inputs
(see Note A)
G
10 pF
(see Note B)
±
VO
VTEST
G
1,2EN or 3,4EN
VTEST
2.5 V
A
1V
2V
1.4 V
0.8 V
G, 1,2EN,
or 3,4EN
2V
1.4 V
0.8 V
G
tPLZ
tPZL
tPLZ
tPZL
Y
VTEST
2.5 V
1.4 V
VOL + 0.5 V
VOL
0
1.4 V
A
G, 1,2EN,
or 3,4EN
2V
1.4 V
0.8 V
G
2V
1.4 V
0.8 V
tPHZ
tPZH
tPHZ
tPZH
Y
VOH
VOH - 0.5 V
1.4 V
0
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition
rate(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns.
B.
CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Figure 4. Enable- and Disable-Time Test Circuit and Waveforms
10
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SN65LVDS3486, SN65LVDS9637
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SLLS262N – JULY 1997 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS
SN55LVDS32, SN65LVDS32
SUPPLY CURRENT
vs
FREQUENCY
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
Four Receivers, Loaded
Per Figure 3, Switching
Simultaneously
VCC = 3.6 V
VCC = 3.3 V
65
VCC = 3 V
55
45
35
25
15
50
100
150
200
2.7
2.5
VCC = 3 V
VCC = 3.3 V
2.3
VCC = 3.6 V
2.1
1.9
1.7
1.5
−50
f − Frequency − MHz
0
50
TA − Free-Air Temperature − °C
Figure 5.
Figure 6.
100
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
t PHL(D) − High-to-Low Propagation Delay Time − ns
I CC − Supply Current − mA (rms)
75
t PLH(D) − Low-to-High Propagation Delay Time − ns
85
2.7
2.5
2.3
VCC = 3 V
2.1
VCC = 3.3 V
1.9
VCC = 3.6 V
1.7
1.5
−50
0
50
TA − Free-Air Temperature − °C
100
Figure 7.
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SLLS262N – JULY 1997 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
3.5
5.0
2.5
2.0
1.5
1.0
0.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−60
12
VOL − Low-Level Output Voltage − V
VOH − High-Level Output Voltage − V
4.5
3.0
0.0
−50
−40
−30
−20
−10
0
0
10
20
30
40
50
60
IOH − High-Level Output Current − mA
IOL − Low-Level Output Current − mA
Figure 8.
Figure 9.
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80
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SN65LVDS3486, SN65LVDS9637
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SLLS262N – JULY 1997 – REVISED MARCH 2004
APPLICATION INFORMATION
USING AN LVDS RECEIVER WITH RS-422 DATA
Receipt of data from a TIA/EIA-422 line driver can be accomplished using a TIA/EIA-644 line receiver with the
addition of an attenuator circuit. This technique gives the user a high-speed and low-power 422 receiver.
If the ground noise between the transmitter and receiver is not a concern (less than ±1 V), the answer can be as
simple as shown in Figure 10. A resistor divider circuit in front of the LVDS receiver attenuates the 422
differential signal to LVDS levels.
The resistors present a total differential load of 100 Ω to match the characteristic impedance of the transmission
line and to reduce the signal 10:1. The maximum 422 differential output signal, or 6 V, is reduced to 600 mV. The
high input impedance of the LVDS receiver prevents input bias offsets and maintains a greater than 200-mV
differential input voltage threshold at the inputs to the divider. This circuit is used in front of each LVDS channel
that also receives 422 signals.
R1
45.3 Ω
’LVDS32
R3
5.11 Ω
A
R4
5.11 Ω
B
Y
R2
45.3 Ω
NOTE: The components used were standard values. (1) R1, R2 = NRC12F45R3TR, NIC components, 45.3 Ω, 1/8 W, 1%,
1206 package (2) R3, R4 = NRC12F5R11TR, NIC components, 5.11 Ω, 1/8 W, 1%, 1206 package (3) The resistor
values do not need to be 1% tolerance. However, it can be difficult locating a supplier of resistors having values less
than 100 Ω in stock and readily available. The user may find other suppliers with comparable parts having tolerances
of 5% or even 10%. These parts are adequate for use in this circuit.
Figure 10. RS-422 Data Input to an LVDS Receiver Under Low Ground-Noise Conditions
If ground noise between the RS-422 driver and LVDS receiver is a concern, the common-mode voltage must be
attenuated. The circuit must then be modified to connect the node between R3 and R4 to the LVDS receiver
ground. This modification to the circuit increases the common-mode voltage from ±1 V to greater than ±4.5 V.
The devices are generally used as building blocks for high-speed point-to-point data transmission where ground
differences are less than 1 V. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers
approach ECL speeds without the power and dual-supply requirements.
Submit Documentation Feedback
13
SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
www.ti.com
SLLS262N – JULY 1997 – REVISED MARCH 2004
APPLICATION INFORMATION (continued)
TRANSMISSION DISTANCE
vs
SIGNALING RATE
Transmission Distance − m
100
30% Jitter
(see Note A)
10
5% Jitter
(see Note A)
1
24 AWG UTP 96 Ω
(PVC Dielectric)
0.1
10
100
1000
Signaling Rate − Mbps
A.
This parameter is the percentage of distortion of the unit interval (UI) with a pseudorandom data pattern.
Figure 11. Typical Transmission Distance Versus Signaling Rate
1
1B
VCC
16
0.1 µF
(see Note A)
100 Ω
2
3
VCC 4
5
6
1A
4B
4A
G
4Y
2Y
G
2A
3Y
2B
3A
GND
3B
0.001 µF
(see Note A)
15
1Y
100 Ω
7
3.3 V
14
100 Ω
(see Note B)
13
12
11
See Note C
10
100 Ω
8
9
A.
Place a 0.1-µF and a 0.001-µF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between VCC
and the ground plane. The capacitors should be located as close as possible to the device terminals.
B.
The termination resistance value should match the nominal characteristic impedance of the transmission media with
±10%.
C.
Unused enable inputs should be tied to VCC or GND as appropriate.
Figure 12. Typical Application Circuit Schematic
14
Submit Documentation Feedback
SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
www.ti.com
SLLS262N – JULY 1997 – REVISED MARCH 2004
APPLICATION INFORMATION
1/4 ’LVDS31
Strb/Data_TX
TpBias on
Twisted-Pair A
Strb/Data_Enable
TP
55 Ω
’LVDS32
5 kΩ
Data/Strobe
55 Ω
3.3 V
TP
20 kΩ
500 Ω
VG on
Twisted-Pair B
1 Arb_RX
500 Ω
20 kΩ
3.3 V
500 Ω
20 kΩ
2 Arb_RX
500 Ω
20 kΩ
3.3 V
7 kΩ
Twisted-Pair B Only
7 kΩ
10 kΩ
Port_Status
3.3 kΩ
A.
Resistors are leadless, thick film (0603), 5% tolerance.
B.
Decoupling capacitance is not shown but recommended.
C.
VCC is 3 V to 3.6 V.
D.
The differential output voltage of the 'LVDS31 can exceed that allowed by IEEE1394.
Figure 13. 100-Mbps IEEE 1394 Transceiver
FAIL-SAFE
One of the most common problems with differential signaling applications is how the system responds when no
differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers in that
its output logic state can be indeterminate when the differential input voltage is between –100 mV and100 mV if it
is within its recommended input common-mode voltage range. However, TI LVDS receivers handle the
open-input circuit situation differently.
Submit Documentation Feedback
15
SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
www.ti.com
SLLS262N – JULY 1997 – REVISED MARCH 2004
APPLICATION INFORMATION (continued)
Open-input circuit means that there is little or no input current to the receiver from the data line itself. This could
be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS
receiver pulls each line of the signal pair to near VCC through 300-kΩ resistors (see Figure 14). The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high level, regardless of the differential input voltage.
VCC
300 kΩ
300 kΩ
A
Rt
Y
B
VIT ≈ 2.3 V
Figure 14. Open-Circuit Fail-Safe of LVDS Receiver
It is only under these conditions that the output of the receiver is valid with less than a 100-mV differential input
voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it
is connected as shown in Figure 14. Other termination circuits may allow a dc current to ground that could defeat
the pullup currents from the receiver and the fail-safe feature.
0.01 µF
1
VCC
16
0.1 µF
(see Note A)
1B
100 Ω
2
3
VCC 4
5
6
1A
4B
2Y
4Y
G
2A
100 Ω
7
4A
2B
3Y
3A
5V
1N645
(two places)
15
1Y
G
≈3.6 V
14
100 Ω
(see Note B)
13
12
11
See Note C
10
100 Ω
8
GND
3B
9
A.
Place a 0.1-µF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground
plane. The capacitor should be located as close as possible to the device terminals.
B.
The termination resistance value should match the nominal characteristic impedance of the transmission media with
±10%.
C.
Unused enable inputs should be tied to VCC or GND, as appropriate.
Figure 15. Operation With 5-V Supply
16
Submit Documentation Feedback
SN55LVDS32, SN65LVDS32
SN65LVDS3486, SN65LVDS9637
www.ti.com
SLLS262N – JULY 1997 – REVISED MARCH 2004
APPLICATION INFORMATION (continued)
RELATED INFORMATION
IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for
more information.
For
•
•
•
•
•
•
more application guidelines, see the following documents:
Low-Voltage Differential Signaling Design Notes (SLLA014)
Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
Reducing EMI With LVDS (SLLA030)
Slew Rate Control of LVDS Circuits (SLLA034)
Using an LVDS Receiver With TIA/EIA-422 Data (SLLA031)
Low Voltage Differential Signaling (LVDS) EVM (SLLA033)
Submit Documentation Feedback
17
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
5962-9762201Q2A
ACTIVE
LCCC
FK
20
1
TBD
5962-9762201QEA
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
5962-9762201QFA
ACTIVE
CFP
W
16
1
TBD
A42 SNPB
N / A for Pkg Type
5962-9762201VFA
ACTIVE
CFP
W
16
1
TBD
A42 SNPB
N / A for Pkg Type
5962-9762202Q2A
ACTIVE
LCCC
FK
20
1
TBD
SN55LVDS32W
ACTIVE
CFP
W
16
1
TBD
A42 SNPB
SN65LVDS32D
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32DG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32DR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32DRG4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32NSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32NSRG4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32PWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32PWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32PWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS3486D
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS3486DG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS3486DR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS3486DRG4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637DGK
ACTIVE
MSOP
DGK
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637DGKG4
ACTIVE
MSOP
DGK
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637DGKR
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637DGKRG4
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637DGN
ACTIVE
MSOPPower
PAD
DGN
8
CU NIPDAU
Level-1-260C-UNLIM
80
Addendum-Page 1
Green (RoHS &
no Sb/Br)
POST-PLATE N / A for Pkg Type
POST-PLATE N / A for Pkg Type
N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2006
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65LVDS9637DGNG4
ACTIVE
MSOPPower
PAD
DGN
8
SN65LVDS9637DGNR
ACTIVE
MSOPPower
PAD
DGN
SN65LVDS9637DGNRG4
ACTIVE
MSOPPower
PAD
SN65LVDS9637DR
ACTIVE
SN65LVDS9637DRG4
80
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ55LVDS32FK
ACTIVE
LCCC
FK
20
1
TBD
SNJ55LVDS32J
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
SNJ55LVDS32W
ACTIVE
CFP
W
16
1
TBD
A42 SNPB
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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