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SLES076A − MARCH 2003 − REVISED JANUARY 2004
FEATURES
D 24-Bit Resolution
D Analog Performance:
− Dynamic Range: 113 dB
− THD+N: 0.001%
− Full-Scale Output: 2.1 V rms (at
Postamplifier)
D Differential Voltage Output: 3.2 V p-p
D 8× Oversampling Digital Filter:
− Stop-Band Attenuation: –82 dB
− Pass-Band Ripple: ±0.002 dB
D Sampling Frequency: 10 kHz to 200 kHz
D System Clock: 128, 192, 256, 384, 512, or
768 fS With Autodetect
D Accepts 16-, 20-, and 24-Bit Audio Data
D Data Formats: Standard, I2S, and
Left-Justified
D
D
D
D
Digital De-Emphasis
Soft Mute
Zero Flags for Each Output
Dual Supply Operation:
− 5-V Analog, 3.3-V Digital
D 5-V Tolerant Digital Inputs
D Small 28-Lead SSOP Package, Lead-Free
Product
APPLICATIONS
D A/V Receivers
D DVD Players
D Musical Instruments
D HDTV Receivers
D Car Audio Systems
D Digital Multitrack Recorders
D Other Applications Requiring 24-Bit Audio
DESCRIPTION
The PCM1793 is a monolithic CMOS integrated circuit that
includes stereo digital-to-analog converters and support
circuitry in a small 28-lead SSOP package. The data
converters use TI’s advanced segment DAC architecture
to achieve excellent dynamic performance and improved
tolerance to clock jitter. The PCM1793 provides balanced
voltage outputs, allowing the user to optimize analog
performance externally. Sampling rates up to 200 kHz are
supported.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE CODE
OPERATION
TEMPERATURE
RANGE
PACKAGE
MARKING
PCM1793DB
28-lead SSOP
28DB
−25°C to 85°C
PCM1793
ORDERING
NUMBER
TRANSPORT
MEDIA
PCM1793DB
Tube
PCM1793DBR
Tape and reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
PCM1793
VCCF, VCCL, VCCC, VCCR
VDD
Supply voltage
−0.3 V to 6.5 V
−0.3 V to 4 V
±0.1 V
Supply voltage differences: VCCF, VCCL, VCCC, VCCR
±0.1 V
Ground voltage differences: AGNDF, AGNDL, AGNDC, AGNDR, DGND
LRCK, DATA, BCK, SCK, DEMP0, DEMP1, FMT0, FMT1, FMT2, RST, MUTE
Digital input voltage
–0.3 V to 6.5 V
ZEROL, ZEROR
–0.3 V to (VDD + 0.3 V) < 4 V
–0.3 V to (VCC + 0.3 V) < 6.5 V
Analog input voltage
±10 mA
Input current (any pins except supplies)
Ambient temperature under bias
–40°C to 125°C
Storage temperature
–55°C to 150°C
Junction temperature
150°C
Lead temperature (soldering)
260°C, 5 s
Package temperature (IR reflow, peak)
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted
PCM1793DB
PARAMETER
TEST CONDITIONS
MIN
TYP
RESOLUTION
MAX
24
UNIT
Bits
DATA FORMAT
fS
Audio data interface format
Standard, I2S, left justified
Audio data bit length
16-, 20-, 24-bit selectable
Audio data format
MSB first, 2s complement
Sampling frequency
10
System clock frequency
200
kHz
128, 192, 256, 384, 512, 768 fS
DIGITAL INPUT/OUTPUT
Logic family
TTL compatible
VIH
VIL
Input logic level
IIH
IIL
Input logic current
VIN = VDD
VIN = 0 V
VOH
VOL
Output logic level
IOH = −2 mA
IOL = 2 mA
2
2
0.8
10
–10
VDC
µA
2.4
0.4
VDC
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted
PCM1793DB
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
MAX
DYNAMIC PERFORMANCE (1)
THD+N at VOUT = 0 dB
fS = 44.1 kHz
fS = 96 kHz
fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
Dynamic range
110
113
113
EIAJ, A-weighted, fS = 192 kHz
113
110
113
EIAJ, A-weighted, fS = 192 kHz
113
Channel separation
Level linearity error
fS = 192 kHz
VOUT = −120 dB
106
dB
113
EIAJ, A-weighted, fS = 96 kHz
fS = 44.1 kHz
fS = 96 kHz
0.002%
0.003%
EIAJ, A-weighted, fS = 96 kHz
EIAJ, A-weighted, fS = 44.1 kHz
Signal-to-noise ratio
0.001%
0.0015%
dB
110
110
dB
109
±1
dB
ANALOG OUTPUT
Gain error
–8
±3
8
% of FSR
Gain mismatch, channel-to-channel
–3
±0.5
3
% of FSR
–2
±0.5
2
% of FSR
Bipolar zero error
At BPZ
Differential output voltage (2)
Bipolar zero voltage (2)
Full scale (0 dB)
3.2
At BPZ
1.4
Load impedance (2)
R1 = R2
V p-p
V
1.7
kΩ
DIGITAL FILTER PERFORMANCE
±0.1
De-emphasis error
Pass band
±0.002 dB
–3 dB
Stop band
0.49 fS
0.546 fS
±0.002
Pass-band ripple
Stop-band attenuation
dB
0.454 fS
dB
Stop band = 0.546 fS
–75
dB
Stop band = 0.567 fS
–82
dB
Delay time
29/fS
s
(1) Dynamic performance and DC accuracy are specified at the output of the postamplifier as shown in Figure 28. Analog performance specifications
are measured using the System Twot Cascade audio measurement system by Audio Precisiont in the averaging mode. At all sampling
frequency operations, measurement bandwidth is limited with a 20-kHz AES17 filter.
(2) These parameters are defined at the PCM1793 output pin. Load impedance, R1 and R2, are input resistors of the postamplifier. These are defined
as dc loads.
Audio Precision and System Two are trademarks of Audio Precision, Inc.
Other trademarks are the property of their respective owners.
3
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS (Continued)
all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted
PCM1793DB
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
MAX
POWER SUPPLY REQUIREMENTS
VDD
VCC
Voltage range
IDD
Supply current (1)
ICC
3
3.3
3.6
4.5
5
5.5
6.5
8
fS = 44.1 kHz
fS = 96 kHz
Supply current (1)
Power dissipation (1)
13.5
fS = 192 kHz
fS = 44.1 kHz
28
fS = 96 kHz
fS = 192 kHz
15
14
VDC
mA
16
mA
16
fS = 44.1 kHz
fS = 96 kHz
120
90
fS = 192 kHz
170
110
mW
TEMPERATURE RANGE
Operation temperature
–25
θJA
Thermal resistance
(1) Input is BPZ data.
28-pin SSOP
PIN ASSIGNMENTS
PCM1793
(TOP VIEW)
LRCK
BCK
DATA
MUTE
SCK
RST
VDD
DGND
AGNDF
VCCR
AGNDR
VOUTR−
VOUTR+
VCOM
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
85
100
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FMT2
FMT1
FMT0
DEMP1
DEMP0
ZEROL
ZEROR
VCCF
VCCL
AGNDL
VOUTL−
VOUTL+
AGNDC
VCCC
°C
°C/W
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
Terminal Functions
TERMINAL
NAME
PIN
I/O
DESCRIPTIONS
AGNDC
16
−
Analog ground (internal bias and current DAC)
AGNDF
9
−
Analog ground (DACFF)
AGNDL
19
−
Analog ground (L-channel I/V)
AGNDR
11
−
BCK
2
I
Analog ground (R-channel I/V)
Bit clock input (1)
DATA
3
I
DEMP0
24
I
Serial audio data input (1)
De-emphasis control 0 (1)
DEMP1
25
I
De-emphasis control 1 (1)
DGND
8
−
Digital ground
FMT0
26
I
FMT1
27
I
Audio data format select 0 (1)
Audio data format select 1 (1)
FMT2
28
I
LRCK
1
I
MUTE
4
I
RST
6
I
Analog output mute control (1)
Reset(1)
SCK
5
I
System clock input(1)
VCCC
VCCF
15
−
Analog power supply (internal bias and current DAC), 5 V
21
−
Analog power supply (DACFF), 5 V
VCCL
VCCR
20
−
Analog power supply (L-channel I/V), 5 V
10
−
Analog power supply (R-channel I/V), 5 V
VCOM
VDD
14
−
Internal bias decoupling pin
7
−
Digital power supply, 3.3 V
VOUTL+
VOUTL−
17
O
L-channel analog voltage output +
18
O
L-channel analog voltage output −
VOUTR+
VOUTR−
13
O
R-channel analog voltage output +
12
O
R-channel analog voltage output −
ZEROL
23
O
Zero flag for L-channel
ZEROR
22
O
(1) Schmitt-trigger input, 5-V tolerant
Audio data format select 2 (1)
Left and right clock (fS) input (1)
Zero flag for R-channel
5
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
FUNCTIONAL BLOCK DIAGRAM
LRCK
MUTE
RST
FMT2
Function
Control
I/F
Bias
and
Vref
DEMP0
VOUTR+
VOUTR−
D/S and Filter
VCCL
AGNDC
VCCF
AGNDF
Power Supply
VDD
SCK
Zero
Detect
System
Clock
Manager
DGND
ZEROL
6
VCOM
Current
Segment
DAC
and
I/V Buffer
DEMP1
ZEROR
VOUTL+
AGNDL
FMT0
Advanced
Segment
DAC
Modulator
VCCR
FMT1
VOUTL−
D/S and Filter
8
Oversampling
Digital
Filter
and
Function
Control
AGNDR
DATA
Current
Segment
DAC
and
I/V Buffer
Audio
Data Input
I/F
VCCC
BCK
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
TYPICAL PERFORMANCE CURVES
DIGITAL FILTER
Digital Filter Response
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
3
0.003
−20
2
0.002
Amplitude − dB
Amplitude − dB
−40
−60
−80
−100
1
0.001
0
−1
−0.001
−120
−2
−0.002
−140
−160
0
1
2
3
−3
−0.003
0.0
4
0.1
Frequency [× fS]
0.2
0.3
0.4
0.5
Frequency [× fS]
Figure 1. Frequency Response, Sharp Rolloff
Figure 2. Pass-Band Ripple, Sharp Rolloff
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
0
−2
−20
−4
−6
Amplitude − dB
Amplitude − dB
−40
−60
−80
−8
−10
−12
−14
−100
−16
−120
−18
−140
0
1
2
3
4
Frequency [× fS]
Figure 3. Frequency Response, Slow Rolloff
−20
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency [× fS]
Figure 4. Transition Characteristics, Slow Rolloff
7
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
De-Emphasis Filter
DE-EMPHASIS LEVEL
vs
FREQUENCY
DE-EMPHASIS ERROR
vs
FREQUENCY
0
0.5
fS = 32 kHz
−1
0.3
De-emphasis Error − dB
−2
De-emphasis Level − dB
fS = 32 kHz
0.4
−3
−4
−5
−6
−7
0.2
0.1
−0.0
0.0
−0.1
−0.2
−8
−0.3
−9
−0.4
−10
−0.5
0
2
4
6
8
10
12
14
0
2
4
f − Frequency − kHz
Figure 5
10
12
14
DE-EMPHASIS ERROR
vs
FREQUENCY
0
0.5
fS = 44.1 kHz
−1
fS = 44.1 kHz
0.4
0.3
De-emphasis Error − dB
−2
De-emphasis Level − dB
8
Figure 6
DE-EMPHASIS LEVEL
vs
FREQUENCY
−3
−4
−5
−6
−7
0.2
0.1
−0.0
0.0
−0.1
−0.2
−8
−0.3
−9
−0.4
−10
−0.5
0
2
4
6
8
10
12
14
f − Frequency − kHz
Figure 7
8
6
f − Frequency − kHz
16
18
20
0
2
4
6
8
10
12
14
f − Frequency − kHz
Figure 8
16
18
20
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
De-Emphasis Filter (Continued)
DE-EMPHASIS LEVEL
vs
FREQUENCY
DE-EMPHASIS ERROR
vs
FREQUENCY
0
0.5
fS = 48 kHz
−1
0.3
De-emphasis Error − dB
−2
De-emphasis Level − dB
fS = 48 kHz
0.4
−3
−4
−5
−6
−7
0.2
0.1
−0.0
0.0
−0.1
−0.2
−8
−0.3
−9
−0.4
−10
−0.5
0
2
4
6
8
10
12
14
f − Frequency − kHz
Figure 9
16
18
20
22
0
2
4
6
8
10
12
14
16
18
20
22
f − Frequency − kHz
Figure 10
9
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
ANALOG DYNAMIC PERFORMANCE
Supply Voltage Characteristics
TOTAL HARMONIC DISTORTION + NOISE
vs
SUPPLY VOLTAGE
DYNAMIC RANGE
vs
SUPPLY VOLTAGE
118
116
fS = 192 kHz
Dynamic Range − dB
THD+N − Total Harmonic Distortion + Noise − %
0.01
fS = 96 kHz
0.001
fS = 44.1 kHz
fS = 44.1 kHz
112
4.75 5.00 5.25
108
4.00 4.25 4.50
5.50 5.75 6.00
VCC − Supply Voltage − V
4.75 5.00 5.25
5.50 5.75 6.00
VCC − Supply Voltage − V
Figure 11
Figure 12
SIGNAL-to-NOISE RATIO
vs
SUPPLY VOLTAGE
CHANNEL SEPARATION
vs
SUPPLY VOLTAGE
118
114
112
116
114
fS = 96 kHz
112
fS = 44.1 kHz
fS = 192 kHz
110
Channel Separation − dB
SNR − Signal-to-Noise Ratio − dB
fS = 192 kHz
110
0.0001
4.00 4.25 4.50
fS = 44.1 kHz
110
fS = 96 kHz
fS = 192 kHz
108
106
104
108
4.00 4.25 4.50
4.75 5.00 5.25
5.50 5.75 6.00
VCC − Supply Voltage − V
Figure 13
NOTE: PCM mode, TA = 25°C, VDD = 3.3 V.
10
fS = 96 kHz
114
102
4.00 4.25 4.50
4.75 5.00 5.25
5.50 5.75 6.00
VCC − Supply Voltage − V
Figure 14
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
Temperature Characteristics
TOTAL HARMONIC DISTORTION + NOISE
vs
FREE-AIR TEMPERATURE
DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
118
116
fS = 192 kHz
Dynamic Range − dB
THD+N − Total Harmonic Distortion + Noise − %
0.01
fS = 96 kHz
0.001
fS = 44.1 kHz
fS = 96 kHz
fS = 44.1 kHz
114
fS = 192 kHz
112
110
0.0001
−50
−25
0
25
50
75
108
−50
100
−25
Figure 15
116
112
Channel Separation − dB
SNR − Signal-to-Noise Ratio − dB
114
fS = 44.1 kHz
fS = 96 kHz
fS = 192 kHz
110
108
−50
50
75
100
CHANNEL SEPARATION
vs
FREE-AIR TEMPERATURE
118
112
25
Figure 16
SIGNAL-to-NOISE RATIO
vs
FREE-AIR TEMPERATURE
114
0
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
fS = 44.1 kHz
110
fS = 96 kHz
fS = 192 kHz
108
106
−25
0
25
50
TA − Free-Air Temperature − °C
Figure 17
75
100
104
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 18
NOTE: PCM mode, VDD = 3.3 V, VCC = 5 V.
11
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
AMPLITUDE vs FREQUENCY
−50
−60
−60
−70
−70
−80
−80
−90
−90
Amplitude − dB
Amplitude − dB
AMPLITUDE vs FREQUENCY
−50
−100
−110
−120
−100
−110
−120
−130
−130
−140
−140
−150
−150
−160
−160
0
5
10
15
20
0
10
20
30
f − Frequency − kHz
Figure 19. −60-dB Output Spectrum, BW = 20 kHz
TOTAL HARMONIC DISTORTION + NOISE
vs
INPUT LEVEL
THD+N − Total Harmonic Distortion + Noise − %
100
10
1
0.1
0.01
0.001
−80
−60
−40
−20
0
Input Level − dBFS
Figure 21. THD+N vs Input Level, PCM Mode
NOTE: PCM mode, fS = 44.1 kHz, TA = 25°C, VDD = 3.3 V, VCC = 5 V.
12
50
60
70
80
90 100
Figure 20. −60-dB Output Spectrum, BW = 100 kHz
NOTE: PCM mode, fS = 44.1 kHz, 32768 points, 8 average, TA = 25°C, VDD = 3.3 V, VCC = 5 V.
0.0001
−100
40
f − Frequency − kHz
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
The PCM1793 requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input (pin 5). The PCM1793 has a system clock detection circuit
that automatically senses which frequency the system clock is operating. Table 1 shows examples of system clock
frequencies for common audio sampling rates.
Figure 22 shows the timing requirements for the system clock input. For optimal performance, it is important to use
a clock source with low phase jitter and noise. One of the Texas Instruments’ PLL1700 family of multiclock generators
is an excellent choice for providing the PCM1793 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SYSTEM CLOCK FREQUENCY (FSCK) (MHZ)
SAMPLING FREQUENCY
128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
32 kHz
4.096
6.144
8.192
12.288
16.384
24.576
44.1 kHz
5.6488
8.4672
11.2896
16.9344
22.5792
33.8688
48 kHz
6.144
9.216
12.288
18.432
24.576
36.864
96 kHz
12.288
18.432
24.576
36.864
192 kHz
24.576
36.864
49.152
73.728
49.152
(1)
73.728
(1)
(1) This system clock rate is not supported for the given sampling frequency.
t(SCKH)
H
2.0 V
System Clock (SCK)
0.8 V
L
t(SCY)
t(SCKL)
PARAMETERS
MIN
MAX
UNITS
t(SCY) System clock pulse cycle time
t(SCKH) System clock pulse duration, HIGH
13
ns
5
ns
t(SCKL) System clock pulse duration, LOW
5
ns
Figure 22. System Clock Input Timing
Power-On and External Reset Functions
The PCM1793 includes a power-on reset function. Figure 23 shows the operation of this function. With VDD > 2 V,
the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time
VDD > 2 V.
The PCM1793 also includes an external reset capability using the RST input (pin 6). This allows an external controller
or master reset circuit to force the PCM1793 to initialize to its default reset state.
Figure 24 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The
RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock
periods. The external reset is especially useful in applications where there is a delay between the PCM1793 power
up and system clock activation.
13
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
VDD
2.4 V (Max)
2.0 V (Typ)
1.6 V (Min)
Reset
Reset Removal
Internal Reset
1024 System Clocks
System Clock
Figure 23. Power-On Reset Timing
RST (Pin 6)
1.4 V
t(RST)
Reset
Reset Removal
Internal Reset
1024 System Clocks
System Clock
t(RST)
PARAMETERS
MIN
Reset pulse duration, LOW
20
Figure 24. External Reset Timing
14
MAX
UNITS
ns
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AUDIO DATA INTERFACE
Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes LRCK (pin 1), BCK (pin 2), and DATA (pin 3). BCK is the
serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio
interface. Serial data is clocked into the PCM1793 on the rising edge of BCK. LRCK is the serial audio left/right word
clock.
The PCM1793 requires the synchronization of LRCK and the system clock, but does not need a specific phase
relation between LRCK and the system clock.
If the relationship between LRCK and the system clock changes more than ±6 BCK, internal operation is initialized
within 1/fS and the analog outputs are forced to the bipolar zero level until resynchronization between LRCK and the
system clock is completed.
PCM Audio Data Formats and Timing
The PCM1793 supports industry-standard audio data formats, including standard right-justified, I2S, and
left-justified. The data formats are shown in Figure 26. Data formats are selected using the format bits,
FMT2 (pin 28), FMT1 (pin27), and FMT0 (pin26) as shown in Table 2. All formats require binary 2s complement,
MSB-first audio data. Figure 25 shows a detailed timing diagram for the serial audio interface.
Table 2. Audio Data Format Selection
FMT2
PIN 28
FMT1
PIN 27
FMT0
PIN 26
FORMAT
LOW
LOW
LOW
16-bit standard format, right-justified
LOW
LOW
HIGH
20-bit standard format, right-justified
LOW
HIGH
LOW
24-bit standard format, right-justified
LOW
HIGH
HIGH
HIGH
LOW
LOW
24-bit MSB-first, left-justified format
16-bit I2S format
HIGH
LOW
HIGH
24-bit I2S format
HIGH
HIGH
LOW
Reserved
HIGH
HIGH
HIGH
Reserved
15
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
1.4 V
LRCK
t(BCH)
t(BCL)
t(LB)
1.4 V
BCK
t(BCY)
t(BL)
1.4 V
DATA
t(DS)
t(DH)
PARAMETERS
MIN
UNITS
BCK pulse cycle time
70
ns
BCK pulse duration, LOW
30
ns
t(BCH)
t(BL)
BCK pulse duration, HIGH
30
ns
BCK rising edge to LRCK edge
10
ns
t(LB)
t(DS)
LRCK edge to BCK rising edge
10
ns
DATA setup time
10
ns
t(DH)
—
DATA hold time
10
ns
LRCK clock duty
50% ± 2 bit clocks
Figure 25. Timing of Audio Interface
16
MAX
t(BCY)
t(BCL)
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
(1) Standard Data Format (Right Justified); L-Channel = HIGH, R-Channel = LOW
1/fS
LRCK
R-Channel
L-Channel
BCK
Audio Data Word = 16-Bit
DATA
14 15 16
1
2
MSB
15 16
1
2
15 16
LSB
Audio Data Word = 20-Bit
DATA
18 19 20
1
2
19 20
1
2
19 20
LSB
MSB
Audio Data Word = 24-Bit
DATA
22 23 24
1
2
23 24
1
2
23 24
LSB
MSB
(2) Left Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS
LRCK
R-Channel
L-Channel
BCK
Audio Data Word = 24-Bit
DATA
1
2
23 24
1
2
23 24
1
2
LSB
MSB
(3) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
1/fS
LRCK
L-Channel
R-Channel
BCK
Audio Data Word = 16-Bit
DATA
1
2
15 16
MSB
1
2
1
2
15 16
1
2
1
2
LSB
Audio Data Word = 24-Bit
DATA
1
2
23 24
MSB
23 24
LSB
Figure 26. Audio Data Input Formats
17
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
FUNCTION DESCRIPTIONS
Zero Detect
When the PCM1793 detects that the audio input data in the L-channel or R-channel is continuously zero for 1024
fS, the PCM1793 sets ZEROL (pin 23) or ZEROR (pin 22) to HIGH.
Soft Mute
The PCM1793 supports mute operation. When MUTE (pin 4) is set to HIGH, both analog outputs are transitioned
to the bipolar zero level in −0.5-dB steps with a transition speed of 1/fS per step. This system provides pop-free muting
of the DAC output.
De-Emphasis
The PCM1793 has de-emphasis filters for sampling frequencies of 32 kHz, 44.1 kHz, and 48 kHz. DEMP1 (pin 25)
and DEMP0 (pin 24) select the sampling frequency for which de-emphasis filtering is performed, as shown in Table 3.
Table 3. De-Emphasis Control
18
DEMP1
PIN 25
DEMP0
PIN 24
DE-EMPHASIS FUNCTION
LOW
LOW
Disabled
LOW
HIGH
48 kHz
HIGH
LOW
44.1 kHz
HIGH
HIGH
32 kHz
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
TYPICAL CONNECTION DIAGRAM
L/R Clock (fS)
1
LRCK
FMT2
Bit Clock
2
BCK
FMT1 27
Audio Data
3
DATA
FMT0 26
4
MUTE
DEMP1
5
SCK
DEMP0 24
6
RST
ZEROL
23
7
VDD
ZEROR
22
System Clock
3.3 V
+
25
Controller
PCM1793
8
DGND
VCCF
21
9
AGNDF
VCCL
20
AGNDL
19
10 VCCR
Analog
Output Stage
(See Figure 28)
28
11 AGNDR
VOUTL− 18
12 VOUTR−
VOUTL+
17
13 VOUTR+
AGNDC
16
VCCC
15
14 VCOM
Analog
Output Stage
(See Figure 28)
Figure 27. Typical Application Circuit
19
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
APPLICATION INFORMATION
ANALOG OUTPUTS
1
LRCK
FMT2
2
BCK
FMT1 27
3
DATA
FMT0 26
4
MUTE
DEMP1
5
SCK
DEMP0 24
6
RST
ZEROL
23
7
VDD
ZEROR
22
28
25
PCM1793
8
DGND
VCCF
21
9
AGNDF
VCCL
20
AGNDL
19
10 VCCR
11 AGNDR
VOUTL− 18
12 VOUTR−
VOUTL+
17
13 VOUTR+
AGNDC
16
VCCC
15
14 VCOM
+
0.1 µF
+
5V
10 µF
R4L
R2L
R6L
C3L
C1L
R1L
−
R5L
R3L
VOUT
L-Channel
+
C2L
1 µF
R4R
C3R
R6R
R2R
C1R
R1R
−
R5R
R3R
+
VOUT
R-Channel
C2R
NOTE: Example R and C values for fC = 77 kHz – R1, R2: 1.8 kΩ, R3,R4: 3.3 kΩ, R5,R6: 680 Ω, C1: 1800 pF, C2, C3: 560 pF.
Figure 28. Typical Application for Analog Output Stage
Analog Output Level and LPF
The signal level of the DAC differential-voltage output {(VOUTL+)–(VOUTL–), (VOUTR+)–(VOUTR–)} is 3.2 Vp-p
at 0 dB (full scale). The voltage output of the LPF is given by following equation:
VOUT = 3.2 Vp-p × (Rf /Ri)
Here, Rf is the feedback resistor in the LPF, and R3 = R4 in a typical application circuit. Ri is the input resistor
in the LPF, and R1 = R2 in a typical application circuit.
Op Amp for LPF
An OPA2134 or 5532 type op amp is recommended for the LPF circuit to obtain the specified audio
performance. Dynamic performance such as gain bandwidth, settling time, and slew rate of the op amp largely
determines the audio dynamic performance of the LPF section. The input noise specification of the op amp
should be considered to obtain a 113-dB S/N ratio.
20
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
Analog Gain of Balanced Amplifier
The DAC voltage outputs are followed by balanced amplifier stages, which sum the differential signals for each
channel, creating a single-ended voltage output. In addition, the balanced amplifiers provide a third-order
low-pass filter function, which band limits the audio output signal. The cutoff frequency and gain are determined
by external R and C component values. In this case, the cutoff frequency is 77 kHz with a gain of 1.83. The
output voltage for each channel is 5.9 Vp-p, or 2.1 V rms.
THEORY OF OPERATION
Upper
6 Bit
ICOB
Decoder
0−62
Level
0−66
Digital
Input
24 Bit
8 fS
MSB
and
Lower 18 Bit
3rd-Order
5-Level
Sigma-Delta
Advanced
DWA
Current
Segment
DAC
I/V
Converter
Analog
Voltage
Output
0−4
Level
Figure 29. Advanced Segment DAC With I/V Converter
The PCM1793 uses TI’s advanced segment DAC architecture to achieve excellent dynamic performance and
improved tolerance to clock jitter. The PCM1793 provides balanced voltage outputs.
Digital input data via the digital filter is separated into 6 upper bits and 18 lower bits. The 6 upper bits are converted
to inverted complementary offset binary (ICOB) code. The lower 18 bits, associated with the MSB, are processed
by a five-level third-order delta-sigma modulator operated at 64 fS by default. The 1 level of the modulator is equivalent
to the 1 LSB of the ICOB code converter. The data groups processed in the ICOB converter and third-order
delta-sigma modulator are summed together to an up-to-66-level digital code, and then processed by data-weighted
averaging (DWA) to reduce the noise produced by element mismatch. The data of up to 66 levels from the DWA is
converted to an analog output in the differential-current segment section.
This architecture has overcome the various drawbacks of conventional multibit processing and also achieves
excellent dynamic performance.
21
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
CONSIDERATIONS FOR APPLICATION CIRCUITS
PCB Layout Guidelines
A typical PCB floor plan for the PCM1793 is shown in Figure 30. A ground plane is recommended, with the analog
and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1793 must be
oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections to the digital
audio interface and control signals originating from the digital section of the board. Separate power supplies are
recommended for the digital and analog sections of the board. This prevents the switching noise present on the digital
supply from contaminating the analog power supply and degrading the dynamic performance of the D/A converters.
In cases where a common 5-V supply would be used for the analog and digital sections, an inductance (RF choke,
ferrite bead) must be placed between the analog and digital 5-V supply connections to avoid coupling of the digital
switching noise into the analog circuitry. Figure 31 shows the recommended approach for single-supply applications.
Digital Power
+VD
DGND
Analog Power
AGND +5VA
+VS
−VS
REG
VCC
Digital Logic
and
Audio
Processor
VDD
DGND
PCM1793
Output
Circuits
Digital
Ground
AGND
Digital Section
Analog Section
Return Path for Digital Signals
Figure 30. Recommended PCB Layout
22
Analog
Ground
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
Power Supplies
RF Choke or Ferrite Bead
+5V AGND
+VS
−VS
REG
VCC
VDD
VDD
DGND
Output
Circuits
PCM1793
AGND
Digital Section
Analog Section
Common
Ground
Figure 31. Single-Supply PCB Layout
Bypass and Decoupling Capacitor Requirements
Various-sized decoupling capacitors can be used, with no special tolerances being required. All capacitors must be
located as close as possible to the appropriate pins of the PCM1793 to reduce noise pickup from surrounding circuitry.
Aluminum electrolytic capacitors that are designed for hi-fi audio applications are recommended for larger values,
while metal film or monolithic ceramic capacitors are used for smaller values.
Post-LPF Design
By proper choice of the op amp and resistors used in the post-LPF circuit, excellent performance of the PCM1793
should be achieved. To obtain 0.001% THD+N, 113 dB signal-to-noise-ratio audio performance, the THD+N and input
noise performance of the op amp must be considered. This is because the input noise of the op amp contributes
directly to the output noise level of the application. The VOUT pins of the PCM1793 and the input resistor of the
post-LPF circuit must be connected as closely as possible.
Out-of-band noise level and attenuated sampling spectrum level are much lower than for typical delta-sigma type
DACs due to the combination of a high-performance digital filter and advanced segment DAC architecture. The use
of a second-order or third-order post-LPF is recommended for the post-LPF of the PCM1793. The cutoff frequency
of the post-LPF depends on the application. For example, there are many sampling-rate operations such as
fS = 44.1 kHz on CDDA, fS = 96 kHz on DVD-M, fS = 192 kHz on DVD-A, fS = 64 fS on DSD (SACD).
23
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SLES076A − MARCH 2003 − REVISED JANUARY 2004
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°−ā 8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
24
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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