TI CD54HC165F3A

[ /Title
(CD74H
C165,
CD74H
CT165)
/Subject
(High
Speed
CMOS
Logic 8Bit Parallel-
CD54HC165, CD74HC165,
CD54HCT165, CD74HCT165
Data sheet acquired from Harris Semiconductor
SCHS156C
February 1998 - Revised October 2003
High-Speed CMOS Logic
8-Bit Parallel-In/Serial-Out Shift Register
Features
Description
• Buffered Inputs
The ’HC165 and ’HCT165 are 8-bit parallel or serial-in shift
registers with complementary serial outputs (Q7 and Q7)
available from the last stage. When the parallel load (PL)
input is LOW, parallel data from the D0 to D7 inputs are
loaded into the register asynchronously. When the PL is
HIGH, data enters the register serially at the DS input and
shifts one place to the right (Q0→Q1→Q2, etc.) with each
positive-going clock transition. This feature allows parallelto-serial converter expansion by typing the Q7 output to the
DS input of the succeeding device.
• Asynchronous Parallel Load
• Complementary Outputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
For predictable operation the LOW-to-HIGH transition of CE
should only take place while CP is HIGH. Also, CP an d CE
should be LOW before the LOW-to-HIGH transition of PL to
prevent shifting the data when PL goes HIGH.
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
Ordering Information
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
PART NUMBER
Pinout
CD54HC165, CD54HCT165
(CERDIP)
CD74HC165, CD74HCT165
(PDIP, SOIC)
TOP VIEW
PL 1
16 VCC
CP 2
15 CE
D4 3
14 D3
D5 4
13 D2
D6 5
12 D1
D7 6
11 D0
Q7 7
10 DS
GND 8
9 Q7
TEMP. RANGE
(oC)
CD54HC165F3A
-55 to 125
16 Ld CERDIP
CD54HCT165F3A
-55 to 125
16 Ld CERDIP
CD74HC165E
-55 to 125
16 Ld PDIP
CD74HC165M
-55 to 125
16 Ld SOIC
CD74HC165MT
-55 to 125
16 Ld SOIC
CD54HC165M96
-55 to 125
16 Ld SOIC
CD74HCT165E
-55 to 125
16 Ld PDIP
CD74HCT165M
-55 to 125
16 Ld SOIC
CD74HCT165MT
-55 to 125
16 Ld SOIC
CD54HCT165M96
-55 to 125
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
PACKAGE
1
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
Functional Diagram
D0
D1
D2
PARALLEL
DATA
INPUTS
D3
11
12
13
14
3
D4
4
D5
D6
Q7
7
6
D7
DS
9
5
SERIAL
OUTPUTS
Q7
10
1 15
PL
2
GND = 8
VCC = 16
CE
CP
TRUTH TABLE
INPUTS
OPERATING MODE
Parallel Load
Serial Shift
Hold Do Nothing
H
h
l
L
X
↑
qn
Qn REGISTER
OUTPUTS
PL
CE
CP
DS
D0 - D7
Q0
Q 1 - Q6
Q7
Q7
L
X
X
X
L
L
L-L
L
H
L
X
X
X
H
H
H-H
H
L
H
L
↑
l
X
L
q0 - q5
q6
q6
H
L
↑
h
X
H
q0 - q5
q6
q6
H
H
X
X
X
q0
q1 - q6
q7
q7
=High Voltage Level
= High Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition
= Low Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition
= Low Voltage Level
= Don’t Care
= Transition from Low to High Level
= Lower Case Letters Indicate The State Of the Reference Output Clock Transition
2
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current per Output, IO
For VO < -0.5V VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
High Level Input
Voltage
VIH
-
Low Level Input
Voltage
VIL
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
HC TYPES
High Level Output
Voltage
CMOS Loads
VOH
-
VIH or
VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
II
VCC or
GND
-
-
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
-
6
-
-
±0.1
-
±1
-
±1
µA
3
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
SYMBOL
VI (V)
ICC
VCC or
GND
0
High Level Input
Voltage
VIH
-
Low Level Input
Voltage
VIL
High Level Output
Voltage
CMOS Loads
VOH
PARAMETER
Quiescent Device
Current
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
6
-
-
8
-
80
-
160
µA
-
4.5 to
5.5
2
-
-
2
-
2
-
V
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
VIH or
VIL
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
II
VCC to
GND
0
5.5
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
-
8
-
80
-
160
µA
∆ICC
(Note 2)
VCC
-2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
DS, D0 to D7
0.35
CP, PL
0.65
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.
Prerequisite For Switching Specifications
25oC
PARAMETER
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
tWL, tWH
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
HC TYPES
CP Pulse Width
4
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
Prerequisite For Switching Specifications
(Continued)
25oC
PARAMETER
PL Pulse Width
Set-up Time
D0-D7 to PL
Hold Time
VCC (V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
tWL
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
2
35
-
45
-
55
-
ns
4.5
7
-
9
-
11
-
ns
6
6
-
8
-
9
-
ns
2
0
-
0
-
0
-
ns
4.5
0
-
0
-
0
-
ns
6
0
-
0
-
0
-
ns
2
100
-
125
-
150
-
ns
4.5
20
-
25
-
30
-
ns
6
17
-
21
-
26
-
ns
2
6
-
5
-
4
-
MHz
4.5
30
-
24
-
20
-
MHz
6
35
-
28
-
24
-
MHz
tSU
tSU(L)
tSU
tH
DS to CP or CE
CE to CP
Recovery Time
tH
tREC
PL to CP
Maximum Clock Pulse
Frequency
-55oC TO 125oC
SYMBOL
DS to CP
CE to CP
-40oC TO 85oC
fMAX
HCT TYPES
CP Pulse Width
tWL, tWH
4.5
18
-
23
-
27
-
ns
PL Pulse Width
tWL
4.5
20
-
25
-
30
-
ns
Set-up Time
DS to CP
tSU
4.5
20
-
25
-
30
-
ns
tSU(L)
4.5
20
-
25
-
30
-
ns
D0-D7 to PL
tSU
6
20
-
25
-
30
-
ns
Hold Time
DS to CP or CE
tH
4.5
7
-
9
-
11
-
ns
CE to CP
tS, tH
4.5
0
-
0
-
0
-
ns
Recovery Time
PL to CP
tREC
4.5
20
-
25
-
30
-
ns
Maximum Clock Pulse
Frequency
fMAX
4.5
27
-
22
-
18
-
MHz
CE to CP
5
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
Switching Specifications
PARAMETER
Input tr, tf = 6ns
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
-40oC TO 85oC -55oC TO 125oC
VCC (V)
TYP
MAX
MAX
MAX
UNITS
2
-
165
205
250
ns
4.5
-
33
41
50
ns
CL = 15pF
5
13
-
-
-
ns
CL = 50pF
6
-
28
35
43
ns
CL = 50pF
2
-
175
220
265
ns
4.5
-
35
44
53
ns
CL = 15pF
5
14
-
-
-
ns
CL = 50pF
6
-
30
37
45
ns
CL = 50pF
2
-
150
190
225
ns
4.5
-
30
38
45
ns
CL = 15pF
5
12
-
-
-
ns
CL = 50pF
6
-
26
33
38
ns
CL = 50pF
2
-
75
95
110
ns
4.5
-
15
19
22
ns
6
-
13
16
19
ns
HC TYPES
Propagation Delay
CP or CE to Q7 or Q7
PL to Q7 or Q7
D7 to Q7 or Q7
Output Transition Times
tPLH, tPHL
tPLH, tPHL
tTLH, tTHL
Input Capacitance
CIN
-
-
-
10
10
10
pF
Power Dissipation
Capacitance
(Notes 3, 4)
CPD
-
5
17
-
-
-
pF
CL = 50pF
4.5
-
40
50
60
ns
CL = 15pF
5
17
-
-
-
ns
CL = 50pF
4.5
-
40
50
60
ns
CL = 15pF
5
17
-
-
-
ns
CL = 50pF
4.5
-
35
44
53
ns
CL = 15pF
5
14
-
-
-
ns
tTLH, tTHL
CL = 50pF
4.5
-
15
19
22
ns
Input Capacitance
CIN
CL = 50pF
-
-
10
10
10
pF
Power Dissipation
Capacitance
(Notes 3, 4)
CPD
5
24
-
-
pF
HCT TYPES
Propagation Delay
tPLH, tPHL
CP or CE to Q7 or Q7
PL to Q7 or Q7
D7 to Q7 or Q7
Output Transition Times
tPLH, tPHL
tPLH, tPHL
-
NOTES:
3. CPD is used to determine the dynamic power consumption, per package.
4. PD = VCC2 fi + ∑ (CL VCC2 + fO) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply
Voltage.
6
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
Test Circuits and Waveforms
tr
tf
90%
10%
CP OR CE
VS
GND
tW
tW
INPUT LEVEL
1/fMAX
tPHL
90%
Q7 OR Q7
PL
tPLH
tPHL
tPLH
VS
10%
VS
Q7 OR Q7
tTLH
tTHL
FIGURE 3. SERIAL-SHIFT MODE
tr
FIGURE 4. PARALLEL-LOAD MODE
tf
INPUT LEVEL
90%
10%
INPUT D7
VALID
INPUT LEVEL
GND
tPLH
GND
tSU
VS
tH
INPUT LEVEL
VS
PL
tTLH
tTHL
VS
INPUTS D0-D7
tPHL
90%
10%
Q7 OR Q7
VS
GND
FIGURE 5. PARALLEL-LOAD MODE
FIGURE 6. PARALLEL-LOAD MODE
VALID
INPUT LEVEL
INPUTS DS
PL
GND
tSU
tH
INPUT LEVEL
VS
GND
tREC
INPUT LEVEL
CP OR CE
CP OR CE
INPUT LEVEL
VS
GND
GND
FIGURE 7. SERIAL-SHIFT MODE
FIGURE 8. SERIAL-SHIFT MODE
CE INHIBITED
INPUT LEVEL
CP
tSU
GND
tSU(L)
tSU
CP
tSU(L)
INPUT LEVEL
INHIBITED
CE
GND
FIGURE 9. SERIAL-SHIFT, CLOCK-INHIBIT MODE
7
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
PACKAGING INFORMATION
(1)
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
5962-8685501EA
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
CD54HC165F3A
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
CD54HCT165F3A
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
CD74HC165E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HC165EE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HC165M
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC165M96
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC165M96E4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC165M96G4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC165ME4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC165MG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC165MT
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC165MTE4
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC165MTG4
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT165E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HCT165EE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HCT165M
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT165M96
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT165M96E4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT165M96G4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT165ME4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT165MG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT165MT
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT165MTE4
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCT165MTG4
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
The marketing status values are defined as follows:
Addendum-Page 1
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CD74HC165M96
D
16
SITE 27
330
16
6.5
10.3
2.1
8
16
Q1
CD74HC165M96
D
16
SITE 41
330
16
6.5
10.3
2.1
8
16
Q1
CD74HCT165M96
D
16
SITE 27
330
16
6.5
10.3
2.1
8
16
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Sep-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
CD74HC165M96
D
16
SITE 27
342.9
336.6
0.0
CD74HC165M96
D
16
SITE 41
346.0
346.0
0.0
CD74HCT165M96
D
16
SITE 27
342.9
336.6
0.0
Pack Materials-Page 2
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