SN65LVDS250 SN65LVDT250 www.ti.com SLLS594B – MARCH 2004 – REVISED OCTOBER 2004 LVDS 4x4 CROSSPOINT SWITCH FEATURES • • • • • • • • • • • SN65LVDS250DBT ( Marked as LVDS250) SN65LVDT250DBT ( Marked as LVDT250) (TOP VIEW) Greater Than 2.0 Gbps Operation Nonblocking Architecture Allows Each Output to be Connected to Any Input Pk-Pk Jitter: – 60 ps Typical at 2.0 Gbps – 110 ps Typical at 2.5 Gbps Compatible With ANSI TIA/EIA-644-A LVDS Standard Available Packaging 38-Pin TSSOP 25 mV of Input Voltage Threshold Hysteresis Propagation Delay Times: 800 ps Typical Inputs Electrically Compatible With LVPECL, CML and LVDS Signal Levels Operates From a Single 3.3-V Supply Low Power: 110 mA Typical Integrated 110-Ω Line Termination Resistors Available With SN65LVDT250 S10 S11 1A 1B S20 S21 2A 2B GND VCC GND 3A 3B S30 S31 4A 4B S40 S41 APPLICATIONS VCC GND 1Y 1Z 1DE 2Y 2Z 2DE GND VCC GND 3Y 3Z 3DE 4Y 4Z 4DE GND VCC EYE PATTERN Clock Buffering/Clock Muxing Wireless Base Stations High-Speed Network Routing Telecom/Datacom DESCRIPTION The SN65LVDS250 and SN65LVDT250 are 4x4 nonblocking crosspoint switches in a flow-through pin-out allowing for ease in PCB layout. Low-voltage differential signaling (LVDS) is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve the high signaling speeds while maintaining low signal skews. The SN65LVDT250 incorporates 110-Ω termination resistors for those applications where board space is a premium. The SN65LVDS250 and SN65LVDT250 characterized for operation from -40°C to 85°C. are 75 mV/div • • • • 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 76 − ps/div VIC= 1.2 V |VID| = 200 mV 2 Gbps Input = PRBS 223 −1 VCC = 3.3 V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated SN65LVDS250 SN65LVDT250 www.ti.com SLLS594B – MARCH 2004 – REVISED OCTOBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. LOGIC DIAGRAM S10 - S41 8 1DE 1A 1Y 1B 1Z 2DE 2A 2B 2Y 4X4 MUX 2Z 3DE 3A 3Y 3B 3Z 4DE 4A 4Y 4B 4Z Integrated Termination on LVDT Only 2 SN65LVDS250 SN65LVDT250 www.ti.com SLLS594B – MARCH 2004 – REVISED OCTOBER 2004 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS INPUT LVDS250 VCC A VCC B 7V 7V VCC VCC 300 kΩ DE S10, S41 400 Ω 400 Ω 300 kΩ 7V 7V OUTPUT LVDS250 VCC VCC VCC Y 7V Z 7V 3 SN65LVDS250 SN65LVDT250 www.ti.com SLLS594B – MARCH 2004 – REVISED OCTOBER 2004 Table 1. CROSSPOINT LOGIC TABLES OUTPUT CHANNEL 1 CONTROL PINS OUTPUT CHANNEL 2 INPUT SELECTED CONTROL PINS OUTPUT CHANNEL 3 INPUT SELECTED CONTROL PINS INPUT SELECTED OUTPUT CHANNEL 4 CONTROL PINS INPUT SELECTED S10 S11 1Y/1Z S20 S21 2Y/2Z S30 S31 3Y/3Z S40 S41 4Y/4Z 0 0 1A/1B 0 0 1A/1B 0 0 1A/1B 0 0 1A/1B 0 1 2A/2B 0 1 2A/2B 0 1 2A/2B 0 1 2A/2B 1 0 3A/3B 1 0 3A/3B 1 0 3A/3B 1 0 3A/3B 1 1 4A/4B 1 1 4A/4B 1 1 4A/4B 1 1 4A/4B PACKAGE DISSIPATION RATINGS (1) (2) (3) PACKAGE CIRCUIT BOARD MODEL TA≤ 25°C POWER RATING TSSOP (DBT) Low-K (2) TSSOP (DBT) High-K (3) DERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING 1038 mW 9.0 mW/°C 496 mW 1772 mW 15.4 mW/°C 847 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounded and with no air flow. In accordance with the Low-K thermal metric definitions of EIA/JESD51-6 In accordance with the High-K thermal metric definitions of EIA/JESD51-6 THERMAL CHARACTERISTICS PARAMETER TEST CONDITIONS VALUE ΘJB Junction-to-board thermal resistance 40.3 ΘJC Junction-to-case thermal resistance 8.5 PD Device power dissipation UNITS °C/W VCC = 3.3 V, TA = 25°C, 1 GHz 356 mW VCC = 3.6 V, TA = 85°C, 1 GHz 522 mW ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNITS Supply voltage range, VCC Voltage range (2) -0.5 V to 4 V S, DE -0.5 V to 4 V A, B -0.5 V to 4 V |VA - VB| (LVDT only) 1V Y, Z Electrostatic discharge Continuous power dissipation (1) (2) (3) (4) 4 -0.5 V to 4 V Human body model (3) Charged-device model (4) All pins All pins ±3 kV ±500 V See Dissipation Rating Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. SN65LVDS250 SN65LVDT250 www.ti.com SLLS594B – MARCH 2004 – REVISED OCTOBER 2004 RECOMMENDED OPERATING CONDITIONS MIN VCC Supply voltage VIH High-level input voltage S10-S41, 1DE-4DE VIL Low-level input voltage S10-S41, 1DE-4DE |VID| 3 Magnitude of differential input voltage TA 3.3 V 2 VCC V 0 0.8 V 0.1 1 V LVDT 0.1 0.8 V 0 Junction temperature (1) (1) UNIT 3.6 LVDS Input voltage (any combination of common-mode or input signals) TJ NOM MAX Operating free-air temperature -40 3.3 V 140 °C 85 °C Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded. TIMING SPECIFICATIONS PARAMETER tSET Input to select setup time tHOLD Input to select hold time tSWITCH Select to switch output MIN NOM MAX UNIT 0.6 See Figure 7 ns 0.2 1.2 ns 1.6 ns INPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted (1) PARAMETER TEST CONDITIONS VIT+ Positive-going differential input voltage threshold See Figure 1 VIT- Negative-going differential input voltage threshold See Figure 1 VID(HYS) Differential input voltage hysteresis MIN TYP (1) MAX UNIT 100 mV -100 mV 25 1DE-4DE IIH High-level input current IIL Low-level input current II Input current (A or B inputs) VI = 0 V or 3.3 V, second input at 1.2 V (other input open for LVDT) -20 20 µA II(OFF) Input current (A or B inputs) VCC≤ 1.5 V, VI = 0 V or 3.3 V, second input at 1.2 V(other input open for LVDT) -20 20 µA IIO Input offset current (|IIA - IIB|) (LVDS) VIA = VIB, 0 ≤ VIA≤ 3.3 V -6 6 µA Termination resistance (LVDT) VID = 300 mV, VIC = 0 V to 3.3 V 90 110 132 Termination resistance (LVDT with power-off) VID = 300 mV, VIC = 0 V to 3.3 V, VCC = 1.5 V 90 110 132 RT CI (1) S10-S41 1DE-4DE S10-S41 Differential input capacitance VIH = 2 V mV -10 VIL = 0.8 V 20 -10 20 2.5 µA µA Ω pF All typical values are at 25°C and with a 3.3 V supply. 5 SN65LVDS250 SN65LVDT250 www.ti.com SLLS594B – MARCH 2004 – REVISED OCTOBER 2004 OUTPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS |VOD| Differential output voltage magnitude ∆|VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage ICC Supply current RL=100 Ω IOS Short-circuit output current VOY or VOZ = 0 V IOSD Differential short circuit output current VOD = 0 V IOZ High-impedance output current VO = 0 V or VCC CO Differential output capacitance See Figure 2 VID = ±100 mV See Figure 3 MIN TYP MAX UNIT 247 350 454 mV -50 50 mV 1.125 1.375 -50 50 mV 50 150 mV 110 145 mA -27 27 mA -12 12 mA ±1 µA 2 V pF SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output 700 800 1200 tPHL Propagation delay time, high-to-low-level output 700 800 1200 tr Differential output signal rise time (20%-80%) tf Differential output signal fall time (20%-80%) tsk(p) Pulse skew (|tPHL - tPLH|) (1) 50 ps tsk(o) Channel-to-channel output skew (2) 175 ps tsk(pp) Part-to-part skew (3) 300 ps See Figure 4 200 245 200 245 0 deviation) (4) ps tjit(per) Period jitter, rms (1 standard See Figure 6 1 3 ps tjit(cc) Cycle-to-cycle jitter (peak) (5) See Figure 6 8 17 ps tjit(pp) Peak-to-peak jitteR (6) See Figure 6 60 110 ps See Figure 6 48 65 ps peak-to-peak (7) tjit(det) Deterministic jitter, tPHZ Propagation delay, high-level-to-high-impedance output tPLZ Propagation delay, low-level-to-high-impedance output tPZH Propagation delay, high-impedance -to-high-level output tPZL Propagation delay, high-impedance-to-low-level output (1) (2) (3) (4) (5) (6) (7) 6 6 See Figure 5 6 300 ns 300 tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device. tsk(o) is the maximum delay time difference between drivers over temperature, VCC, and process. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Input voltage = VID = 200 mV, 50% duty cycle at 1.0 GHz, tr = tf= 50 ps (20% to 80%), measured over 1000 samples. Input voltage = VID = 200 mV, 50% duty cycle at 1.0 GHz, tr = tf= 50 ps (20% to 80%). Input voltage = VID = 200 mV, 223-1 PRBS pattern at 2.0 Gbps, tr = tf = 50 ps (20% to 80%), measured over 200k samples. Input voltage = VID = 200 mV, 27-1 PRBS pattern at 2.0 Gbps, tr= tf = 50 ps (20% to 80%). SN65LVDS250 SN65LVDT250 www.ti.com SLLS594B – MARCH 2004 – REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION IIA A Y B Z VID VIA+VIB VOD VIA VIC VIB 2 VOY VOC VOZ IIB VOY+VOZ 2 Figure 1. Voltage and Current Definitions 3.75 kΩ Y VOD + _ 100 Ω Z 0 V ≤ V(test) ≤ 2.4 V 3.75 kΩ Figure 2. Differential Output Voltage (VOD) Test Circuit A A ≈1.4 V B ≈1 V 49.9 Ω ±1% Y VID VOC(PP) B A. Z 49.9 Ω ±1% 1 pF VOC VOC(SS) VOC All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ±10 ns; RL = 100Ω ; CL includes instrumentation and fixture capacitance within 0,06 mm of the DUT; the measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 300 MHz. Figure 3. Test Circuit and Definitions fot the Driver Common-Mode Output Voltage A VID VIA B VIB Y 1 pF VOY VOD Z 100 Ω VIA 1.4 V VIB 1V VID 0.4 V 0V -0.4 V VOZ tPHL tPLH 0V Differential 80% VOY - VOZ 20% tf A. tr All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 0.25 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the DUT. Figure 4. Timing Test Circuit and Waveforms 7 SN65LVDS250 SN65LVDT250 www.ti.com SLLS594B – MARCH 2004 – REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION (continued) 49.9 Ω ±1% Y 1 V or 1.4 V 1 pF 1.2 V 49.9 Ω ±1% VOY Z DE 1.2 V VOZ 3V 1.5 V 0V DE ≅ 1.4 V VOY or VOZ 1.25 V 1.2 V tPZH tPHZ 1.2 V 1.15 V ≅1V VOZ or VOY tPZL A. tPLZ All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the DUT. Figure 5. Enable and Disable Time Circuit and Definitions VA 0V VB Clock Input 0V Ideal Output VY - VZ 1/fo 1/fo Period Jitter Cycle-to-Cycle Jitter Actual Output Actual Output 0V 0V VY - VZ tc(n) VY - VZ tc(n) tc(n +1) tjit(cc) = | tc(n) - tc(n + 1) | tjit(pp) = | tc(n) - 1/fo | Peak-to-Peak Jitter VA PRBS Input 0V VB VY PRBS Output 0V VZ tjit(pp) A. All input pulses are supplied by an Agilent 81250 Stimulus System. B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software. Figure 6. Driver Jitter Measurement Waveforms 8 SN65LVDS250 SN65LVDT250 www.ti.com SLLS594B – MARCH 2004 – REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION (continued) A/B A/B S tSET tHOLD OUT Y/Z Y/Z tSWITCH DE A/B A/B S tSET OUT tHOLD Y/Z Y/Z tSWITCH DE A. tSET and tHOLD times specify that data must be in a stable state before and after mux control switches. Figure 7. Input to Select for Both Rising and Falling Edge Setup and Hold Times 9 SN65LVDS250 SN65LVDT250 www.ti.com SLLS594B – MARCH 2004 – REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY 103 98 200 400 600 800 900 tPHL 800 tPLH 700 600 −45 1000 1200 f − Frequency − MHz Peak-to-Peak Jitter − ps VID = 800 mV VID = 400 mV 10 0.5 1 1.5 2 2.5 3 30 VID = 800 mV 80 VID = 400 mV 40 220 440 660 880 VID = 200 mV 20 VID = 400 mV VID = 800 mV 15 10 VID = 200 mV 5 0 0 1100 VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, Input = Clock 25 100 60 0 440 f − Frequency − MHz 880 1320 1760 0 2200 220 440 660 880 Figure 11. Figure 12. Figure 13. PEAK-TO-PEAK JITTER vs DATA RATE PEAK-TO-PEAK JITTER vs FREQUENCY PEAK-TO-PEAK JITTER vs DATA RATE 30 Peak-to-Peak Jitter − ps 100 VID = 800 mV 80 140 VCC = 3.3 V, TA = 25°C, VIC = 2.9 V, Input = Clock 25 VID = 400 mV 60 40 VID = 200 mV 20 VID = 200 mV VID = 400 mV VID = 800 mV 5 20 440 880 1320 1760 Data Rate − Mbps Figure 14. 2200 VCC = 3.3 V, TA = 25°C, VIC = 2.9 V, Input = PRBS 223 −1 120 15 10 1100 f − Frequency − MHz Data Rate − Mbps VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, Input = PRBS 223 −1 3.5 Vic − Common-Mode Input Voltage − V 20 0 Peak-to-Peak Jitter − ps 0 95 Peak-to-Peak Jitter − ps Peak-to-Peak Jitter − ps 700 −25 −5 15 35 55 75 TA − Free-Air Temperature − °C VCC = 3.3 V, TA = 25°C, VIC = 400 mV, Input = PRBS 223 −1 120 5 10 tPLH PEAK-TO-PEAK JITTER vs FREQUENCY 15 0 760 PEAK-TO-PEAK JITTER vs DATA RATE VID = 200 mV 0 tPHL 820 PEAK-TO-PEAK JITTER vs FREQUENCY 20 120 880 Figure 10. 140 140 940 Figure 9. VCC = 3.3 V, TA = 25°C VIC= 400 mV, Input = Clock 0 VCC = 3.3 V, TA = 25°C, |V ID| = 200 mV, f = 1 MHz Figure 8. 30 25 t pd − Propagation Delay Time − ps 108 0 1000 VCC = 3.3 V, VIC = 1.2 V, |V ID| = 200 mV, f = 1 MHz Peak-to-Peak Jitter − ps 113 PROPAGATION DELAY TIME vs COMMON-MODE INPUT VOLTAGE 1000 VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, |V ID| = 200 mV t pd − Propagation Delay Time − ps I CC − Supply Current − mA 118 PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 100 VID = 800 mV 80 60 VID = 200 mV 40 20 VID = 400 mV 0 0 0 220 440 660 880 f − Frequency − MHz Figure 15. 1100 0 440 880 1320 Data Rate − Mbps Figure 16. 1760 2200 SN65LVDS250 SN65LVDT250 www.ti.com SLLS594B – MARCH 2004 – REVISED OCTOBER 2004 TYPICAL CHARACTERISTICS (continued) PEAK-TO-PEAK JITTER vs FREE-AIR TEMPERATURE PEAK-TO-PEAK JITTER vs DATA RATE 120 90 VCC = 3.3 V, VIC = 1.2 V, |V ID| = 200 mV, Input = 2 Gbps PRBS 223 −1 100 Peak-to-Peak Jitter − ps Peak-to-Peak Jitter − ps 82 74 66 58 −40 −20 0 20 40 60 80 60 40 0 100 0 TA − Free-Air Temperature − °C 200 20 150 15 100 10 5 Added Random Jitter 0 1000 1500 EYE PATTERN 30 25 500 2800 35 250 50 2240 75 mV/div 300 1680 40 Period Jitter − ps VCC = 3.3 V, VIC = 1.2 V, |V ID| = 200 mV, TA = 25°C, Input = Clock 350 1120 Figure 18. DIFFERENTIAL OUTPUT VOLTAGE vs FREQUENCY 400 560 Data Rate − Mbps Figure 17. V OD − Differential Output Voltage − mV 80 20 50 0 VCC = 3.3 V, VIC = 1.2 V, |V ID| = 200 mV, Input = PRBS 223 −1 2000 0 2500 f − Frequency − MHz 60 − ps/div VIC= 1.2 V, |VID| = 200 mV, 2.5 Gbps, Input = PRBS 223 −1, VCC = 3.3 V Figure 19. Figure 20. 11 SN65LVDS250 SN65LVDT250 www.ti.com SLLS594B – MARCH 2004 – REVISED OCTOBER 2004 APPLICATION INFORMATION CONFIGURATION EXAMPLES S10 0 S30 1 S11 0 S31 0 S20 0 S40 1 S21 1 S41 1 S10 0 S30 0 S20 0 S40 0 S21 0 S41 0 1A 1Y 1A 1Y 1B 1Z 1B 1Z 2A 2Y 2Y 2B 2Z 2Z 3A 3Y 3Y 3B 3Z 3Z 4A 4Y 4Y 4B 4Z 4Z S10 0 S30 1 S11 0 S31 0 S20 0 S40 1 S21 0 S41 0 S10 1 S30 0 S11 1 S31 0 S20 1 S40 0 S21 1 S41 0 1A 1Y 1A 1Y 1B 1Z 1B 1Z 2Y 2Y 2Z 2Z 12 S11 0 S31 0 3A 3Y 3Y 3B 3Z 3Z 4Y 4A 4Y 4Z 4B 4Z SN65LVDS250 SN65LVDT250 www.ti.com SLLS594B – MARCH 2004 – REVISED OCTOBER 2004 APPLICATION INFORMATION (continued) TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, etc.) 50 Ω 3.3 V or 5 V 3.3 V SN65LVDS250 A ECL B 50 Ω 50 Ω 50 Ω VTT = VCC -2 V VTT Figure 21. Low-Voltage Positive Emitter-Coupled Logic (LVPECL) 3.3 V 50 Ω 50 Ω 3.3 V 3.3 V SN65LVDS250 A CML B 50 Ω 50 Ω 3.3 V Figure 22. Current-Mode Logic (CML) 3.3 V 3.3 V 50 Ω SN65LVDS250 A ECL B 50 Ω 1.1 kΩ VTT 1.5 kΩ VTT = VCC -2 V 3.3 V Figure 23. Single-Ended (LVPECL) 3.3 V or 5 V 50 Ω 3.3 V SN65LVDS250 A 100 Ω LVDS B 50 Ω Figure 24. Low-Voltage Differential Signaling (LVDS) 13 PACKAGE OPTION ADDENDUM www.ti.com 31-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LVDS250DBT ACTIVE SM8 DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LVDS250DBTG4 ACTIVE SM8 DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LVDS250DBTR ACTIVE SM8 DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LVDS250DBTRG4 ACTIVE SM8 DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LVDT250DBT ACTIVE SM8 DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LVDT250DBTG4 ACTIVE SM8 DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LVDT250DBTR ACTIVE SM8 DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LVDT250DBTRG4 ACTIVE SM8 DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVDS250DBTR DBT 38 SITE 60 330 16 6.9 10.2 1.8 12 16 Q1 SN65LVDT250DBTR DBT 38 SITE 60 330 16 6.9 10.2 1.8 12 16 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) SN65LVDS250DBTR DBT 38 SITE 60 346.0 346.0 33.0 SN65LVDT250DBTR DBT 38 SITE 60 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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