CD74ACT297 DIGITAL PHASE-LOCKED LOOP SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999 D D D D D D D D D D D D Digital Design Avoids Analog Compensation Errors Easily Cascadable for Hlgher Order Loops Useful Frequency Range – DC to 110 MHz Typical (K CLK) – DC to 70 MHz Typical (I/D CLK) Dynamically Variable Bandwidth Very Narrow Bandwidth Attainable Power-On Reset Output Capability – Standand: XORPD OUT, ECPD OUT – Bus Drlver: I/D OUT SCR Latch-Up-Resistant CMOS Process and Circuit Design Speed of Bipolar FAST/AS/S with Significantly Reduced Power Consumption Balanced Propagation Delays ESD Protectlon Exceeds 2000 V per MIL-STD-883, Method 3015 Packaged in Small-Outline Integrated Circuit Package M PACKAGE (TOP VIEW) B A ENCTR K CLK I/D CLK D/U I/D OUT GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC C D φA2 ECPD OUT XORPD OUT φB φA1 description The CD74ACT297 device is designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. These devices contain all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked loops as described in Figure 1. Both exclusive-OR (XORPD) and edge-controlled (ECPD) phase detectors are provided for maximum flexibility. Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation or to cascade to higher order phase-locked loops. The length of the up/down K counter is digitally programmable according to the K-counter function table. With A, B, C, and D all low, the K counter is disabled. With A high and B, C, and D low, the K counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C, and D are programmed high, the K counter becomes 17 stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A-through-D inputs can maximize the overall performance of the digital phase-locked loop. This device performs the classic first-order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked loop (DPLL) is not affected by VCC and temperature variations, but depends solely on accuracies of the K clock, I/D clock, and loop propagation delays. The I/D clock frequency and the divide-by-N modulos determine the center frequency of the DPLL. The center frequency is defined by the relationship fc = I/D clock/2N (Hz). The CD74ACT297 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI is a trademark of Texas Instruments Incorporated. FAST is a trademark of Fairchild Semiconductor. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD74ACT297 DIGITAL PHASE-LOCKED LOOP SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999 Modulo Controls D C B A 14 15 1 K CLK D/U ENCTR I/D CLK 2 4 6 3 Modulo K Counter 5 φA1 9 φB 10 φA2 13 Increment/Decrement Circuit 11 J 12 K Figure 1. Simplifed Block Diagram 2 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 I/D OUT XORPD OUT ECPD OUT CD74ACT297 DIGITAL PHASE-LOCKED LOOP SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999 Function Tables K COUNTER (DIGITAL CONTROL) D C B A MODULO (K) L L L L L L L H Inhibited 23 L L H L L L H H L H L L L H L H L H H L L H H H H L L L H L L H H L H L H L H H H H L L H H L H H H H L H H H H 24 25 26 27 28 29 210 211 212 213 214 215 216 217 EXCLUSIVE-OR PHASE DETECTOR φA1 φB L L L L H H H L H H H L XORPD OUT EDGE-CONTROLLED PHASE DETECTOR φA2 φB ECPD OUT H or L ↓ H ↓ H or L L H or L ↑ No change ↑ H or L No change H = steady-state high level L = steady-state low level ↓ = transition from high to low ↑ = transition from low to high POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CD74ACT297 DIGITAL PHASE-LOCKED LOOP SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999 functional block diagram K Counter A B C D 2 1 2 4 8 1 15 14 X/Y 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 To Mode Controls 12–2 (11 stages not shown) K CLK D/U ENCTR 4 R C20 6 20D R C20 3 T 20D M13 M14 M13 14T R 13T R 1T T 1T T 13D 14D R R 13T M14 T R 13D 14T T T R 14D R R R R POWER-UP RESET l=1 Decrement 1 Increment I/D CLK I/D Circuit 5 7 I/D OUT 21D 21D 21D C21 21D C21 C21 21J C21 C21 C21 C21 C21 21D C21 21D 21K 21D 21D Exclusive-OR Phase Detector φA1 9 11 φB XORPD OUT 10 Edge-Controlled Phase Detector S R φA2 4 12 S R 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ECPD OUT CD74ACT297 DIGITAL PHASE-LOCKED LOOP SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999 The phase detector generates an error-signal waveform that, at zero phase error, is a 50% duty-cycle square wave. At the limits of linear operation, the phase-detector output will be either high or low all of the time, depending on the direction of the phase error (φin – φout). Within these limits, the phase-detector output varies linearly with the input phase error according to the gain kd, which is expressed in terms of phase-detector output per cycle of phase error. The phase-detector output can be varied between ±1 according to the relation: Phase-detector output + % high100– % low (1) The output of the phase detector will be kd φe, where the phase error φe = φin – φout. Exclusive-OR phase detectors (XORPD) and edge-controlled phase detectors (ECPD) are commonly used digital types. The ECPD is more complex than the XORPD logic function, but can be described generally as a circuit that changes states on one of the transitions of its inputs. For an XORPD, kd is 4 because its output remains high (PD output = 1) for a phase error of 1/4 cycle. Similarly, for the ECPD, kd is 2 because its output remains high for a phase error of 1/2 cycle. The type of phase detector will determine the zero-phase-error point, i.e., the phase separation of the phase-detector inputs for φe defined to be zero. For the basic DPLL system of Figure 2, φe = 0 when the phase-detector output is a square wave. The XORPD inputs are 1/4 cycle out of phase for zero phase error. For the ECPD, φe = 0 when the inputs are 1/2 cycle out of phase. K CLK Mfc Carry Divide-By-N Counter D/U Borrow XORPD OUT φA1 fin, φin φB I/D CLK I/D Circuit 2 Nfc I/D OUT Divide-By-K Counter fout, φout Figure 2. DPLL Using Exclusive-OR Phase Detection The phase-detector output controls the up/down input to the K counter. The counter is clocked by input frequency Mfc, which is a multiple M of the loop center frequency fc. When the K counter recycles up, it generates a carry pulse. Recycling while counting down generates a borrow pulse. If the carry and borrow outputs are conceptually combined into one output that is positive for a carry and negative for a borrow, and if the K counter is considered as a frequency divider with the ratio Mfc/K, the output of the K counter will equal the input frequency multiplied by the division ratio. Thus, the output from the K counter is (kdφeMfc)K. The carry and borrow pulses go to the increment/decrement (I/D) circuit, which, in the absence of any carry or borrow pulse, has an output that is one half of the input clock (I/D CLK). The input clock is just a multiple, 2N, of the loop center frequency. In response to a carry or borrow pulse, the I/D circuit will either add or delete a pulse at I/D OUT. Thus, the output of the I/D circuit will be Nfc 4 (kdφeMfc)/2K. The output of the N counter (or the output of the phase-locked loop) is: fo + fc ) (kdfeMfc)ń2KN (2) When this result is compared to the equation for a first-order analog phase-locked loop, the digital equivalent of the gain of the VCO is just Mfc/2KN or fc/K for M = 2N. Thus, the simple first-order phase-locked loop with an adjustable K counter is the equivalent of an analog phase-locked loop with a programmable VCO gain. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CD74ACT297 DIGITAL PHASE-LOCKED LOOP SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999 Mfc K CLK Carry Divide-By-K Counter D/U ENCTR Borrow XORPD OUT φA1 fout, φout φB I/D CLK J fin, φin φA2 I/D Circuit ECPD 2 Nfc K I/D OUT Divide-By-N Counter Figure 3. DPLL Using Both Phase Detectors in a Ripple-Cancellation Scheme absolute maximum ratings over recommended operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V DC input diode current, IIK (VI < –0.5 V or VI > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA DC input diode current, IOK (VO < –0.5 V or VO > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA DC output source or sink current per output pin, IO (VO > –0.5 V or VO < VCC + 0.5 V) . . . . . . . . . . ±50 mA Continuous current through VCC or GND (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance,θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. For up to four outputs per device, add ±25 mA for each additional output. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions 6 MIN MAX 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO dt/dv Output voltage 0 TA Operating free-air temperature range High-level input voltage 2 Input rise and fall slew rate –40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V V 0.8 V VCC VCC V V 10 ns 85 °C CD74ACT297 DIGITAL PHASE-LOCKED LOOP SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS VI = VIH or VIL VI =VIH or VIL VCC TA = 25°C MIN MAX MIN MAX IO = –50 µA IO = –24 mA 4.5 V 4.4 4.5 V 3.94 IO = –75 mA IO = 50 µA 5.5 V 4.5 V 0.1 0.1 IO = 24 mA IO = 75 mA† 4.5 V 0.36 0.44 UNIT 4.4 V 3.8 3.85 5.5 V V 1.65 II ICC (MSI) VI = VCC or GND VI = VCC or GND 5.5 V ±0.1 ±1 5.5 V 8 80 ICC (SSI/FF) VI = VCC or GND 5.5 V 4 40 mA mA mA DICC VI = VCC –2.1 V 4.5 V to 5.5 V 2.4 2.8 mA † Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C. ACT Input Load Table INPUT UNIT LOAD ENCTR, D/U 0.1 A, B, C, D, K CLK, φA2 0.2 I/O CLK, φA1, φB 0.5 NOTE: Unit Load is ∆ICC limit specified in electrical characteristics table (e.g., 2.4 mA at 25°C). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 CD74ACT297 DIGITAL PHASE-LOCKED LOOP SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TA = 25°C MIN MAX PARAMETER fclock l k Clock frequency tw Pulse duration tsu Setup time before K CLK↑ th Hold time after K CLK↑ MIN K CLK 55 45 I/D CLK 40 35 K CLK 6 8 I/D CLK 7 9 D/U 13 17 ENCTR 12 16 D/U 3 7 ENCTR 2 6 Carry Pulse (Internal Signal) Borrrow Pulse (Internal Signal) I/D CLK I/D OUT 92CS-40449 Figure 4. I/D OUT In Lock Condition φB φA2 ECPD OUT 92CS-40450 Figure 5. Edge-Controlled Phase-Comparator Waveforms 8 POST OFFICE BOX 655303 MAX • DALLAS, TEXAS 75265 UNIT MHz ns ns ns CD74ACT297 DIGITAL PHASE-LOCKED LOOP SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999 φB φA1 XORPD OUT 92CS-40451 Figure 6. Exclusive-OR Phase-Detector Waveforms 1/F max tw I/D CLK 3V 1.5 V 1.5 V 0V tPHL tPHL ≈VCC 90% I/D OUT 10% 50% VCC 50% VCC VOL tTHL tTLH 92CS-40452 Figure 7. Waveforms Showing Clock (ID CLK) to Output (ID OUT) Propagation Delays, Clock Pulse Duration, and Maximum Clock Pulse Frequency 3V φB 1.5 V 1.5 V 0V tPHL φA1 3V 1.5 V 1.5 V 0V tPLH tPHL ≈VCC XORPD OUT 50% VCC 50% VCC 50% VCC 50% VCC VOL tPLH 92CS-43151 Figure 8. Waveforms Showing Phase Input (φB, φA2) to Output (XORPD OUT) Propagation Delays POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 CD74ACT297 DIGITAL PHASE-LOCKED LOOP SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999 3V φB 1.5 V 1.5 V 0V 3V 1.5 V φA2 0V ≈VCC 50% VCC 50% VCC ECPD OUT VOL tPLH tPHL 92CS-43152 Figure 9. Waveforms Showing Phase Input (φB, φA2) to Output (ECPD OUT) Propagation Delays ÏÏÏ ÎÎÎÎÎÏÏÏÏ ÏÏÏ ÎÎÎÎÎÏÏÏÏ ÏÏÏ ÎÎÎÎÎÏÏÏÏ tH tH 3V D/U ENCTR 1.5 V 1.5 V 1.5 V 1.5 V 0V tsu tsu 3V K CLK 1.5 V 1.5 V 1.5 V 0V tw 1/fmax 92CS-40453 NOTE A: Shaded areas indicate when the input is permitted to change for predictable output performance. Figure 10. Waveforms Showing Clock (K CLK) Pulse Duration and Maximum Clock Pulse Frequency, and Inputs (D/U, ENCTR) to Clock (K CLK) Setup and Hold Times. switching characteristics over recommended operating free-air temperature range, CL = 50 pF, (unless otherwise noted) PARAMETER fmax tPLH tPHL tPHL tPLH tPHL tPLH tPHL tPLH 10 FROM (INPUT) K CLK I/D CLK TO (OUTPUT) I/D OUT I/D CLK I/D OUT φA2 ECPD OUT φA1 XORPD OUT φB XORPD OUT φB ECPD OUT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TA = 25°C TYP MAX MIN 55 45 40 35 MAX UNIT MHz 19 24 19 24 24 30 17 22 17 22 17 22 17 22 24 30 ns ns ns ns ns CD74ACT297 DIGITAL PHASE-LOCKED LOOP SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 500 Ω CL = 50 pF (see Note A) LOAD CIRCUIT 3V 1.5 V Timing Input 0V tw 90% 1.5 V Input tsu 3V 90% 1.5 V 10% 10% tr tf 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) 3V 1.5 V 1.5 V 0V tPLH In-Phase Output VOH 50% VCC VOL tPHL Out-of-Phase Output tPLZ 50% VCC tPZH VOH 50% VCC VOL 1.5 V 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH 50% VCC 3V 1.5 V tPZL tPHL 50% VCC 3V 1.5 V 1.5 V Data Input VOLTAGE WAVEFORMS INPUT RISE AND FALL TIMES AND PULSE DURATION Input th VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 20% VCC [ VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 11. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated