LTC6820 isoSPI Isolated Communications Interface Features Description 1Mbps Isolated SPI Data Communications n Simple Galvanic Isolation Using Standard Transformers n Bidirectional Interface Over a Single Twisted Pair n Supports Cable Lengths Up to 100 Meters n Very Low EMI Susceptibility and Emissions n Configurable for High Noise Immunity or Low Power n Engineered for ISO26262 Compliant Systems n Requires No Software Changes in Most SPI Systems n Ultralow, 2µA Idle Current n Automatic Wake-Up Detection n Operating Temperature Range: –40°C to 125°C n2.7V to 5.5V Power Supply n Interfaces to All Logic from 1.7V to 5.5V n Available in 16-Lead QFN and MSOP Packages The LTC®6820 provides bidirectional SPI communications between two isolated devices through a single twistedpair connection. Each LTC6820 encodes logic states into signals that are transmitted across an isolation barrier to another LTC6820. The receiving LTC6820 decodes the transmission and drives the slave bus to the appropriate logic states. The isolation barrier can be bridged by a simple pulse transformer to achieve hundreds of volts of isolation. n Applications The LTC6820 drives differential signals using matched source and sink currents, eliminating the requirement for a transformer center tap and reducing EMI. Precision window comparators in the receiver detect the differential signals. The drive currents and the comparator thresholds are set by a simple external resistor divider, allowing the system to be optimized for required cable lengths and desired signal-to-noise performance. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and isoSPI is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patents pending. Industrial Networking Battery Monitoring Systems n Remote Sensors n n Typical Application Microcontroller to SPI Slave Isolated Interface SDO SDI SCK CS REMOTE SLAVE IC 1.2 MSTR MOSI IP MISO SCK IM CS 1.0 120Ω 100 METERS TWISTED PAIR IP MOSI MISO IM SCK CS 0.8 0.6 0.4 0.2 LTC6820 MSTR SDI SDO SCK CS CAT-5 ASSUMED LTC6820 DATA RATE (Mbps) MASTER µC Data Rate vs Cable Length 0 120Ω 1 10 CABLE LENGTH (METERS) 100 6820 TA01b 6820 TA01a 6820f 1 LTC6820 Absolute Maximum Ratings (Notes 1, 2, 3) Input Supply Voltages (VDD and VDDS) to GND............6V Pin Voltages SCK, CS, EN................–0.3V to VDDS + 0.3V (6V Max) IBIAS, SLOW, IP, IM......–0.3V to VDD + 0.3V (6V Max) All Other Pin Voltages............................... –0.3V to 6V Maximum Source/Sink Current IP, IM..................................................................30mA MOSI, MISO, SCK, CS.........................................20mA Operating Temperature Range LTC6820I..............................................–40°C to 85°C LTC6820H........................................... –40°C to 125°C Specified Temperature Range LTC6820I..............................................–40°C to 85°C LTC6820H........................................... –40°C to 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) MSOP................................................................ 300°C Pin Configuration GND ICMP IBIAS EN TOP VIEW TOP VIEW 16 15 14 13 MOSI 1 EN MOSI MISO SCK CS VDDS POL PHA 12 SLOW MISO 2 11 MSTR 17 SCK 3 10 IP CS 4 9 IM 8 16 15 14 13 12 11 10 9 IBIAS ICMP GND SLOW MSTR IP IM VDD MS PACKAGE 16-LEAD PLASTIC MSOP VDD 7 PHA 6 POL VDDS 5 1 2 3 4 5 6 7 8 UD PACKAGE 16-LEAD (3mm × 3mm) PLASTIC QFN TJMAX = 150°C, θJA = 120°C/W TJMAX = 150°C, θJA = 58.7°C/W EXPOSED PAD (PIN 17) PCB CONNECTION TO GND IS OPTIONAL Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6820IUD#PBF LTC6820IUD#TRPBF LGFM 16-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C LTC6820HUD#PBF LTC6820HUD#TRPBF LGFM 16-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C LTC6820IMS#PBF LTC6820IMS#TRPBF 6820 16-Lead Plastic MSOP –40°C to 85°C LTC6820HMS#PBF LTC6820HMS#TRPBF 6820 16-Lead Plastic MSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 6820f 2 LTC6820 Electrical Characteristics The l denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25°C. VDD = 2.7V to 5.5V, VDDS = 1.7V to 5.5V, RBIAS = 2k to 20k unless otherwise specified. All voltages are with respect to GND. SYMBOL PARAMETER Power Supply Operating Supply Voltage Range VDD IO Supply Voltage Range (Level Shifting) VDDS Supply Current, READY/ACTIVE States IDD (Note 4) Supply Current, IDLE State IDDS IO Supply Current (Note 5) Biasing VBIAS Voltage on IBIAS Pin IB AIB Isolated Interface Bias Current (Note 6) Isolated Interface Current Gain VA Transmitter Pulse Amplitude Threshold-Setting Voltage on ICMP Pin Leakage Current on ICMP Pin Leakage Current on IP and IM Pins Receiver Comparator Threshold Voltage Gain Receiver Common Mode Bias VCM Receiver Input Resistance RIN Idle/Wake-Up (See Figures 13, 14, 15) Differential Wake-Up Voltage VWAKE (See Figure 13) Dwell Time at VWAKE tDWELL Start-Up Time After Wake Detection tREADY Idle Time-Out Duration tIDLE Digital I/O VIH(CFG) Digital Voltage Input High, Configuration Pins (PHA, POL, MSTR, SLOW) Digital Voltage Input Low, Configuration VIL(CFG) Pins (PHA, POL, MSTR, SLOW) Digital Voltage Input High, SPI Pins VIH(SPI) (CS, SCK, MOSI, MISO) Digital Voltage Input Low, SPI Pins VIL(SPI) (CS, SCK, MOSI, MISO) Digital Voltage Input High, EN Pin VIH(EN) VICMP ILEAK(ICMP) ILEAK(IP/IM) ATCMP VIL(EN) Digital Voltage Input Low, EN Pin VOH Digital Voltage Output High (CS and SCK) VOL Digital Voltage Output Low (MOSI, MISO, CS, SCK) CONDITIONS MIN l 2.7 1.7 4 l 1.3 l Affects CS, SCK, MOSI, MISO and EN Pins RBIAS = 2kΩ (IB = 1mA) 1/tCLK = 0MHz 1/tCLK = 1MHz 1/tCLK = 0MHz RBIAS = 20kΩ (IB = 0.1mA) 1/tCLK = 1MHz MSTR = 0V MSTR = VDD SPI Inputs and EN Pin at 0V or VDDS, SPI Outputs Unloaded l READY/ACTIVE State IDLE State RBIAS = 2k to 20k VA ≤ 1.6V VA = |VIP – VIM| VTCMP = ATCMP • VICMP VICMP = 0V to VDD IDLE State, VIP = VIM = 0V to VDD VCM = VDD/2 to VDD – 0.2V, VICMP = 0.2V to 1.5V IP/IM Not Driving Single-Ended to IP or IM l l l 4.8 7 2 2.4 2 1 l 1.9 l IB = 1mA IB = 0.1mA VDD < 3.3V VDD ≥ 3.3V TYP l l 18 18 2.0 0 VBIAS/RBIAS 20 20 l l l 0.2 l l 0.5 MAX UNITS 5.5 5.5 5.8 2.9 6 3 1 V V mA mA mA mA µA µA µA 2.1 V V mA 22 mA/mA 24 mA/mA VDD – 1.7V V 1.6 V 1.5 V ±1 µA ±2 µA 0.6 V/V l 0.4 l (VDD – VICMP/3 – 167mV) 26 35 42 V kΩ tDWELL = 240ns l 240 mV VWAKE = 240mV l 240 ns µs ms l l 4 VDD = 2.7V to 5.5V (POL, PHA, MSTR, SLOW) l 0.7 • VDD VDD = 2.7V to 5.5V (POL, PHA, MSTR, SLOW) l VDDS = 2.7V to 5.5V VDDS = 1.7V to 2.7V VDDS = 2.7V to 5.5V VDDS = 1.7V to 2.7V VDDS = 2.7V to 5.5V VDDS = 1.7V to 2.7V VDDS = 2.7V to 5.5V VDDS = 1.7V to 2.7V VDDS = 3.3V, Sourcing 2mA VDDS = 1.7V, Sourcing 1mA VDDS = 3.3V, Sinking 3.3mA VDDS = 1.7V, Sinking 1mA l 0.7 • VDDS l 0.8 • VDDS l l 5.7 8 7.5 V 0.3 • VDD 0.3 • VDDS 0.2 • VDDS l 2 l 0.85 • VDDS l l 0.8 0.25 • VDDS l VDDS – 0.2 l VDDS – 0.25 l l 0.2 0.2 V V V V V V V V V V V V V 6820f 3 LTC6820 Electrical Characteristics The l denotes the specifications which apply over the full specified junction temperature range, otherwise specifications are at TA = 25°C. VDD = 2.7V to 5.5V, VDDS = 1.7V to 5.5V, RBIAS = 2k to 20k unless otherwise specified. All voltages are with respect to GND. SYMBOL PARAMETER ILEAK(DIG) Digital Pin Input Leakage Current Input/Output Pin Capacitance CI/O Isolated Pulse Timing (See Figure 2) t1/2PW(CS) Chip-Select Half-Pulse Width Chip-Select Pulse Inversion Delay tINV(CS) Chip-Select Response Delay tDEL(CS) Data Half-Pulse Width t½PW(D) Data Pulse Inversion Delay tINV(D) Data Response Delay tDEL(D) isoSPI™ Timing—Master (See Figures 3, 4) SCK Latching Edge to SCK Latching Edge tCLK CONDITIONS PHA, POL, MSTR, SLOW = 0V to VDD CS, SCK, MOSI, MISO, EN = 0V to VDDS (Note 9) MIN TYP l l 120 150 40 140 50 l l l l (Note 8) (Note 7) MOSI Setup Time Before SCK Latching Edge (Note 8) t1 MOSI Hold Time After SCK Latching Edge t2 SCK Low tCLK = t3 + t4 ≥ 1µs t3 SCK High tCLK = t3 + t4 ≥ 1µs t4 CS Rising Edge to CS Falling Edge t5 SCK Latching Edge to CS Rising Edge (Note 7) t6 CS Falling Edge to SCK Latch Edge (Note 7) t7 SCK Non-Latch Edge to MISO Valid (Note 8) t8 SCK Latching Edge to Short ±1 Transmit t9 CS Transition to Long ±1 Transmit t10 CS Rising Edge to MISO Rising (Note 8) t11 isoSPI Timing—Slave (See Figures 3, 4) isoSPI Data Recognized to SCK (Note 8) t12 Latching Edge SCK Pulse Width t13 SCK Non-Latch Edge to isoSPI Data Transmit (Note 8) t14 CS Falling Edge to SCK Non-Latch Edge PHA = 1 t15 CS Falling Edge to isoSPI Data Transmit t16 CS Rising Edge to SCK Latching Edge PHA = 1 t17 CS Rising Edge to MOSI Rising Edge t18 Data Return Delay tRTN Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive, and all voltages are referenced to GND unless otherwise specified. 75 l SLOW = 0 SLOW = 1 l l l l l l l l l l l l l l l l l l l l l l l l 110 0.9 90 0.9 115 0.9 90 0.9 200 1.8 90 0.9 145 1.1 115 1.1 145 1.1 120 1.1 265 2.2 120 1.1 l SLOW = 0 SLOW = 1 l l 485 3.3 UNITS µA 10 pF 180 200 190 60 70 120 ns ns ns ns ns ns 55 50 55 55 µs µs ns ns ns ns µs µs µs ns ns ns ns 185 1.4 150 1.4 190 1.4 160 1.4 345 2.8 160 1.4 35 625 4 ns µs ns µs ns µs ns µs ns µs ns µs ns ns µs 1 5 25 25 50 50 0.6 1 1 l SLOW = 0 SLOW = 1 SLOW = 0 SLOW = 1 SLOW = 0 SLOW = 1 SLOW = 0 SLOW = 1 SLOW = 0 SLOW = 1 SLOW = 0 SLOW = 1 MAX ±1 Note 3: The LTC6820I is guaranteed to meet specified performance from –40°C to 85°C. The LTC6820H is guaranteed to meet specified performance from –40°C to 125°C. Note 4: Active supply current (IDD) is dependent on the amount of time that the output drivers are active on IP and IM. During those times IDD will increase by the 20 • IB drive current. For the maximum data rate 1MHz, the drivers are active approximately 10% of the time if MSTR = 1, and 5% 6820f 4 LTC6820 Electrical Characteristics of the time if MSTR = 0. See Applications Information section for more detailed information. Note 5: The IO supply pin, VDDS, provides power for the SPI inputs and outputs, including the EN pin. If the inputs are near 0V or VDDS (to avoid static current in input buffers) and the outputs are not sourcing current, then IDDS includes only leakage current. Note 6: The LTC6820 is guaranteed to meet specifications with RBIAS resistor values ranging from 2k to 20k, with 1% or better tolerance. Those resistor values correspond to a typical IB that can range from 0.1mA (for 20k) to 1mA (for 2k). Note 7: These timing specifications are dependent on the delay through the cable, and include allowances for 50ns of delay each direction. 50ns corresponds to 10m of CAT-5 cable (which has a velocity of propagation of 66% the speed of light). Use of longer cables would require derating these specs by the amount of additional delay. Note 8: These specifications do not include rise or fall time. While fall time (typically 5ns due to the internal pull-down transistor) is not a concern, rising-edge transition time tRISE is dependent on the pull-up resistance and load capacitance. In particular, t12 and t14 require tRISE < 110ns (if SLOW = 0) for the slave’s setup and hold times. Therefore, the recommended time constant is 50ns or less. For example, if the total capacitance on the data pin is 25pF (including self capacitance CI/O of 10pF), the required pull-up resistor value is RPU ≤ 2kΩ. If these requirements can’t be met, use SLOW = 1. Note 9: Guaranteed by design. Not tested in production. Typical Performance Characteristics VDD = VDDS, unless otherwise noted. 5.3 7 VDD = 5V, IB = 1mA VDD = 3V, IB = 1mA 5 4 VDD = 5V, IB = 0.1mA 2 1 MSTR = 1 200 400 600 FREQUENCY (kHz) 800 5.1 VDD = 3V 5.0 4.9 VDD = 3V, IB = 0.1mA 0 VDD = 5V 4.8 –50 1000 –25 50 0 75 25 TEMPERATURE (°C) 3.0 3.0 2.5 2.5 SLAVE (MSTR = 0) 1.5 MASTER (MSTR = 1) 0.5 VIH 2.5 HIGH LOW 2.0 1.5 1.0 VIL 0.5 0 125 ONLY SPI PINS 3.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 100 2.0 SLAVE (MSTR = 0) 1.0 0.5 5.5 Output Resistance vs Supply Voltage (VOH/VOL) VDD = 5V 1.5 5.0 6820 G03 Supply Current (IDLE) vs Temperature SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) Supply Current (IDLE) vs Supply Voltage 1.0 3.5 6820 G02 6820 G01 2.0 100 OUTPUT RESISTANCE (Ω) 3 4.0 IB = 1mA 5.2 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 6 Input Voltage Threshold (Except EN Pin) vs Supply Voltage (VDD or VDDS) Supply Current (READY) vs Temperature INPUT VOLTAGE THRESHOLD (V) Supply Current (READY/ACTIVE) vs Clock Frequency MASTER (MSTR = 1) 80 OUTPUT SOURCING 2mA CURRENT 60 40 20 OUTPUT SINKING 3.3mA CURRENT 0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 6820 G04 0 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 6820 G05 0 1.5 3.5 2.5 4.5 SUPPLY VOLTAGE (V) 5.5 6820 G19 6820f 5 LTC6820 Typical Performance Characteristics IBIAS Voltage vs Temperature IBIAS Voltage Load Regulation 2.010 2.02 2.00 1.98 1.96 –50 IB = 1mA IB = 0.1mA 50 25 0 75 TEMPERATURE (°C) –25 100 125 VDD = 3V 2.005 2.000 1.995 1.990 0.2 0 0.6 0.8 0.4 IBIAS CURRENT (mA) 6820 G07 22.0 20 VDD = 3V IB = 1mA 18 17 22.0 VDD = 5V 20.5 VDD = 3V 20.0 19.5 19.0 5 20.0 DRIVER COMMON MODE (V) CURRENT GAIN (mA/mA) 20.5 IB = 1mA, VDD = 5V IB = 0.1mA, VDD = 3V 19.5 IB = 1mA, VDD = 3V 19.0 0.2 0 0.4 0.8 0.6 IBIAS CURRENT (mA) IB = 1mA 20.0 19.5 19.0 18.0 2.5 1.0 75 50 25 TEMPERATURE (°C) 100 125 6820 G13 3.5 4 4.5 5 VA = 1V Driver Common Mode Voltage vs Pulse Amplitude 5.0 IB = 0.1mA, VDD = 5V 4.5 4 IB = 1mA, VDD = 5V 3 IB = 0.1mA, VDD = 3V 2 IB = 1mA, VDD = 3V 1 0 –50 –25 5.5 6820 G12 IB = 0.1mA, VDD = 5V 4.0 IB = 1mA, VDD = 5V 3.5 3.0 IB = 0.1mA, VDD = 3V 2.5 2.0 1.5 0 3 SUPPLY VOLTAGE (V) 18.5 18.0 –50 –25 IB = 0.1mA 20.5 18.5 21.5 21.0 21.0 Driver Common Mode Voltage vs Temperature VA = 1V 5.5 VA = 1V 6820 G11 Driver Current Gain vs Temperature IB = 0.1mA, VDD = 5V 5 3.5 4 4.5 SUPPLY VOLTAGE (V) 21.5 6820 G10 22.0 3 Driver Current Gain vs Supply Voltage VA = 1V 21.0 18.0 2.0 0.5 1.0 1.5 PULSE AMPLITUDE VA (V) 2.5 6820 G09 18.5 VA(MAX) = 1.3V FOR VDD = 3V 0 1.990 DRIVER COMMON MODE (V) VDD = 3V IB = 0.1mA 19 1.995 CURRENT GAIN (mA/mA) VDD = 5V IB = 0.1mA 21 2.000 21.5 CURRENT GAIN (mA/mA) CURRENT GAIN AIB (mA/mA) 22 IB = 1mA Driver Current Gain vs IBIAS Current (IB) VA(MAX) = 1.6V FOR VDD > 3.3V VDD = 5V IB = 1mA 1.0 IB = 0.1mA 2.005 6820 G08 Driver Current Gain vs Amplitude 23 IBIAS Voltage vs Supply Voltage 2.010 IBIAS PIN VOLTAGE (V) VDD = 3V 3 PARTS IBIAS PIN VOLTAGE (V) IBIAS PIN VOLTAGE (V) 2.04 VDD = VDDS, unless otherwise noted. 50 0 75 25 TEMPERATURE (°C) 100 125 6820 G14 1.0 IB = 1mA, VDD = 3V 0 0.5 1.5 1.0 PULSE AMPLITUDE (V) 2.0 6820 G15 6820f 6 LTC6820 Typical Performance Characteristics Comparator Threshold Gain vs ICMP Voltage Comparator Threshold Gain vs Common Mode 0.52 0.50 0.48 0.44 VDD = 3V VDD = 5V 0 0.2 0.56 0.4 0.6 0.8 1.0 1.2 ICMP VOLTAGE (V) 0.54 0.52 VICMP = 1V VDD = 3V VICMP = 1V VDD = 5V 0.50 0.48 VICMP = 0.2V VDD = 3V VICMP = 0.2V VDD = 5V 0.46 0.44 1.4 1.6 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 COMMON MODE VOLTAGE (V) WAKE-UP PULSE AMPLITUDE, VWAKE (mV) 5.5 0.54 VDD = 3V 3 PARTS 0.52 0.50 0.48 0.46 0.44 –50 VICMP = 1V VICMP = 0.2V –25 50 25 0 75 TEMPERATURE (°C) 6820 G17 6820 G16 Wake-Up Pulse Amplitude vs Dwell Time 300 COMPARATOR THRESHLD GAIN (V/V) 0.54 0.46 Comparator Threshold Gain vs Temperature 0.56 3 PARTS COMPARATOR THRESHLD GAIN (V/V) COMPARATOR THRESHOLD GAIN (V/V) 0.56 VDD = VDDS, unless otherwise noted. 100 125 6820 G18 Start-Up Time VDD = 3V CS 5V/DIV GUARANTEED WAKE-UP REGION 250 3.6µs IBIAS 2V/DIV 200 150 IP-IM 1V/DIV 100 50 0 300 150 450 WAKE-UP DWELL TIME, tDWELL (ns) VDDS = 5V MSTR = 1 RBIAS = 2k 600 6820 G06 1µs/DIV 6820 G20 SPI Signal and isoSPI Pulses, MSTR = 1 SPI Signal and isoSPI Pulses, MSTR = 0 CS 5V/DIV IP-IM 2V/DIV SCK 5V/DIV CS 5V/DIV MOSI 5V/DIV SCK 5V/DIV MIS0 5V/DIV MOSI 5V/DIV IP-IM 2V/DIV MIS0 5V/DIV VDD = 5V VDDS = 3.3V PHA = 1 POL = 1 1.2µs/DIV 6820 G21 VDD = 5V VDDS = 5V PHA = 0 POL = 0 1.2µs/DIV 6820 G22 6820f 7 LTC6820 Pin Functions (QFN/MSOP) MOSI (Pin 1/Pin 2): SPI Master Out/Slave In Data. If connected on the master side of a SPI interface (MSTR pin high), this pin receives the data signal output from the master SPI controller. If connected on the slave side of the interface (MSTR pin low), this pin drives the data signal input to the slave SPI device. The output is open drain, so an external pull-up resistor to VDDS is required. MISO (Pin 2/Pin 3): SPI Master In/Slave Out Data. If connected on the master side of a SPI interface (MSTR pin high), this pin drives the data signal input to the master SPI controller. If connected on the slave side of the interface (MSTR pin low), this pin receives the data signal output from the slave SPI device. The output is open drain, so an external pull-up resistor to VDDS is required. SCK (Pin 3/Pin 4): SPI Clock Input/Output. If connected on the master side of the interface (MSTR pin high), this pin receives the clock signal from the master SPI controller. This input should not be pulled above VDDS. If connected on the slave side of the interface (MSTR pin low), this pin outputs the clock signal to the slave device. The output driver is push-pull; no external pull-up resistor is needed. CS (Pin 4/Pin 5): SPI Chip Select Input/Output. If connected on the master side of the interface (MSTR pin high), this pin receives the chip select signal from the master SPI controller. This input should not be pulled above VDDS. If connected on the slave side of the interface (MSTR pin low), this pin outputs the chip select signal to the slave device. The output driver is push-pull; no external pull-up resistor is needed. VDDS (Pin 5/Pin 6): SPI Input/Output Power Supply Input. The output drivers for the SCK and CS pins use the VDDS input as their positive power supply. The input threshold voltages of SCK, CS, MOSI, MISO and EN are determined by VDDS. May be tied to VDD or to a supply above or below VDD to level shift the SPI I/O. If separate from VDD, connect a bypass capacitor of at least 0.01μF directly between VDDS and GND. POL (Pin 6/Pin 7): SPI Clock Polarity Input. Tie to VDD or GND. See Operation section for details. PHA (Pin 7/Pin 8): SPI Clock Phase Input. Tie to VDD or GND. See Operation section for details. VDD (Pin 8/Pin 9): Device Power Supply Input. Connect a bypass capacitor of at least 0.01μF directly between VDD and GND. IM (Pin 9/Pin 10): Isolated Interface Minus Input/Output. IP (Pin 10/Pin 11): Isolated Interface Plus Input/Output. MSTR (Pin 11/Pin 12): Serial Interface Master/Slave Selector Input. Tie this pin to VDD if the device is on the master side of the isolated interface. Tie this pin to GND if the device is on the slave side of the isolated interface. SLOW (Pin 12/Pin 13): Slow Interface Selection Input. For clock frequencies at or below 200kHz, or if slave devices cannot meet timing requirements, this pin should be tied to VDD. For clock frequencies above 200kHz, this pin should be tied to GND. GND (Pin 13/Pin 14): Device Ground. ICMP (Pin 14/Pin 15): Isolated Interface Comparator Voltage Threshold Set. Tie this pin to the resistor divider between IBIAS and GND to set the voltage threshold of the interface receiver comparators. The comparator thresholds are set to 1/2 the voltage on the ICMP pin. IBIAS (Pin 15/Pin 16): Isolated Interface Current Bias. Tie IBIAS to GND through a resistor divider to set the interface output current level. When the device is enabled, this pin is approximately 2V. When transmitting pulses, the sink current on each of the IP and IM pins is set to 20 times the current sourced from pin IBIAS to GND. Limit the capacitance on the IBIAS pin to less than 50pF to maintain the stability of the feedback circuit regulating the IBIAS voltage. EN (Pin 16/Pin 1): Device Enable Input. If high, this pin forces the LTC6820 to stay enabled, overriding the internal IDLE mode function. If low, the LTC6820 will go into IDLE mode after the CS pin has been high for 5.7ms (when MSTR pin is high) or after no signal on the IP/IM pins for 5.7ms (when MSTR pin is low). The LTC6820 will wake-up less than 8µs after CS falls (MSTR high) or after a signal is detected on IP/IM (MSTR low). Exposed Pad (Pin 17, QFN Package Only): Exposed pad may be left open or connected to device GND. 6820f 8 LTC6820 SLOW POL PHA VDDS VDDS EN RPU (TO MOSI IF MSTR = 0) MOSI (TO MISO IF MSTR = 1) MISO SCK CS IB IBIAS RB1 ICMP LOGIC MSTR IDLE TIMEOUT 2V WAKE DETECT READY RBIAS = RB1 + RB2 VDD VICMP + 167mV 3 OPEN WHEN IDLE RB2 + – 35k 35k PULSE QUALIFICATION 0.1µF EN CS Rx = +1 + THRESHOLD Rx = –1 Tx = –1 0.5x – Tx = +1 TIMING VDD VDDS-POWERED SPI PIN TRANSLATION VDD VDD-POWERED CONFIGURATION INPUTS Block Diagram IP IDRV GND RM IM Tx • 20 • IB 6820 BD Operation The LTC6820 creates a bidirectional isolated serial port interface (isoSPI) over a single twisted pair of wires, with increased safety and noise immunity over a nonisolated interface. Using transformers, the LTC6820 translates standard SPI signals (CS, SCK, MOSI and MISO) into pulses that can be sent back and forth on twisted-pair cables. The receiver consists of a window comparator with a differential voltage threshold, VTCMP. When VIP – VIM is greater than +VTCMP, the comparator detects a logic +1. When VIP – VIM is less than –VTCMP, the comparator detects a logic –1. A logic 0 (null) indicates VIP – VIM is between the positive and negative thresholds. A typical system uses two LTC6820 devices. The first is paired with a microcontroller or other SPI master. Its IP and IM transmitter/receiver pins are connected across an isolation barrier to a second LTC6820 that reproduces the SPI signals for use by one or more slave devices. The comparator outputs are sent to pulse timers (filters) that discriminate between short and long pulses. The transmitter is a current-regulated differential driver. The voltage amplitude is determined by the drive current and the equivalent resistive load (cable characteristic impedance and termination resistor, RM). Selecting Bias Resistors The adjustable signal amplitude allows the system to trade power consumption for communication robustness, and the adjustable comparator threshold allows the system to account for signal losses. 6820f 9 LTC6820 Operation ISOLATION BARRIER MSTR MASTER SDO SDI SCK CS IP LTC6820 IM MOSI MISO IBIAS SCK CS ICMP IP RM RB1 RM TWISTED-PAIR CABLE WITH CHARACTERISTIC IMPEDANCE RM MSTR IM IBIAS RB1 ICMP RB2 SLAVE LTC6820 MOSI MISO SCK CS SDI SDO SCK CS RB2 6820 F01 Figure 1. Typical System Using Two LTC6820 Devices The transmitter drive current and comparator voltage threshold are set by a resistor divider (RBIAS = RB1 + RB2) between the IBIAS pin and GND, with the divided voltage tied to the ICMP pin. When the LTC6820 is enabled (not IDLE), IBIAS is held at 2V, causing a current, IB, to flow out of the IBIAS pin. The IP and IM pin drive currents are 20 • IB. The comparator threshold is half the voltage on the ICMP pin (VICMP). As an example, if divider resistor RB1 is 1.21k and resistor RB2 is 787Ω (so that RBIAS = 2k), then: IB = 2V = 1mA RB1 +RB2 IDRV = IIP = IIM = 20 • IB = 20mA VICMP = 2V • RB2 =I •R = 788mV RB1 +RB2 B B2 VTCMP = 0.5 • VICMP = 394mV In this example, the pulse drive current IDRV will be 20mA, and the receiver comparators will detect pulses with IP-IM amplitudes greater than ±394mV. If the isolation barrier uses 1:1 transformers connected by a twisted pair and terminated with 100Ω resistors on each end, then the transmitted differential signal amplitude (±) will be: VA =IDRV • RM = 1V 2 (This result ignores transformer and cable losses, which will reduce the amplitude). isoSPI Pulse Detail The isoSPI transmitter can generate three voltage levels: +VA, 0V, and –VA. To eliminate the DC signal component and enhance reliability, isoSPI pulses are defined as symmetric pulse pairs. A +1 pulse pair is defined as a +VA pulse followed by a –VA pulse. A –1 pulse pair is –VA followed by +VA. The duration of each pulse is defined as t1/2PW. (The total isoSPI pulse duration is 2 • t1/2PW). The LTC6820 allows for two different t1/2PW values so that four types of pulses can be transmitted, as listed in Table 1. Table 1. isoSPI Pulse Types PULSE TYPE Long +1 Long –1 Short +1 Short –1 FIRST LEVEL +VA (150ns) –VA (150ns) +VA (50ns) –VA (50ns) SECOND LEVEL –VA (150ns) +VA (150ns) –VA (50ns) +VA (50ns) ENDING LEVEL 0V 0V 0V 0V Long pulses are used to transmit CS changes. Short pulses transmit data (MOSI or MISO). An LTC6820 detects four types of communication events from the SPI master: CS falling, CS rising, SCK latching MOSI = 0, and SCK latching MOSI = 1. It converts each event into one of the four pulse types, as shown in Table 2. Table 2. Master Communication Events SPI MASTER EVENT CS Rising CS Falling SCK Latching Edge, MOSI = 1 SCK Latching Edge, MOSI = 0 TRANSMITTED PULSE Long +1 Long –1 Short +1 Short –1 6820f 10 LTC6820 Operation On the other side of the isolation barrier (i.e., the other end of the cable) another LTC6820 is configured to interface with a SPI slave. It receives the transmitted pulses and reconstructs the SPI signals on its output port, as shown in Table 3. In addition, the slave device may transmit a return data pulse to the master to set the state of MISO. See isoSPI Interaction and Timing for additional details. Table 3. Slave SPI Port Output RECEIVED PULSE SPI PORT ACTION RETURN PULSE Long +1 Drive CS High None Long –1 Drive CS Low Short +1 1. Set MOSI = 1 2. Pulse SCK Short –1 Setting Clock Phase and Polarity (PHA and POL) (No Return Pulse if MISO = 1) A slave LTC6820 never transmits long (CS) pulses. Furthermore, a slave will only transmit a short –1 pulse (when MISO = 0), never a +1 pulse. This allows for multiple slave devices on a single cable without risk of collisions (see Multidrop section). isoSPI Pulse Specifications Figure 2 details the timing specifications for the +1 and –1 isoSPI pulses. The same timing specifications apply to either version of these symmetric pulses. In the Electrical +1 PULSE A valid pulse must meet the minimum spec for t1/2PW and the maximum spec for tINV. In other words, the half-pulse width must be long enough to pass through the appropriate pulse timer, but short enough for the inversion to begin within the valid window of time. The response observed at MOSI, MISO or CS will occur after delay tDEL from the pulse inversion. Short –1 Pulse if MISO = 0 1. Set MOSI = 0 2. Pulse SCK Characteristics table, these specifications are further separated into CS (long) and Data (short) parameters. SPI devices often use one clock edge to latch data and the other edge to shift data. This avoids timing problems associated with clock skew. There is no standard to specify whether the shift or latch occurs first. There is also no requirement for data to be latched on a rising or falling clock edge, although latching on the rising edge is most common. The LTC6820 supports all four SPI operating modes, as configured by the PHA and POL Pins. Table 4. SPI Modes MODE POL PHA 0 0 0 SCK Idles Low, Latches on Rising (1st) Edge 1 0 1 SCK Idles Low, Latches on Falling (2nd) Edge 2 1 0 SCK Idles High, Latches on Falling (1st) Edge 3 1 1 SCK Idles High, Latches on Rising (2nd) Edge VA VTCMP VIP – VIM –VTCMP –VA t1/2PW t1/2PW tINV tDEL MOSI, MISO OR CS –1 PULSE DESCRIPTION VA VTCMP VIP – VIM –VTCMP tINV t1/2PW t1/2PW tDEL –VA MOSI, MISO OR CS 6820 F02 Figure 2. isoSPI Differential Pulse Detail 6820f 11 LTC6820 Operation If POL = 0, SCK idles low. Data is latched on the rising (first) clock edge if PHA = 0 and on the falling (second) clock edge if PHA = 1. If POL =1, SCK idles high. Data is latched on the falling (first) clock edge if PHA = 0 and on the rising (second) clock edge if PHA = 1. The two most common configurations are mode 0 (PHA = 0 and POL = 0) and mode 3 (PHA = 1 and POL = 1) because these modes latch data on a rising clock edge. isoSPI Interaction and Timing The timing diagrams in Figures 3 and 4 show how an isoSPI in master mode (connected to a SPI master) interacts with an isoSPI in slave mode (connected to a SPI slave). Figure 3 details operation with PHA = 0 (and shows SCK signals for POL = 0 or 1). Figure 4 provides the timing diagram for PHA = 1. Although not shown, it is acceptable to use different SPI modes (PHA and POL settings) on the master and slave devices. A master SPI device initiates communication by lowering CS. The LTC6820 converts this transition into a Long –1 pulse on its IP/IM pins. The pulse traverses the isolation barrier (with an associated cable delay) and arrives at the IP/IM pins of the slave LTC6820. Once validated, the Long –1 pulse is converted back into a falling CS transition, this time supplied to the slave SPI device. If slave PHA = 1, SCK will also leave the idle state at this time. Before the master SPI device supplies the first latching clock edge (usually a rising edge, but see Table 4 for exceptions), the slave LTC6820 must transmit the initial slave data bit SN, which it determines by sampling the state of MISO after a suitable delay. If MISO = 0, the slave will transmit a Short –1 pulse to the master. The master LTC6820 will receive and decode the pulse and set the master MISO = 0 (matching the slave). However, if the slave MISO=1, the slave does not transmit a pulse. The master will interpret this null response as a 1 and set the master MISO = 1. This makes it possible to connect multiple slave LTC6820’s to a single cable with no conflicting signals (see Multidrop section). After the falling CS sequence, every latching clock edge on the master converts the state of the MOSI pin into an isoSPI data pulse (MN, MN–1, … M0) while simultaneously latching the slave’s data bit. As the slave LTC6820 receives each data bit it will set the slave MOSI pin to the proper state and then generate an SCK pulse before returning the slave’s MISO data (either as a Short –1 pulse, or as a null). At the end of communication, the final data bit sent by the slave (either as a pulse or null) will be ignored by the master controller. (The slave LTC6820 must return a data bit since it cannot predict when communications will cease.) The master SPI device can then raise CS, which is transmitted to the slave in the form of a Long +1 pulse. The process ends with the slave LTC6820 transitioning CS high, and returning SCK to the idle state if PHA = 1. Rise Time MOSI and MISO outputs have open-drain drivers. The rise time tRISE for the data output is determined by the pull-up resistance and load capacitance. RPU must be small enough to provide adequate setup and hold times. Slow Mode When configured for slave operation, the LTC6820 provides two operating modes to ensure compatibility with a wide range of SPI timing scenarios. These modes are referred to as fast and slow mode, and are set using the SLOW pin. When configured for master operation, the SLOW pin setting has no effect on the LTC6820 operation. In this case, it is recommended to tie the SLOW pin to GND. In fast mode (SLOW pin tied to GND), the LTC6820 can operate at clock rates up to 1MHz (tCLK = 1µs). However, some SPI slave devices can’t respond quickly enough to support this data rate. Fast mode requires a slave to operate with setup and response times of 100ns, as well as 100ns clock widths. In addition, allowances must be made for the RC rise time of MOSI and MISO’s open-drain outputs. In slow mode (SLOW pin tied to V+), the timing requirement are relaxed at the expense of maximum data rate. As indicated in the Electrical Characteristics, the clock pulses and required setup and response times are increased to 0.9µs minimum. Accordingly, the minimum tCLK (controlled by the master) must be limited to 5µs. The SLOW pin setting has no effect on the master LTC6820 (with MSTR = 1). 6820f 12 MISO MOSI SCK (POL = 1) SCK (POL = 0) CS ISO ISO MISO MOSI SCK (POL = 1) SCK (POL = 0) CS 0 SN t9 SAMPLE tDEL(CS) t16 500 CSB = 0 t10 t7 1000 t1 t2 MN t4 tDEL(D) 2000 tRISE tDEL(D) SAMPLE SN-1 t3 MN-1 t12 2500 TIME (ns) t13 t14 SAMPLE SN-2 3000 SLAVE DOES NOT TRANSMIT +1 M0 Figure 3. Transceiver Timing Diagram (PHA = 0) 1500 tRTN t8 tRISE tCLK 3500 t6 4000 tDEL(CS) IGNORED t10 t11 t18 4500 CSB = 1 t5 6820 F03 5000 LTC6820 Operation 6820f 13 14 MISO MOSI SCK (POL = 0) SCK (POL = 1) CS ISO ISO MISO MOSI SCK (POL = 0) SCK (POL = 1) CS 0 SN t9 SAMPLE tDEL(CS) t16 500 t15 CSB = 0 t10 t7 1000 t1 t2 MN t4 t8 2000 tRISE tDEL(D) SAMPLE SN-1 t3 MN-1 t12 TIME (ns) 2500 t13 t14 tDEL(D) SAMPLE SN-2 3000 t6 3500 SLAVE DOES NOT TRANSMIT +1 MO Figure 4. Transceiver Timing Diagram (PHA = 1) 1500 tRTN tRISE tCLK 4000 tDEL(CS) IGNORED t10 t11 t18 4500 t17 CSB = 1 t5 6820 F04 5000 LTC6820 Operation 6820f LTC6820 Operation Figure 6 demonstrates slow mode, as compared to fast mode in Figure 5. IP-IM 2V/DIV SCK 5V/DIV VDD VDD + – VICMP + 167mV 3 OPEN WHEN IDLE POS IP MOSI 5V/DIV 35k MISO 5V/DIV 35k RM VDD = 5V VDDS = 5V 200ns/DIV 6820 F05 IM NEG POS NEG Figure 5. Fast Mode (SLOW = 0) 20 • IB VIP – VIM IP-IM 2V/DIV SCK 5V/DIV 6820 F07 Figure 7. Pulse Driver 25 VDD = 5V VDDS = 5V 1µs/DIV 6820 F06 Figure 6. Slow Mode (SLOW = 1) IP and IM Pulse Driver The IP and IM pins transmit and receive the isoSPI pulses. The transmitter uses a current-regulated driver (see Figure 7) to establish the pulse amplitude, as determined by the IBIAS pin current, IB, and the load resistance. The sinking current source is regulated to 20x the bias current IB. The sourcing current source operates in a current-starved (resistive) manner to maintain the sourcing pin’s voltage near VDD, as shown in Figures 8 and 9. The common mode voltage (while driving) is dependent on bias current and output amplitude. The output driver will regulate the common mode and peak swing of IP and IM to the proper levels, allowing for a broad range of output amplitude with fairly flat gain, as shown in Figure 10. SOURCING OUTPUT 20 1V AMPLITUDE 15 SINKING OUTPUT 10 5 0 VDD = 3V IB = 1mA 0 1 1.5 2 VIP OR VIM (V) 0.5 2.5 3 6820 F08 Figure 8. Drive Source/Sink vs Output Voltage 3.0 SOURCING OUTPUT 2.5 OUTPUT VOLTAGE (V) MISO 5V/DIV SOURCE/SINK CURRENT (mA) MOSI 5V/DIV 2.0 VCM 1.5 1.0 SINKING OUTPUT 0.5 0 VDD = 3V IB = 1mA 0 0.5 1 1.5 2 PULSE AMPLITUDE (V) 2.5 3 6820 F09 Figure 9. Output Voltages and Common Mode vs Amplitude 6820f 15 LTC6820 Operation 25 3.0 TRANSMIT SHORT +1 20 2.0 15 VOLTAGE (V) CURRENT GAIN (mA/mA) 2.5 10 IM RECEIVE SHORT –1 1.0 0.5 IP-IM 0 –0.5 5 0 IP 1.5 VDD = 3V IS = 1mA 0 0.5 VDD = 3V IB = 1mA –1.0 1 1.5 2 PULSE AMPLITUDE (V) 2.5 3 –1.5 0 200 6820 F10 Figure 10. AIB Current Gain vs Amplitude 6820 F11 Figure 11. Transmitting and Receiving Data This type of driver does not require a center-tapped transformer, but such a transformer may improve noise immunity, especially if it has a common mode choke. See the Applications Information section for additional details. IDLE IDLE TIMEOUT (tIDLE) Receiver Common Mode Bias When not transmitting, the output driver maintains IP and IM near VDD with a pair of 35k (RIN) resistors to a voltage of VDD – VICMP/3 – 167mV. This weak bias network holds the outputs near their desired operating point without significantly loading the cable, which allows a large number of LTC6820’s to be paralleled without affecting signal amplitude. Figure 11 shows the differential and single-ended IP and IM signals while transmitting and receiving data. The driver forces the common mode voltage it needs while transmitting, then it returns to the bias level with a time constant of RIN • CLOAD/2, where CLOAD is the sum of the capacitance at the IP and IM pins. When the LTC6820 is in low power IDLE mode, the bias voltage is disconnected from the 35k resistors, resulting in a 70k differential load. State Diagram During periods of no communication, a low current IDLE (or shutdown) state is available to reduce power. In the IDLE state the LTC6820 shuts down most of the circuitry. A slave device uses a low current comparator to monitor for activity, so it has larger IDLE current. 1000 800 600 400 TIME (ns) WAKE-UP SIGNAL (tREADY) READY NO ACTIVITY ON isoSPI PORT TRANSMIT/RECEIVE ACTIVE 6820 F12 Figure 12. State Diagram In the READY state all circuitry is enabled and ready to transmit or receive, but is not actively transmitting on IP and IM. Supply current increases when actively communicating, so this condition is referred to as the ACTIVE state. Supply Current Table 5 provides equations for estimating IDD in each state. The results are for average supply current (as opposed to peak currents), and make the assumption that a slave is returning an equal number of 0s and 1s (significant because the slave doesn’t generate +1 data pulses, so the average driver current is smaller). 6820f 16 LTC6820 Operation Table 5. IDD Equations STATE IDLE MSTR ESTIMATED IDD 0 (slave) 2µA 1 (master) 1µA READY 0 or 1 ACTIVE 0 (slave) 1 (master) 1.7mA + 3 • IB 100ns • 0.5 2mA + 3+ 20 • •I tCLK B 100ns 2mA + 3+ 20 • •I tCLK B IDLE Mode and Wake-Up Detection To conserve power, an LTC6820 in slave mode (MSTR = 0) will enter an IDLE state after 5.7ms (tIDLE) of inactivity on the IP/IM pins. In this condition IDD is reduced to less than 6µA and the SPI pins are idled (CS = 1, MOSI = 1 and SCK = POL). Figure 15 demonstrates a simple procedure for waking a master (MSTR = 1) LTC6820 and its connected slave (MSTR = 0). A negative edge on CS causes the master to drive IBIAS to 2V and, after a short delay, transmit a long +1 pulse. (If CS remains low throughout tREADY, the LTC6820 would first generate a –1 pulse, then the +1 pulse when CS returns high). The long pulse serves as a wake-up signal for the slave device, which responds by driving its IBIAS pin to 2V and entering the READY state. 240mV A LTC6820 in master mode (MSTR = 1) doesn’t use the wake-up detection comparator. A falling edge on CS will enable the isoSPI port within tREADY, and the LTC6820 will transmit a long (CS) pulse as it leaves the IDLE state. (The polarity of the pulse matches the CS state at the end of tREADY). The master LTC6820 will remain in the READY/ACTIVE state as long as CS = 0. If CS transitions high and EN = 0 it will enter the IDLE state, but not until tIDLE expires. This prevents the device from shutting down between data packets. In either master or slave mode the IDLE feature may be disabled by driving EN high. This forces the device to remain “ready” at all times. 240ns DELAY (FILTER) |IPAC–IMAC| > 240mV 240ns IM SLAVE IMAC MASTER CS WAKE-UP The LTC6820 will continue monitoring the IP and IM pins using a low power AC-coupled detector. It will wake up when it sees a differential signal of 240mV or greater that persists for 240ns or longer. In practice, a long (CS) isoSPI pulse is sufficient to wake the device up. Once the comparator generates the wake-up signal it can take up to 8µs (tREADY) for bias circuits to stabilize. Figure 14 details the sequence of waking up a slave LTC6820 (placing it in the READY state), using it to communicate, then allowing it to return to the low power IDLE state. IPAC IP IDLE TIMER EN tREADY READY (IBIAS = 2V) tIDLE 6820 F13 Figure 13. Wake-Up Detection and IDLE Timer REJECTS COMMON MODE NOISE IP IM IP-IM READY tDWELL tIDLE tREADY OK TO COMMUNICATE 6820 F14 Figure 14. Slave LTC6820 Wake-Up/Idle Timing ALLOW >2 • tREADY TO WAKE MASTER AND SLAVE MASTER CS MASTER IBIAS tIDLE tREADY IP-IM tDWELL SLAVE IBIAS tREADY tIDLE SLAVE CS 6820 F15 Figure 15. Master and Slave Wake-Up/Idle Sequence 6820f 17 LTC6820 Operation Multidrop The SPI slaves must be addressable, because they will all see the same CS signal (as decoded by each slave LTC6820). n Multiple slaves can be connected to a single master by connecting them in parallel (multidrop configuration)along one cable. As shown in Figure 16, the cable should be terminated only at the beginning (master) and the end. In between, the additional LTC6820’s and their associated slave devices will be connected to “stubs” on the cable. These stubs should be kept short, with as little capacitance as possible, to avoid degrading the termination along the cable. When not addressed, the slave SDO must remain high. n When a slave is not addressed, its LTC6820 will not transmit data pulses as long as MISO (the SPI device’s SDO) remains high. This eliminates the possibility for collisions, as only the addressed slave device will ever be returning data to the master. The multidrop scheme is only possible if the SPI slaves have certain characteristics: MASTER SDO SDI SCK CS LTC6820 LTC6820 MSTR MOSI IP MISO SCK IM CS IP MSTR MOSI MISO IM SCK CS RM SLAVE 1 1 SDI SDO SCK CS 1 1 LTC6820 IP MSTR MOSI MISO IM SCK CS SLAVE 2 2 SDI SDO SCK CS 2 2 LTC6820 IP RM MSTR MOSI MISO IM SCK CS 3 SLAVE 3 3 SDI SDO SCK CS 3 6820 F16 Figure 16. Multidropping Multiple Slaves on a Single Cable 6820f 18 LTC6820 Applications Information isoSPI Setup For cables over 50 meters: The LTC6820 allows each application to be optimized for power consumption or for noise immunity. The power and noise immunity of an isoSPI system is determined by the programmed IB current. The IB current can range from 0.1mA to 1mA. A low IB reduces the isoSPI power consumption in the READY and ACTIVE states, while a high IB increases the amplitude of the differential signal voltage VA across the matching termination resistor, RM. IB = 1mA IB is programmed by the sum of the RB1 and RB2 resistors connected between the IBIAS pin and GND. For most applications setting IB to 0.5mA is a good compromise between power consumption and noise immunity. Using this IB setting with a 1:1 transformer and RM = 120Ω, RB1 should be set to 2.8k and RB2 set to 1.2k. In a typical CAT5 twisted pair these settings will allow for communication up to 50m. For applications that require cables longer than 50m it is recommended to increase the amplitude VA by increasing IB to 1mA. This compensates for the increased insertion loss in the cable and maintains high noise immunity. So when using cables over 50m and, again, using a transformer with a 1:1 turns ratio and RM = 120Ω, RB1 would be 1.4k and RB2 would be 600Ω. Other IB settings can be used to reduce power consumption or increase the noise immunity as required by the application. In these cases when setting VICMP and choosing RB1 and RB2 resistor values the following rules should be used: VA = (20 • IB) • (RM/2) VTCMP = 1/4 • VA VICMP = 2 • VTCMP RB2 = VICMP/IB 2V RB1 = –RB2 IB The maximum data rate of an isoSPI link is determined by the length of the cable used. For cables 10 meters or less the maximum 1MHz SPI clock frequency is possible. As the length of the cable increases the maximum possible SPI clock rate decreases. This is a result of the increased propagation delays through the cable creating possible timing violations. Cable delay affects three timing specifications, tCLK, t6, and t7. In the Electrical Characteristics table, each is derated by 100ns to allow for 50ns of cable delay. For longer cables, the minimum timing parameters may be calculated as shown below: tCLK, t6, and t7 > 0.9µs + 2 • tCABLE Pull-Up Resistance Considerations VA = (20 • IB) • (RM/2) The data output (MOSI if MSTR = 0, MISO if MSTR = 1) requires a pull-up resistor, RPU. The rise time tRISE is determined by RPU and the capacitance on the pin. RPU must be small enough to provide adequate setup and hold times. For a slave device, the time constant must be less than t12 and t14. In fast mode, 50ns is recommended. VTCMP = 1/2 • VA RPU < 50ns/CLOAD VICMP = 2 • VTCMP Larger pull-up resistances, up to 5k, can be used in slow mode. For cables 50 meters or less: IB = 0.5mA RB2 = VICMP/IB 2V RB1 = –RB2 IB 6820f 19 LTC6820 Applications Information Table 6. Typical RB1 and RB2 Values MAX CABLE LENGTH TURNS RATIO TERMINATION RESISTANCE IB VA VTCMP VICMP RB2 RB1 IDRV READY CURRENT 100m 1 :1 120Ω 1mA 1.2V 0.3V 0.6V 604Ω 1.4k 20mA 4.7mA 50m 1 :1 120Ω 0.5mA 0.6V 0.3V 0.6V 1.21k 2.8k 10mA 3.2mA 100m 1 :1 75Ω 1mA 0.75V 0.19V 0.38V 374Ω 1.62k 20mA 4.7mA 50m 1 :1 75Ω 0.5mA 0.375V 0.19V 0.38V 750Ω 3.24k 10mA 3.2mA Transformer Selection Guide As shown in Figure 1, a transformer or a pair of transformers are used to isolate the IP and IM signals between the two LTC6820’s. The isoSPI signals have programmable pulse amplitudes up to 1.6V, and pulse widths of 50ns and 150ns. To meet these requirements, choose a transformer having a magnetizing inductance ranging from 50µH to 350µH, and a 1:1 or 2:1 turns ratio. Minimizing transformer insertion loss will reduce required transmit power; generally an insertion loss of less than –1.5dB is recommended. For optimal common mode noise rejection, choose a centertapped transformer or a transformer with an integrated common mode choke. The center tap can be tied to a 27pF or smaller capacitor (larger will restrict the driver’s ability to set the common mode voltage). If the transformer has both a center tap and common mode choke on the primary side, a larger capacitor may be used. Table 7 shows a recommended list of transformers for use with the LTC6820. 10/100BaseTX Ethernet transformers are inexpensive and work very well in this application. Ethernet transformers often include a common mode choke, which will improve common mode rejection as compared to other transformers. Table 7. Recommended Transformers MANUFACTURER PART NUMBER ISOLATION VOLTAGE TURNS RATIO CENTER TAP CM CHOKE PCA EPF8119SE 1500VRMS 1:1 Yes Yes Halo TG110-AE050N5LF 1500VRMS 1:1 Yes Yes Pulse PE-68386NL 1500V DC 1:1 No No Murata 78613/3C 1000VRMS 1:1 Yes No Murata 78604/3C 1000VRMS 2:1 No No Pulse HX1188NL 1500VRMS 1:1 Yes Yes EPCOS B82804A0354A110 1500V DC 1:1 No No µC SDO SDI SCK CS µC SDO SDI SCK CS 2:1 Transformers LTC6820 MSTR MOSI IP MISO SCK IM CS 2:1 1:2 480Ω IP 480Ω Single-Transformer Isolation LTC6820 MSTR MOSI IP MISO SCK IM CS LTC6820 MOSI MISO IM SCK CS LTC6820 IP 120Ω 120Ω LTC2452 MSTR SDO SCK CS LTC6802 MSTR MOSI MISO IM SCK CS SDI SDO SCK CS 6820 F17 Figure 17. Alternative Isolation Barriers 20 6820f LTC6820 Applications Information Capacitive Isolation Barrier use a transformer with a center tap and a common mode choke as shown in Figure 19. The center tap of the transformer should be bypassed with a 27pF capacitor. The center tap capacitor will help attenuate common mode signals. Large center tap capacitors should be avoided as they will prevent the isoSPI transmitters common mode voltage from settling. In some applications, where the environment is relatively noise free and only galvanic isolation is required, capacitors can be used in place of transformers as the isolation barrier. With capacitive coupling, the twisted pair cable is driven by a voltage and is subject to signal loss with cable length. This low cost isolated solution can be suitable for short distance interconnections (1 meter or less), such as between adjacent circuit boards or across a large PCB. The capacitors will provide galvanic isolation, but no common mode rejection. This option uses the drivers in a different way, by using pull up resistors to maintain the common mode near VDD, only the sinking drive current has any effect. Figure 18 shows an example application circuit using a capacitive isolation barrier capable of driving 1 meter of cable. MANUFACTURER PART NUMBER Murata GCM188R72A104KA64 CAPACITANCE VOLTAGE RATING 100nF 100V To improve common mode current rejection a common mode choke should also be placed in series with the IP and IM lines of the LTC6820. The common mode choke will both increase EMI immunity and reduce EMI emission. When choosing a common mode choke, the differential mode impedance should be 20Ω or less for signals 50MHz and below. Generally common mode chokes similiar to those used in Ethernet applications are recommended. Table 8. Recommended Common Mode Chokes MANUFACTURER PART NUMBER TDK EMC DIFFERENTIAL COMMON MODE IMPEDANCE AT IMPEDANCE AT 50MHz 50MHz ACT45B-220-2P 20Ω 5000Ω When using the LTC6820, for the best electromagnetic compatibility (EMC) performance it is recommended to Capacitive Isolation µC SDO SDI SCK CS LTC6820 LTC6820 MSTR 100nF MSTR MOSI IP MISO SCK IM CS LTC2640 IP MOSI MISO SDI IM SCK CS SCK CS 100nF 6820 F18 Figure 18. Capacitive Isolation Barrier LTC6820 IP IM 27pF 120Ω 6820 F19 Figure 19. Connection of Transformer and Common Mode Choke 6820f 21 LTC6820 Applications Information Layout of the isoSPI signal lines also plays a significant role in maximizing the immunity of a circuit. The following layout guidelines should be followed: 1. The transformer should be placed as close to the isoSPI cable connector as possible. The distance should be kept less than 2cm. The LTC6820 should be placed at least 1cm to 2cm away from the transformer to help isolate the IC from the magnetic coupling fields. 2. On the top layer, no ground plane should be placed under the magnetic, the isoSPI connector, or in between the transformer and the connector. 3. The IP and IM traces should be isolated from surrounding circuits. No traces should cross the IP and IM lines, unless separated by a ground plane within the printed circuit board. The isoSPI drive currents are programmable and allow for a tradeoff between power consumption and noise immunity. The noise immunity of the LTC6820 has been evaluated using a bulk current injection (BCI) test. The BCI test injects current into the twisted-pair lines at set levels over a frequency range of 1MHz to 400MHz. With the minimum IB current, 0.1mA, the isoSPI serial link has been shown to pass a 40mA BCI test with no bit errors. A 40mA BCI test level is sufficient for most industrial applications. Automotive applications tend to have a higher BCI requirement so the recommended IB is set to 1mA, the maximum power level. The isoSPI system has been shown to pass a 200mA BCI test with no transmitted bit errors. The 200mA test level is typical for automotive testing. Software Layer The isoSPI physical layer has high immunity to EMI and is not particularly susceptible to bit errors induced by noise, but for best results in a high noise environment it is recommended to implement a software layer that uses an error detection code like a cyclic redundancy check or check sum. Error detection codes will allow software detection of any bit error and will notify the system to retry the last erroneous serial communication. 1.5cm 1cm IP IM CONNECTOR 6820 F20 Figure 20. Example Layout 6820f 22 LTC6820 Typical Applications Remote Sensor Monitor with Micropower Shutdown LTC6820 IBIAS ICMP VDDS GND SLOW VDD MSTR POL MISO PHA MOSI SCK IP CS IM EN 5V 100nF 2k 2.8k 1.21k 1.21k 2.8k 5V 100nF 120Ω 1 16 1 16 2 15 2 15 3 14 3 14 HX1188NL LTC6820 IBIAS ICMP GND SLOW MSTR IP IM PHA POL VDD 120Ω HX1188NL LT6656-3 + 100nF EN CS SCK MISO MOSI VDDS 3V 1µF 3.6V + IN+ VREF VCC MISO LTC2452 TO SENSOR – SCK CS IN– 6820 TA02 IQ SHUTDOWN = 3.7µA 100 Meter Remote DAC Control LTC6820 IBIAS ICMP VDDS GND SLOW VDD MSTR POL MISO PHA MOSI SCK IP CS IM EN 3V 100nF 2k 1.4k 604Ω 604Ω 1.4k 5V 100nF 120Ω 1 16 1 16 2 15 2 15 3 14 3 14 HX1188NL LTC6820 IBIAS ICMP GND SLOW MSTR IP IM PHA POL VDD 120Ω HX1188NL LT6656-3 + 100nF EN CS SCK MISO MOSI 2k VDDS 3V 1µF 3.6V VREF VCC SDI VOUT OUT LTC2640 SCK CS GND 6820 TA03 6820f 23 LTC6820 Typical Applications Interfacing to Addressable Stack of LTC6804-2 Multicell Battery Monitors LTC6804-2 VREG ISOMD A3 A2 A1 IBIAS A0 2 IPA ICMP IMA VM 120Ω 806Ω 1.21k 2 LTC6804-2 VREG ISOMD A3 A2 A1 IBIAS A0 1 IPA ICMP IMA VM 806Ω 1.21k LTC6820 IBIAS ICMP VDDS GND SLOW VDD MSTR POL MISO PHA MOSI SCK IP CS IM EN 5V 100nF 2k 806Ω 1 1.21k LTC6804-2 VREG ISOMD A3 A2 A1 IBIAS A0 5V 100nF 0 IPA ICMP IMA VM 120Ω 806Ω 1.21k 6820 TA05 0 6820f 24 LTC6820 Typical Applications Battery Monitoring System Using a Multidrop isoSPI Link LTC6803-2 1.21k GND3 806Ω VDD3 LTC6820 IBIAS ICMP GND SLOW MSTR EN MOSI MISO SCK CS IP IM VDD VDDS POL PHA A3 A2 A1 A0 GND3 MOSI MISO SCK CS VSTACK3 GND3 100Ω VREG CZT3055 2k 120Ω 2k VDD3 LTC6803-2 1.21k GND2 806Ω VDD2 LTC6820 IBIAS ICMP GND SLOW MSTR GND2 EN MOSI MISO SCK CS MOSI MISO SCK CS A3 A2 A1 A0 VSTACK2 GND2 100Ω VREG CZT3055 2k IP IM VDD 5V 100nF 2k LTC6820 EN IBIAS ICMP VDDS GND SLOW VDD MSTR POL MISO PHA MOSI SCK IP CS IM VDDS POL PHA 2k VDD2 LTC6803-2 806Ω 1.21k 806Ω 1.21k 5V 100nF GND1 VDD1 LTC6820 IBIAS ICMP GND SLOW MSTR EN MOSI MISO SCK CS IP IM VDD VDDS POL PHA GND1 MOSI MISO SCK CS A3 A2 A1 A0 VREG VSTACK1 GND1 100Ω CZT3055 2k 120Ω 2k VDD1 6820 TA04 6820f 25 LTC6820 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UD Package 16-Lead Plastic QFN (3mm × 3mm) (Reference LTC DWG # 05-08-1700 Rev A) Exposed Pad Variation AA 0.70 ±0.05 3.50 ±0.05 1.65 ±0.05 2.10 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ±0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.20 TYP OR 0.25 × 45° CHAMFER R = 0.115 TYP 0.75 ±0.05 15 PIN 1 TOP MARK (NOTE 6) 16 0.40 ±0.10 1 1.65 ±0.10 (4-SIDES) 2 (UD16 VAR A) QFN 1207 REV A 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-4) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 ±0.05 0.50 BSC 6820f 26 LTC6820 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 16-Lead Plastic MSOP (Reference LTC DWG # 05-08-1669 Rev Ø) 0.889 ±0.127 (.035 ±.005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 4.039 ±0.102 (.159 ±.004) (NOTE 3) 0.50 (.0197) BSC 0.305 ±0.038 (.0120 ±.0015) TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) DETAIL “A” 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) 0° – 6° TYP 0.280 ±0.076 (.011 ±.003) REF 16151413121110 9 GAUGE PLANE 0.53 ±0.152 (.021 ±.006) DETAIL “A” 0.18 (.007) SEATING PLANE 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 1234567 8 0.50 NOTE: (.0197) 1. DIMENSIONS IN MILLIMETER/(INCH) BSC 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.86 (.034) REF 0.1016 ±0.0508 (.004 ±.002) MSOP (MS16) 1107 REV Ø 6820f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC6820 Typical Application Interfacing to Daisy-Chained Stack of LTC6804-1 Multicell Battery Monitors LTC6804-1 IPB VREG ISOMD IMB IBIAS IPA ICMP IMA VM 806Ω 120Ω 1.21k GND4 LTC6804-1 IPB VREG ISOMD IMB IBIAS IPA ICMP IMA VM 120Ω 806Ω 120Ω 5V 100nF 2k LTC6820 EN IBIAS ICMP VDDS GND SLOW VDD MSTR POL MISO PHA MOSI SCK IP CS IM 806Ω 1.21k GND3 1.21k LTC6804-1 5V 100nF IPB VREG ISOMD IMB IBIAS IPA ICMP IMA VM 120Ω 806Ω 120Ω 120Ω 1.21k 6820 TA06 GND2 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC6803-2/ LTC6803-4 Multicell Battery Stack Monitor with an Individually Addressable SPI Interface Functionality Equivalent to LTC6803-1/LTC6803-3, Allows for Parallel Communication Battery Stack Topologies LTC6803-1/ LTC6803-3 Multicell Battery Stack Monitor with Daisy-Chained SPI Interface Functionality Equivalent to LTC6803-2/LTC6803-4, Allows for Multiple Devices to Be Daisy Chained LTC6903 1kHz to 68MHz Programmable Silicon Oscillator with SPI Interface Frequency Resolution of 0.01%. No External Components Required. Operates on 2.7V to 5.5V. LTC6804-1/ LTC6804-2 Multicell Battery Stack Monitor with Built-In isoSPI Interface Includes isoSPI Interfaces for Communication with Master LTC6820 and to other LTC6804 Devices 6820f 28 Linear Technology Corporation LT 1112 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2012