OPA2890 OP A2 89 0 OPA 2890 SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 Low-Power, Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER with Disable FEATURES 1 • FLEXIBLE SUPPLY RANGE: +3V to +12V Single Supply ±1.5V to ±6V Dual Supplies • UNITY-GAIN STABLE • WIDEBAND +5V OPERATION: 90MHz (G = 2V/V) • OUTPUT VOLTAGE SWING: ±4.1V • HIGH SLEW RATE: 400V/µs • LOW QUIESCENT CURRENT: 1.1mA/ch • LOW DISABLE CURRENT: 30µA/ch DESCRIPTION APPLICATIONS The low 1.1mA/ch supply current of the OPA2890 is precisely trimmed at +25°C. This trim, along with low temperature drift, ensures lower maximum supply current than competing products. System power may be reduced further using the optional disable control pin (MSOP-10 package only). Leaving this disable pin open, or holding it high, operates the OPA2890 normally. If pulled low, the OPA2890 supply current drops to less than 30µA/ch while the output goes into a high-impedance state. 2 • • • • • • • The OPA2890 represents a major step forward in unity-gain stable, voltage-feedback op amps. A new internal architecture provides slew rate and full-power bandwidth previously found only in wideband, current-feedback op amps. These capabilities give exceptional single-supply operation. Using a single +5V supply, the OPA2890 can deliver a 0.9V to 4.1V output swing with over 30mA drive current and 210MHz bandwidth. This combination of features makes the OPA2890 an ideal RGB line driver or single-supply analog-to-digital converter (ADC) input driver. VIDEO LINE DRIVING xDSL LINE DRIVERS/RECEIVERS HIGH-SPEED IMAGING CHANNELS ADC BUFFERS PORTABLE INSTRUMENTS TRANSIMPEDANCE AMPLIFIERS ACTIVE FILTERS 1kW 50W 0V ® 4V 500pF 200W +5V +6V ADS8472 VI 1/2 OPA2890 16W RELATED OPERATIONAL AMPLIFIER PRODUCTS -6V 200W SINGLES 750W 0.01mF 16-Bit 1MSPS SAR ADC 750W 375W 16W Voltage-feedback amplifier with disable (1800V/µs) DUALS TRIPLES OPA890 Very low-power voltage-feedback with disable +6V 1/2 OPA2890 Low-power voltage-feedback with disable OPA2889 OPA690 OPA2690 OPA3690 VREF/2 -6V 500kHz LP Pole Low Power, DC-Coupled, Single-to-Differential Driver for ≤100kHz Inputs 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR OPA2890 SO-8 D –40°C to +85°C OPA2890 OPA2890 MSOP-10 DGS –40°C to +85°C BPQ (1) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY OPA2890ID Rail, 75 OPA2890IDR Tape and Reel, 2500 OPA2890IDGST Tape and Reel, 250 OPA2890IDGSR Tape and Reel, 2500 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. OPA2890 UNIT ±6.5 V Power supply Internal power dissipation See Thermal Characteristics Input voltage range ±VS V –40 to +125 °C Lead temperature (soldering, 10s) +260 °C Maximum junction temperature (TJ) +150 °C Minimum junction temperature: continuous operation, long-term reliability +140 °C Human body model (HBM) 2000 V Charge device model (CDM) 1500 V Machine model (MM) 200 V Storage temperature range ESD Rating: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. PIN CONFIGURATIONS SO-8 Top View Out A 2 1 -In A 2 +In A 3 -VS 4 A B MSOP-10 Top View 8 +VS +In A 1 10 -In A 7 Out B DIS A 2 9 Out A 6 -In B -VS 3 8 +VS 5 +In B DIS B 4 7 Out B +In B 5 6 -In B Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 ELECTRICAL CHARACTERISTICS: VS = ±5V At TA = +25°C, RF = 0Ω, G = +1V/V, and RL = 200Ω, unless otherwise noted. OPA2890ID, IDGS TYP MIN/MAX OVER TEMPERATURE +25°C (2) 0°C to +70°C (3) –40°C to +85°C (3) 100 60 50 45 G = +10V/V, VO = 100mVPP 12 8 7 G > +20V/V 120 90 80 G = +2V/V, VO = 100mVPP 15 PARAMETER CONDITIONS +25°C G = +1V/V, VO = 100mVPP, RF = 0Ω 250 G = +2V/V, VO = 100mVPP MIN/ MAX TEST LEVEL (1) MHz typ C MHz min B 6.5 MHz min B 78 MHz min B MHz typ C UNITS AC PERFORMANCE Small-signal bandwidth Gain bandwidth product Bandwidth for 0.1dB flatness Peaking at a gain of +1V/V Large-signal bandwidth Slew rate VO < 100mVPP 0.2 dB typ C G = +2V/V, VO = 2VPP 110 MHz typ C G = +2V/V, VO = 2V step 400 V/µs min B 0.2V step 3.5 ns typ C G = +1V/V, VO = 2V step 16 ns typ C 10 ns typ C Rise-and-fall time Settling time to 0.02% Settling time to 0.1% Harmonic distortion 300 275 270 G = +2V/V, f = 1MHz, VO = 2VPP 2nd harmonic RL = 200Ω 84 73 69 68 dBc max B RL ≥ 500Ω 100 83 81 80 dBc max B RL = 200Ω 89 84 81 80 dBc max B RL ≥ 500Ω 94 90 87 86 dBc max B Input voltage noise f > 100kHz 8 9 10 11 nV/√Hz max B Input current noise f > 100kHz 1 1.3 1.7 1.9 pA/√Hz max B Differential gain G = +2V/V, VO = 1.4VPP, RL = 150Ω 0.05 % typ C Differential phase G = +2V/V, VO = 1.4VPP, RL = 150Ω 0.03 ° typ C f = 5MHz, Input-referred –68 dB typ C VO = 0V, RL = 100Ω 62 57 56 54 dB min A VCM = 0V ±2 ±5 ±6.6 ±7.1 mV max A ±35 ±35 µV/°C max B ±1.8 ±2 µA max A ±5 ±6 nA/°C max B ±450 ±500 nA max A ±2.5 ±2.5 nA/°C max B 3rd harmonic Channel-to-channel crosstalk DC PERFORMANCE (4) Open-loop voltage gain (AOL) Input offset voltage Average offset voltage drift VCM = 0V Input bias current VCM = 0V Average input bias current drift ±0.1 ±1.6 VCM = 0V Input offset current VCM = 0V Average input offset current drift ±70 ±350 VCM = 0V INPUT Common-mode input range (CMIR) (5) ±3.9 ±3.8 ±3.7 ±3.6 V min A VCM = 0V, Input-referred 66 60 57 56 dB min A Differential VCM = 0V 190 || 0.6 kΩ || pF typ C Common-mode VCM = 0V 3.2 || 0.9 MΩ || pF typ C Common-mode rejection ratio (CMRR) Input impedance OUTPUT Output voltage swing No load ±4.0 ±3.9 ±3.8 ±3.7 V min A RL = 100Ω ±3.6 ±3.1 ±3.05 ±2.9 V min A VO = 0V ±40 ±35 ±33 ±30 mA min A Output shorted to ground ±75 mA typ C G = +2V/V, f = 100kHz 0.04 Ω typ C Output current, sourcing, sinking Peak output current Closed-loop output impedance (1) (2) (3) (4) (5) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Junction temperature = ambient for +25°C tested specifications. Junction temperature = ambient at low temperature limit; junction temperature = ambient +4°C at high temperature limit for over temperature specifications. Current is considered positive out-of-node. VCM is the input common-mode voltage. Tested < 3dB below minimum specified CMRR at ±CMIR limits Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 3 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 ELECTRICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, RF = 0Ω, G = +1V/V, and RL = 200Ω, unless otherwise noted. OPA2890ID, IDGS TYP MIN/MAX OVER TEMPERATURE +25°C +25°C (2) 0°C to +70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX VDIS = 0, Both channels 60 110 120 150 µA max A VIN = 1VDC 7 µs typ C Enable time VIN = 1VDC 200 ns typ C Off isolation G = +2V/V, f = 5MHz 70 dB typ C 4 pF typ C PARAMETER CONDITIONS DISABLE (MSOP-10 ONLY) TEST LEVEL (1) Disablelow Power-down supply current (+VS) Disable time Output capacitance in disable Enable voltage 3.0 3.2 3.4 3.8 V min A Disable voltage 1.4 1.1 1.0 0.8 V max A 15 30 35 40 µA max A Control pin input bias current (VDIS) VDIS = 0V, Each channel POWER SUPPLY Specified operating voltage ±5 V typ C Minimum operating voltage 1.5 V typ C Maximum operating voltage ±6.0 ±6.0 ±6.0 V max A Maximum quiescent current VS = ±5V, Both channels 2.25 2.4 2.45 2.5 mA max A Minimum quiescent current VS = ±5V, Both channels 2.25 2.1 2.05 2.0 mA min A +VS = 4.5V to 5.5V 68 60 58 56 dB min A °C typ C Power-supply rejection ratio (+PSRR) THERMAL CHARACTERISTICS A Specified operating range: D and DGS packages –40 to +85 Thermal resistance, θJA Junction-toambient D SO-8 100 °C/W typ C DGS MSOP-10 135 °C/W typ C 4 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 ELECTRICAL CHARACTERISTICS: VS = +5V At RF = 0Ω, G = +1V/V, and RL = 100Ω, unless otherwise noted. OPA2890ID, IDGS TYP MIN/MAX OVER TEMPERATURE +25°C (2) 0°C to +70°C (3) –40°C to +85°C (3) 90 55 45 40 G = +10V/V, VO = 100mVPP 12 8 6.8 G > +20V/V 120 85 70 G = +2V/V, VO = 100mVPP 15 PARAMETER CONDITIONS +25°C G = +1V/V, VO = 100mVPP, RF = 0Ω 210 G = +2V/V, VO = 100mVPP MIN/ MAX TEST LEVEL (1) MHz typ C MHz min B 6.3 MHz min B 68 MHz min B MHz typ C UNITS AC PERFORMANCE Small-signal bandwidth Gain bandwidth product Bandwidth for 0.1dB flatness Peaking at a gain of +1V/V Large-signal bandwidth Slew rate VO < 100mVPP 0.2 dB typ C G = +2V/V, VO = 2VPP 100 MHz typ C G = +2V/V, VO = 2V step 350 V/µs min B 0.2V step 3.8 ns typ C G = +1V/V, VO = 2V step 18 ns typ C 12 ns typ C Rise-and-fall time Settling time to 0.02% Settling time to 0.1% Harmonic distortion 250 200 175 G = +2V/V, f = 1MHz, VO = 2VPP 2nd harmonic RL = 200Ω 80 71 68 67 dBc max B RL ≥ 500Ω 87 75 71 70 dBc max B RL = 200Ω 83 79 77 76 dBc max B RL ≥ 500Ω 86 83 81 80 dBc max B Input voltage noise f > 100kHz 8.1 9.1 10.1 11.1 nV/√Hz max B Input current noise f > 100kHz 1.1 1.4 1.7 2.0 pA/√Hz max B Differential gain G = +2V/V, VO = 1.4VPP, RL = 150Ω 0.06 % typ C Differential phase G = +2V/V, VO = 1.4VPP, RL = 150Ω 0.04 ° typ C f = 5MHz, Input-referred -68 dB typ C VO = VS/2, RL = 100Ω 60 55 54 52 dB min A VCM = VS/2 ±2 ±5 ±6.6 ±7.1 mV max A ±35 ±35 µV/°C max B ±1.9 ±2.1 µA max A ±5 ±6 nA/°C max B ±500 ±550 nA max A ±2.5 ±2.5 nA/°C max B 3rd harmonic Channel-to-channel crosstalk DC PERFORMANCE (4) Open-loop voltage gain (AOL) Input offset voltage Average offset voltage drift VCM = VS/2 Input bias current VCM = VS/2 Average input bias current drift ±0.1 ±1.7 VCM = VS/2 Input offset current VCM = VS/2 Average input offset current drift ±70 ±400 VCM = VS/2 INPUT Most positive input voltage (5) +4 +3.8 +3.75 +3.7 V min A Least positive input voltage (5) +1 +1.2 +1.2 +1.3 V max A VCM = VS/2, Input-referred 65 59 56 55 dB min A Differential VCM = VS/2 190 || 0.6 kΩ || pF typ C Common-mode VCM = VS/2 3.2 || 0.9 MΩ || pF typ C Common-mode rejection ratio (CMRR) Input impedance OUTPUT Most positive output voltage No load +4.1 +3.9 +3.85 +3.8 V min A RL = 100Ω +3.9 +3.75 +3.7 +3.65 V min A No load +0.9 +1.1 +1.15 +1.2 V max A RL = 100Ω +1.1 +1.35 +1.4 +1.45 V max A VO = VS/2 ±35 ±30 ±28 ±25 mA min A Output shorted to ground ±65 mA typ C G = +2V/V, f = 100kHz 0.04 Ω typ C Least positive output voltage Output current: sourcing, sinking Short-circuit output current Closed-loop output impedance (1) (2) (3) (4) (5) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Junction temperature = ambient for +25°C tested specifications. Junction temperature = ambient at low temperature limit; junction temperature = ambient +2°C at high temperature limit for over temperature specifications. Current is considered positive out-of-node. VCM is the input common-mode voltage. Tested < 3dB below minimum specified CMRR at ±CMIR limits Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 5 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 ELECTRICAL CHARACTERISTICS: VS = +5V (continued) At RF = 0Ω, G = +1V/V, and RL = 100Ω, unless otherwise noted. OPA2890ID, IDGS TYP PARAMETER CONDITIONS DISABLE (MSOP-10 ONLY) MIN/MAX OVER TEMPERATURE +25°C +25°C (2) 0°C to +70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX TEST LEVEL (1) 35 90 100 130 µA max A ns typ C Disable low Power-down supply current (+VS) VDIS = 0V, Both channels Disable time VOUT = 1VDC Enable time VOUT = 1VDC ns typ C Off isolation G = +2V/V, f = 5MHz dB typ C pF typ C Output capacitance in disable Enable voltage 3.0 3.2 3.4 3.8 V min A Disable voltage 1.4 1.1 1.0 0.8 V max A 15 30 35 40 µA max A Control pin input bias current (VDIS) VDIS = 0V, Each channel POWER SUPPLY Specified operating voltage +5 V typ C Minimum operating voltage +3 V typ C Maximum operating voltage +12 +12 +12 V max A A Maximum quiescent current VS = +5V, Both channels 2.1 2.35 2.4 2.45 mA max Minimum quiescent current VS = +5V, Both channels 2.1 1.85 1.8 1.75 mA min A +VS = 4.5V to 5.5V 65 dB typ C –40 to +85 °C typ C Power-supply rejection ratio (+PSRR) THERMAL CHARACTERISTICS Specified operating range: D and DGS packages Thermal resistance, θJA Junction-to-ambient D SO-8 100 °C/W typ C DGS MSOP-10 135 °C/W typ C 6 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS: VS = ±5V At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 200Ω, unless otherwise noted. See Figure 49. SMALL-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE 9 3 G = +1V/V R F = 0W 2VPP 6 -3 3 G = +10V/V Gain (dB) Normalized Gain (dB) 0 -6 -9 0 7VPP -3 G = +5V/V -12 G = +2V/V -15 -6 VO = 0.5VPP RL = 200W G = +2V/V -9 -18 1 10 100 1 600 10 Figure 1. SMALL-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE 4 VO = 500mVPP G = +2V/V VO = 5VPP G = +2V/V 3 Output Voltage (1V/div) Output Voltage (100mV/div) 400 Figure 2. 400 200 100 0 -100 -200 2 1 0 -1 -2 -3 -300 -4 -400 Time (10ns/div) Time (10ns/div) Figure 3. Figure 4. VIDEO DIFFERENTIAL GAIN/DIFFERENTIAL PHASE 0.20 -dP 0.18 CHANNEL-TO-CHANNEL CROSSTALK 0.40 -40 0.36 -45 Input-Referred 0.32 0.28 0.12 0.24 0.10 0.20 +dG 0.08 0.16 +dP 0.06 0.12 Differential Phase (°) -dG 0.14 -50 Crosstalk (dB) 0.16 Differential Gain (%) 100 Frequency (MHz) Frequency (MHz) 300 1VPP 4VPP -55 -60 -65 -70 0.04 0.08 0.02 0.04 -75 0 -80 0 1 2 3 4 1 Video Loads 10 100 Frequency (MHz) Figure 5. Figure 6. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 7 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 200Ω, unless otherwise noted. See Figure 49. HARMONIC DISTORTION vs LOAD RESISTANCE 1MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE -75 VO = 2VPP f = 1MHz G = +2V/V -75 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -70 2nd Harmonic -80 -85 3rd Harmonic -90 VO = 2VPP RL = 200W G = +2V/V -80 2nd Harmonic -85 3rd Harmonic -90 -95 -95 100 1k 2.5 4.5 Figure 8. 5.0 5.5 6.0 HARMONIC DISTORTION vs OUTPUT VOLTAGE -75 -60 Harmonic Distortion (dBc) VO = 2VPP RL = 200W G = +2V/V -70 -80 2nd Harmonic -90 3rd Harmonic -100 RL = 200W f = 1MHz G = +2V/V -80 2nd Harmonic -85 -90 3rd Harmonic -95 -110 0.1 1 0.1 10 1 10 Output Voltage Swing (VPP) Frequency (MHz) Figure 9. Figure 10. HARMONIC DISTORTION vs NONINVERTING GAIN HARMONIC DISTORTION vs INVERTING GAIN -70 -65 VO = 2VPP RL = 200W f = 1MHz -75 2nd Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) 4.0 Figure 7. HARMONIC DISTORTION vs FREQUENCY -80 3rd Harmonic -85 -90 -95 -70 VO = 2VPP RL = 200W f = 1MHz 2nd Harmonic -75 -80 3rd Harmonic -85 -90 1 8 3.5 Supply Voltage (±VS) -50 Harmonic Distortion (dBc) 3.0 Resistance (W) 10 20 -1 -10 Gain (V/V) Gain (V/V) Figure 11. Figure 12. Submit Documentation Feedback -20 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 200Ω, unless otherwise noted. See Figure 49. LOW-FREQUENCY INVERTING HARMONIC DISTORTION TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS -90 -30 VO = 2VPP RL = 500W G = -1V/V 10MHz -50 Spurious Point (+dBc) Harmonic Distortion (dBc) -95 Load power at matched 50W load. -40 -100 -105 2nd Harmonic -60 5MHz -70 -80 -90 1MHz -110 -100 3rd Harmonic -110 -115 1k 10k 100k 1M -8 -6 -4 Frequency (Hz) -2 0 2 4 6 8 Single-Tone Load Power (dBm) Figure 13. Figure 14. RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 9 100 Gain to Capacitive Load (dB) RS (W) G = +2V/V 10 6 CL = 10pF 3 CL = 22pF CL = 47pF 0 CL = 100pF -3 VIN 1/2 OPA2890 RS VOUT CL 1kW (1) 750W -6 750W NOTE: (1) 1kW is optional. -9 1 1 10 100 0 1000 20 40 60 80 100 120 140 160 180 200 Frequency (MHz) Capacitive Load (pF) Figure 15. Figure 16. COMMON-MODE REJECTION RATIO AND POWER-SUPPLY REJECTION RATIO vs FREQUENCY INPUT VOLTAGE AND CURRENT NOISE 80 100 -PSRR CMRR Voltage Noise (nV/ÖHz) Current Noise (pA/ÖHz) CMRR and PSRR (dB) 70 60 +PSRR 50 40 30 20 Voltage Noise (8nV/ÖHz) 10 Current Noise (1pA/ÖHz) 1 10 0 0.1 1k 10k 100k 1M 10M 100M 1 Frequency (Hz) 10 100 1k 10k 100k 1M Frequency (Hz) Figure 17. Figure 18. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 9 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 200Ω, unless otherwise noted. See Figure 49. SUPPLY AND OUTPUT CURRENT vs TEMPERATURE TYPICAL DC DRIFT OVER TEMPERATURE 150 2.36 Sinking Output Current 2.32 2.28 Sourcing Output Current 42.5 2.24 42.0 2.20 Quiescent Supply Current 41.5 2.16 41.0 2.12 40.5 2.08 40.0 -20 0 20 40 60 80 100 100 0 50 0 -0.4 -50 -0.6 -100 -0.8 -150 -1.0 Input Offset Voltage (VOS) -1.2 -40 120 -20 0 20 Figure 19. 80 100 120 NONINVERTING OVERDRIVE RECOVERY 0 -2 3 2 1 0 8 4 6 3 4 2 Output Voltage Left Scale 2 1 0 0 Input Voltage Right Scale -2 -1 -4 -2 -6 -3 -8 -1 -4 Time (5ns/div) Time (10ns/div) Figure 21. Figure 22. CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY OPEN-LOOP GAIN AND PHASE 100 80 374W ZO 750W 0.1 0.01 0.001 160 Open-Loop Gain 60 140 50 120 40 100 Open-Loop Phase 30 80 20 60 10 40 0 20 0 -10 1k 10k 100k 1M 10M 100M Open-Loop Phase (°) 750W 1 180 70 1/2 OPA2890 Open-Loop Gain (dB) 10 Input Voltage (1V/div) 2 VDIS (2V/div) 4 Output Voltage (2V/div) 6 Output Voltage (2V/div) 60 Figure 20. LARGE-SIGNAL DISABLE/ENABLE RESPONSE Output Impedance (W) 40 Ambient Temperature (°C) Ambient Temperature (°C) 100 1k Frequency (Hz) 10k 100k 1M 10M 100M 1G Frequency (Hz) Figure 23. 10 -0.2 Input Bias Current (IB) -200 2.04 -40 0.2 Input Offset Current (IOS) Input Offset Voltage (mV) 43.0 Supply Current (mA) Output Current (mA) 43.5 Input Bias and Offset Current (mA) 44.0 Figure 24. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 200Ω, unless otherwise noted. See Figure 49. DISABLE FEEDTHROUGH -70 VDIS = 0 Disable Feedthrough (dB) -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 1 10 100 Frequency (MHz) Figure 25. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 11 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS: VS = ±5V, Differential At TA = +25°C, Differential Gain = +2V/V, and RL = 400Ω, unless otherwise noted. See Figure 52. DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE 3 9 GD = 1V/V 6 VO = 5VPP GD = 2V/V -3 3 Gain (dB) Normalized Gain (dB) 0 -6 -9 GD = 10V/V -12 -15 -18 1M VO = 8VPP -3 VO = 14VPP -6 GD = 5V/V RF = 750W RL = 400W 0 -9 RL = 400W GD = 2V/V -12 10M 100M 400M 1 Figure 26. Figure 27. DIFFERENTIAL DISTORTION vs LOAD RESISTANCE 200 DIFFERENTIAL DISTORTION vs FREQUENCY -30 2nd Harmonic -70 -75 -80 3rd Harmonic VO = 4VPP f = 1MHz GD = 2V/V -85 VO = 4VPP RL = 400W GD = 2V/V -40 Harmonic Distortion (dBc) -65 -90 -50 -60 2nd Harmonic -70 -80 3rd Harmonic -90 -100 100 1k 1 10 Resistance (W) 20 Frequency (MHz) Figure 28. Figure 29. DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE DIFFERENTIAL DISTORTION vs FREQUENCY -65 -90 2nd Harmonic -70 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 100 Frequency (MHz) -60 Harmonic Distortion (dBc) 10 Frequency (Hz) RL = 400W f = 1MHz GD = 2V/V -75 -80 -85 -100 RL_DIFF = 1kW GD = -1V/V VO = 4VPP 3rd Harmonic -110 -120 -130 2nd Harmonic -140 3rd Harmonic -150 -90 1 12 10 1k 10k 100k Output Voltage (VPP) Frequency (Hz) Figure 30. Figure 31. Submit Documentation Feedback 1M Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS: VS = +5V At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 200Ω, unless otherwise noted. See Figure 49. NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE 3 9 G = +1V/V R F = 0W RL = 200W G = +2V/V 6 1VPP -3 3 Gain (dB) Normalized Gain (dB) 0 -6 G = +10V/V -9 2VPP 0 -3 -12 G = +5V/V -6 -15 3VPP G = +2V/V VO = 500mVPP -18 -9 1 10 100 500 1 10 Frequency (MHz) Figure 32. SMALL-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE 4.1 VO = 0.5VPP G = +2V/V VO = 2VPP G = +2V/V 3.7 Output Voltage (400mV/div) 2.8 Output Voltage (100mV/div) 300 Figure 33. 2.9 2.7 2.6 2.5 2.4 2.3 2.2 3.3 2.9 2.5 2.1 1.7 1.3 2.1 0.9 Time (10ns/div) Time (10ns/div) Figure 34. Figure 35. RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 9 Gain to Capacitive Load (dB) 100 RS (W) 100 Frequency (MHz) 10 CL = 10pF 6 3 CL = 22pF CL = 100pF 0 -3 CL = 47pF -6 VIN 1/2 OPA2890 -9 RS VOUT CL 1kW (1) 750W -12 750W NOTE: (1) 1kW is optional. -15 1 1 10 100 1000 0 20 40 60 80 100 120 140 160 180 200 Capacitive Load (pF) Frequency (MHz) Figure 36. Figure 37. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 13 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS: VS = +5V (continued) At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 200Ω, unless otherwise noted. See Figure 49. HARMONIC DISTORTION vs LOAD RESISTANCE 5.5 4.0 4.5 3.5 3.5 3.0 Output Voltage Left Scale 2.5 2.5 Input Voltage Right Scale 1.5 2.0 0.5 1.5 -0.5 1.0 -70 Harmonic Distortion (dBc) 4.5 Input Voltage (1V/div) Output Voltage (1V/div) NONINVERTING OVERDRIVE RECOVERY 6.5 0.5 -1.5 VO = 2VPP f = 1MHz G = +2V/V -75 2nd Harmonic -80 -85 3rd Harmonic -90 -95 100 Time (10ns/div) 1k Resistance (W) Figure 38. Figure 39. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE -75 -60 VO = 2VPP RL = 200W to VS/2 G = +2V/V Harmonic Distortion (dBc) Harmonic Distortion (dBc) -50 -70 -80 2nd Harmonic -90 RL = 200W to VS/2 f = 1MHz G = +2V/V -80 2nd Harmonic -85 3rd Harmonic 3rd Harmonic -100 -90 0.1 1 0.1 10 1 10 Output Voltage Swing (VPP) Frequency (MHz) Figure 40. Figure 41. TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS -30 Load Power at Matched 50W Load -40 Intercept Point (dBc) 10MHz -50 -60 5MHz -70 -80 1MHz -90 -100 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 Single-Tone Load Power (dB) Figure 42. 14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS: VS = +5V, Differential At TA = +25°C, Differential Gain = +2V/V, and RL = 400Ω, unless otherwise noted. See Figure 58. DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE 3 9 GD = 1V/V, RF = 0W VO = 4VPP 6 GD = 2V/V -3 3 Gain (dB) Normalized Gain (dB) 0 -6 -9 GD = 10V/V -12 -15 -18 1 -3 GD = 5V/V RF = 750W RL = 400W VO = 1VPP 0 RF = 750W RL = 400W GD = +2V/V -6 -9 10 100 300 1 100 Frequency (MHz) Figure 43. Figure 44. DIFFERENTIAL DISTORTION vs LOAD RESISTANCE 200 DIFFERENTIAL DISTORTION vs FREQUENCY -60 -30 2nd Harmonic VO = 4VPP RL = 400W GD = 2V/V -40 -65 -70 VO = 4VPP f = 1MHz GD = 2V/V -75 3rd Harmonic -80 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 10 Frequency (MHz) -50 -60 2nd Harmonic -70 3rd Harmonic -80 -90 -100 -85 100 1k 0.1 1 Resistance (W) Figure 45. 20 Figure 46. DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE DIFFERENTIAL DISTORTION vs FREQUENCY -60 -80 RL = 400W f = 1MHz GD = 2V/V 2nd Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) 10 Frequency (MHz) -70 -80 3rd Harmonic RL_DIFF = 1kW GD = 1V/V VO = 4VPP -85 3rd Harmonic -90 -100 -110 2nd Harmonic -120 Shift Phase 180° of Input Signal -130 -90 0.1 1 10 1 10 100 Output Voltage (VPP) Frequency (Hz) Figure 47. Figure 48. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 1000 15 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 APPLICATIONS INFORMATION WIDEBAND VOLTAGE-FEEDBACK OPERATION +5V +VS 0.1mF The OPA2890 provides an exceptional combination of high output power capability in a dual, wideband, unity-gain stable, voltage-feedback op amp using a new high slew rate input stage. Typical differential input stages used for voltage-feedback op amps are designed to steer a fixed-bias current to the compensation capacitor, setting a limit to the achievable slew rate. The OPA2890 uses a new input stage that places the transconductance element between two input buffers, using the output currents as the forward signal. As the error voltage increases across the two inputs, an increasing current is delivered to the compensation capacitor. This configuration provides high slew rate (400V/µs) while consuming relatively low quiescent current (1.12mA/ch). This exceptional full-power performance comes at the price of a slightly higher input noise voltage than alternative architectures; however, the 8nV/√Hz input voltage noise for the OPA2890 is exceptionally low for this type of input stage. Figure 49 shows the DC-coupled, gain of +2V/V, dual power-supply circuit configuration used as the basis of the ±5V Electrical Characteristics and Typical Characteristics. This illustration is for one channel; the other channel is connected similarly. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 200Ω. Voltage swings reported in the Electrical Characteristics are taken directly at the input and output pins, while output powers (dBm) are at the matched 50Ω load. For the circuit of Figure 49, the total effective load is 200Ω || 1.5kΩ. The disable control line (MSOP-10 package only) is typically left open for normal amplifier operation. Two optional components are included in Figure 49. First, an additional resistor (350Ω) is included in series with the noninverting input. Combined with the 25Ω dc source resistance looking back towards the signal generator, this resistor gives an input bias current cancelling resistance that matches the 750Ω source resistance seen at the inverting input (see the DC Accuracy and Offset Control section). In addition to the usual power-supply decoupling capacitors to ground, a 0.1µF capacitor is also included between the two power-supply pins. In practical printed circuit board (PCB) layouts, this optional capacitor typically improves the 2nd-harmonic distortion performance by 3dB to 6dB. 16 50W Source VI 6.8mF + 350W DIS VD 50W VO 1/2 OPA2890 0.1mF 100W 100W Load RF 750W RG 750W + 6.8mF 0.1mF -VS -5V Figure 49. DC-Coupled, G = +2V/V, Bipolar Supply, Specification and Test Circuit Figure 50 illustrates the ac-coupled, gain of +2V/V, single-supply circuit configuration used as the basis of the +5V Electrical Characteristics and Typical Characteristics. Though not a rail-to-rail design, the OPA2890 requires minimal input and output voltage headroom compared to other very wideband voltage-feedback op amps. It delivers a 3VPP output swing on a single +5V supply with greater than 80MHz bandwidth. The key requirement of broadband single-supply operation is to maintain input and output signal swings within the usable voltage ranges at both the input and the output. The circuit of Figure 50 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 698Ω resistors). Separate bias networks would be required at each input. The input signal is then ac-coupled into the midpoint voltage bias. The input voltage can swing to within 1.5V of either supply pin, giving a 2VPP input signal range centered between the supply pins. The input impedance matching resistor (59Ω) used for testing is adjusted to give a 50Ω input load when the parallel combination of the biasing divider network is included. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 +5V +VS +5V GD = 0.1mF + 1/2 OPA2830 6.8mF 698W 0.1mF 50W 698W 59W RG RF RG RF DIS VD VI RF RG 1/2 OPA2890 VIN VO 200W RL VOUT VS/2 RF 750W 1/2 OPA2830 RG 750W -5V 0.1mF Figure 51. Differential Inverting Specification and Test Circuit Figure 50. DC-Coupled, G = +2V/V, Single-Supply, Specification and Test Circuit +5V GD = 1 + 2RF RG 1/2 OPA2830 Again, an additional resistor (50Ω in this case) is included directly in series with the noninverting input. This minimum recommended value provides part of the dc source resistance matching for the noninverting input bias current. It is also used to form a simple parasitic pole to roll off the frequency response at very high frequencies ( > 500MHz) using the input parasitic capacitance. The gain resistor (RG) is AC-coupled, giving the circuit a dc gain of +1V/V, which puts the input dc bias voltage (2.5V) on the output as well. The output voltage can swing to within 1V of either supply pin while delivering greater than 40mA output current. RF VIN RG RL RF 1/2 OPA2830 -5V Figure 52. Differential Noninverting Specification and Test Circuit DIFFERENTIAL OPERATION Figure 51 shows the inverting differential configuration used as the basis for the ±5V and +5V Typical Characteristics. This circuit offers a combination of excellent distortion with low quiescent current for frequencies below 100kHz. The other possibility is to use the OPA2890 in a differential configuration as shown in Figure 52. This figure illustrates the differential noninverting configuration that has the advantage of showing a high input impedance to any prior stage. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 17 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 HIGH-PERFORMANCE DAC TRANSIMPEDANCE AMPLIFIER WIDEBAND VIDEO MULTIPLEXING One common application for video speed amplifiers that include a disable pin is to wire multiple amplifier outputs together, then select one of several possible video inputs to source onto a single line. This simple wired-OR video multiplexer can be easily implemented using the OP2890IDGS (MSOP-10 package only), as shown in Figure 54. High-frequency DDS digital-to-analog converters (DACs) require a low distortion output amplifier to retain SFDR performance into real-world loads. Figure 53 shows a single-ended output drive implementation. The diagram shows the signal output current(s) connected into the virtual ground summing junction(s) of the OPA2890, which is set up as a transimpedance stage or I-V converter. If the DAC requires that its outputs terminate to a compliance voltage other than ground for operation, the appropriate voltage level may be applied to the noninverting input of the OPA2890. The dc gain for this circuit is equal to RF. At high frequencies, the DAC output capacitance (CD in Figure 53) produces a zero in the noise gain for the OPA2890 that may cause peaking in the closed-loop frequency response. CF is added across RF to compensate for this noise gain peaking. To achieve a flat transimpedance frequency response, the pole in each feedback network should be set to: 1 GBP = 2pRFCF 4pRFCD (1) 50W 1/2 OPA2890 High-Speed DAC VO = IO RF RF1 CF1 IO CD1 RF2 CF2 -IO CD2 1/2 OPA2890 which gives a cutoff frequency f–3dB of approximately: GBP f-3dB = 2pRFCD 50W -VO = -IO RF GBP ® Gain Bandwidth Product (Hz) for the OPA2890 Figure 53. DAC Transimpedance Amplifier +5V 2kW VDIS +5V 305W DISA Video 1 1/2 OPA2890 75W 634W 750W -5V 75W Cable 634W 750W Video 2 RG-59 75W Load +5V 305W 82.5W 82.5W 1/2 OPA2890 DISB 75W 2kW -5V Figure 54. 2-Channel Video Multiplexer (MSOP-10 package only) 18 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 Typically, channel switching is performed either on sync or retrace time in the video signal. The two inputs are approximately equal at this point. The make-before-break disable characteristic of the OPA2890 ensures that there is always one amplifier controlling the line when using a wired-OR circuit such as that shown in Figure 54. Because both inputs may be on for a short period during the transition between channels, the outputs are combined through the output impedance matching resistors (82.5Ω in this case). When one channel is disabled, its feedback network forms part of the output impedance and slightly attenuates the signal in getting out onto the cable. The gain and output matching resistor are slightly increased to get a signal gain of +1V/V at the matched load and provide a 75Ω output impedance to the cable. The video multiplexer connection (see Figure 54) also ensures that the maximum differential voltage across the inputs of the unselected channel does not exceed the rated ±1.2V maximum for standard video signal levels. See the Disable Operation section for the turn-on and turn-off switching glitches using a 0V input for a single channel is typically less than ±50mV. Where two outputs are switched (see Figure 54), the output line is always under the control of one amplifier or the other as a result of the make-before-break disable timing. In this case, the switching glitches for two 0V inputs drops to less than 20mV. HIGH-SPEED DELAY CIRCUIT The OPA2890 makes an ideal amplifier for a variety of active filter designs. Figure 55 illustrates a circuit that uses the two amplifiers within the dual OPA2890 to design a two-stage analog delay circuit. For simplicity, the circuit uses a dual-supply (±5V) operation, but it can also be modified to operate on a signal supply. The input to the first filter stage is driven by the OPA890 as a gain of +2V/V to isolate the signal input from the filter network. Each of the two filter stages is a 1st-order filter with a voltage gain of +1V/V. The delay time through one filter is given by Equation 2. tGR0 = 2RC (2) For a more accurate analysis of the circuit, consider the group delay for the amplifiers. For example, in the case of the OPA2890, the group delay in the bandwidth from 1MHz to 100MHz is approximately 1.0ns. To account for this delay, modify the transfer function, which now comes out to be: tGR = 2 (2RC + TD) (3) with TD = (1/360) × (dφ/df) = delay of the op amp itself. The values of resistors RF and RG should be equal and low to avoid parasitic effects. If the all-pass filter is designed for very low delay times, include parasitic board capacitances to calculate the correct delay time. Simulating this application using the PSpice model of the OPA2890 allows this design to be tuned to the desired performance. C VIN OPA890 1/2 OPA2890 C 1/2 OPA2890 R 750W 750W VOUT R RG 402W RF 402W RG 402W RF 402W Figure 55. Two-Stage, All-Pass Network Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 19 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 DIFFERENTIAL RECEIVER/DRIVER A very versatile application for a dual operational amplifier is the differential amplifier configuration shown in Figure 56. With both amplifiers of the OPA2890 connected for noninverting operation, the circuit provides a high input impedance, while the gain can easily be set by just one resistor, RG. When operated in low gains, the output swing may be limited as a result of the common-mode input swing limits of the amplifier itself. An interesting modification of this circuit is to place a capacitor in series with RG. Now the dc gain for each side is reduced to +1V/V; the ac gain follows the standard transfer function of G = 1 + 2RF/RG. This configuration might be advantageous for applications processing only a frequency band that excludes dc or very low frequencies. An input dc voltage resulting from input bias currents is not amplified by the ac gain and can be kept low. This circuit can be used as a differential line receiver, driver, or as an interface to a differential input ADC. 50W VI 1/2 OPA2890 SINGLE-SUPPLY MFB DIFFERENTIAL ACTIVE FILTER: 2MHz BUTTERWORTH CONFIGURATION The active filter circuit illustrated in Figure 58 can be easily implemented using the OPA2890. In this configuration, each amplifier of the OPA2890 operates as an integrator. For this reason, this type of application is also called an infinite gain filter implementation. A Butterworth filter can be implemented using the following component ratios: 1 fO = 2´p´R´C R1 = R2 = 0.65 ´ R R3 = 0.375 ´ R C1 = C C2 = 2 ´ C The frequency response for a 2MHz Butterworth filter is shown in Figure 57. One advantage for using this type of filter is the independent setting of ωo and Q. Q can be easily adjusted by changing the R3A, B resistors without affecting ωo. RO 3 RF 750W VDIFF = 1 + RF 750W RG 50W 1/2 OPA2890 2RF RG VI - (-VI) Gain (dB) 0 -3 -6 RO -9 -VI -12 Figure 56. High-Speed Differential Receiver 10k 100k 1M 10M Frequency (Hz) Figure 57. Multiple Feedback Filter Frequency Response 20 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 +12V 6kW 50W VCM 1/2 OPA2890 1000pF 6kW C1A 128.7pF R3A 232W R1A 402W R2A 402W C2 257.4pF VIN R1B 402W R2B 402W R3B 232W 50W VOUT C1B 128.7pF 1/2 OPA2890 VCM Figure 58. Single-Supply, MFB Active Filter, 2MHz LP Butterworth DESIGN-IN TOOLS MACROMODELS DEMONSTRATION FIXTURES Two printed circuit boards (PCBs) are available to assist in the initial evaluation of circuit performance using the OPA2890 in its two package options. Both of these are offered free of charge as unpopulated PCBs, delivered with a user’s guide. The summary information for these fixtures is shown in Table 1. Table 1. Demonstration Fixtures by Package PRODUCT PACKAGE ORDERING NUMBER LITERATURE NUMBER OPA2890ID SO-8 DEM-OPA-SO-2A SBOU003 OPA2890IDG S MSOP-10 DEM-OPA-MSOP-2B SBOU040 Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This principle is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA2890 (use two OPA890 SPICE models) is available through the Texas Instruments web page (www.ti.com). This model does a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. It does not do as well in predicting the harmonic distortion or dG/dP characteristics. This model does not attempt to distinguish between the package types in small-signal ac performance. The demonstration fixtures can be requested at the Texas Instruments web site (www.ti.com) through the OPA2890 product folder. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 21 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 OPERATING RECOMMENDATIONS OPTIMIZING RESISTOR VALUES Because the OPA2890 is a unity-gain stable, voltage-feedback op amp, a wide range of resistor values may be used for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. For a noninverting unity-gain follower application, the feedback connection should be made with a 25Ω resistor, not a direct short. This feedback resistor isolates the inverting input capacitance from the output pin and improve the frequency response flatness. Usually, the feedback resistor value should be between 200Ω and 1.5kΩ. Below 200Ω, the feedback network presents additional output loading that can degrade the harmonic distortion performance of the OPA2890. Above 1.5kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor can cause unintentional band-limiting in the amplifier response. A good rule of thumb is to target the parallel combination of RF and RG (see Figure 49) to be less than approximately 400Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network and thus, a zero in the forward response. Assuming a 2pF total parasitic on the inverting node, holding RF || RG < 400Ω keeps this pole above 160MHz. By itself, this constraint implies that the feedback resistor RF can increase to several kΩ at high gains. This increase in resistor size is acceptable as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest. BANDWIDTH vs GAIN: NONINVERTING OPERATION Voltage-feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain increases. In theory, this relationship is described by the Gain Bandwidth Product (GBP) shown in the Electrical Characteristics. Ideally, dividing GBP by the noninverting signal gain (also called the Noise Gain, or NG) predicts the closed-loop bandwidth. In practice, this principle only holds true when the phase margin approaches 90°, as it does in high gain configurations. At low gains (increased feedback factors), most amplifiers exhibit a more complex response with lower phase margin. The OPA2890 is compensated to give a slightly peaked response in a noninverting gain of 2V/V (see Figure 49). This compensation results in a typical gain of +2V/V bandwidth of 100MHz, far exceeding that predicted by dividing the 60MHz GBP by 2. Increasing the gain causes the phase margin to approach 90° and the 22 bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +10V/V, the 12MHz bandwidth shown in the Electrical Characteristics agrees with that predicted using the simple formula and the typical GBP of 120MHz. The frequency response in a gain of +2V/V may be modified to achieve exceptional flatness simply by increasing the noise gain to 2.5V/V. One way to modify the response without affecting the +2V/V signal gain, is to add an 1.5kΩ resistor across the two inputs, as illustrated in the circuit of Figure 49. A similar technique may be used to reduce peaking in unity-gain (voltage follower) applications. For example, by using a 750Ω feedback resistor along with a 750Ω resistor across the two op amp inputs, the voltage follower response is similar to the gain of +2V/V response of Figure 50. Reducing the value of the resistor across the op amp inputs further limits the frequency response due to increased noise gain. The OPA2890 exhibits minimal bandwidth reduction going to single-supply (+5V) operation as compared with ±5V. This feature arises because the internal bias control circuitry retains nearly constant quiescent current as the total supply voltage between the supply pins changes. INVERTING AMPLIFIER OPERATION The OPA2890 is a general-purpose, wideband, voltage-feedback op amp; therefore, all of the familiar op amp application circuits are available to the designer. Inverting operation is one of the more common requirements and offers several performance benefits. See Figure 59 for a typical inverting configuration where the I/O impedances and signal gain from Figure 49 are retained in an inverting circuit configuration. In the inverting configuration, three key design considerations must be noted. The first is that the gain resistor (RG) becomes part of the signal channel input impedance. If input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted-pair, long PCB trace, or other transmission line conductor), RG may be set equal to the required termination value and RF adjusted to give the desired gain. This consideration is the simplest approach and results in optimum bandwidth and noise performance. However, at low inverting gains, the resultant feedback resistor value can present a significant load to the amplifier output. For an inverting gain of –2V/V, setting RG to 50Ω for input matching eliminates the need for RM but requires a 100Ω feedback resistor. This consideration has the interesting advantage that the noise gain becomes equal to 2V/V for a 50Ω source impedance—the same as the noninverting circuits Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 discussed in the previous section. The amplifier output, however, now sees the 100Ω feedback resistor in parallel with the external load. In general, the feedback resistor should be limited to the 200Ω to 1.5kΩ range. In this case, it is preferable to increase both the RF and RG values (see Figure 56), and then achieve the input matching impedance with a third resistor (RM) to ground. The total input impedance becomes the parallel combination of RG and RM. +5V + 0.1mF 6.8mF 0.1mF RB 261W 50W Source VO 1/2 OPA2890 RO 50W 50W Load RG 375W VO = -2V/V VI RF 750W VI RM 57.6W 0.1mF + 6.8mF -5V Figure 59. Gain of –2V/V Example Circuit The second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and influences the bandwidth. For the example in Figure 59, the RM value combined in parallel with the external 50Ω source impedance yields an effective driving impedance of 50Ω || 57.6Ω = 26.7Ω. This impedance is added in series with RG for calculating the noise gain (NG). The resultant NG is 2.86V/V for Figure 59, as opposed to only 2V/V if RM could be eliminated as discussed above. Therefore, the bandwidth is slightly lower for the gain of –2V/V circuit of Figure 59 than for the gain of +2V/V circuit of Figure 49. The third important consideration in inverting amplifier design is setting the bias current cancellation resistor on the noninverting input (RB). If this resistor is set equal to the total dc resistance looking out of the inverting node, the output dc error (as a result of the input bias currents) is reduced to [(Input Offset Current) × RF]. If the 50Ω source impedance is DC-coupled in Figure 57, the total resistance to ground on the inverting input is 402Ω. Combining this resistance in parallel with the feedback resistor gives the RB = 261Ω used in this example. To reduce the additional high-frequency noise introduced by this resistor, it is sometimes bypassed with a capacitor. As long as RB < 350Ω, the capacitor is not required because the total noise contribution of all other terms is less than that of the op amp input noise voltage. As a minimum, the OPA2890 requires an RB value of 50Ω to damp out parasitic-induced peaking—a direct short to ground on the noninverting input runs the risk of a very high-frequency instability in the input stage. DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance that may be recommended to improve ADC linearity. A high-speed, high open-loop gain amplifier such as the OPA2890 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the open-loop output resistance of the amplifier is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series-isolation resistor between the amplifier output and the capacitive load. This solution does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended RS versus capacitive load (see Figure 15 and Figure 36) and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA2890. Long PCB traces, unmatched cables, and connections to multiple devices can easily exceed this value. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA2890 output pin (see the Board Layout Guidelines section). DISTORTION PERFORMANCE The OPA2890 provides good distortion performance into a 100Ω load on ±5V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single +5V supply. Generally, until the fundamental Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 23 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 signal reaches very high frequency or power levels, the 2nd harmonic dominates the distortion with a negligible 3rd harmonic component. Focusing then on the 2nd harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network; in the noninverting configuration (see Figure 49), this value is the sum of RF + RG, while in the inverting configuration it is only RF. Also, providing an additional supply-decoupling capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). Operating differentially also lowers 2nd-harmonic distortion terms (see the plot on the front page). In most op amps, increasing the output voltage swing increases harmonic distortion directly. The output stage used in the OPA2890 holds the difference between fundamental power and the 2nd- and 3rd-harmonic powers relatively constant with increasing output power until very large output swings are required ( > 4VPP). This also shows up in the two-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For two tones centered at 10MHz, with 4dBm/tone into a matched 50Ω load (that is, 1VPP for each tone at the load, which requires 4VPP for the overall two-tone envelope at the output pin), the Typical Characteristics show a 38dBc difference between the test tone powers and the 3rd-order intermodulation spurious powers. This exceptional performance for all 22.5mW internal power dissipation parts improves further when operating at lower frequencies or powers. NOISE PERFORMANCE High slew rate, unity-gain stable, voltage-feedback op amps usually achieve the slew rate at the expense of a higher input noise voltage. However, the 8nV/√Hz input voltage noise for the OPA2890 is much lower than that of comparable amplifiers. The input-referred voltage noise, and the two input-referred current noise terms, combine to give low output noise under a wide variety of operating conditions. Figure 60 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. 24 ENI 1/2 OPA2890 RS EO IBN ERS RF Ö4kTRS Ö4kTRF 4kT RG RG IBI 4kT = 1.6E - 20J at 290°K Figure 60. Op Amp Noise Analysis Model The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 4 shows the general form for the output noise voltage using the terms shown in Figure 60. EO = 2 2 2 2 [ENI + (IBNRS) + 4kTRS]NG + (IBIRF) + 4kTRFNG (4) Dividing this expression by the noise gain (NG = (1 + RF/RG)) gives the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 5. EN = 2 2 ( ) + 4kTR NG 2 ENI + (IBNRS) + 4kTRS + IBIRF NG F (5) Evaluating these two equations for the OPA2890 circuit and component values (see Figure 49) gives a total output spot noise voltage of 17.5nV/√Hz and a total equivalent input spot noise voltage of 8.7nV/√Hz. This result includes the noise added by the bias current cancellation resistor (350Ω) on the noninverting input. This total input-referred spot noise voltage is only slightly higher than the 8nV/√Hz specification for the op amp voltage noise alone. This result is the case as long as the impedances appearing at each op amp input are limited to the previously recommend maximum value of 400Ω. Keeping both (RF || RG) and the noninverting input source impedance less than 400Ω satisfies both noise and frequency response flatness considerations. Because the resistor-induced noise is relatively negligible, additional capacitive decoupling across the bias current cancellation resistor (RB) for the inverting op amp configuration of Figure 59 is not required. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 DC ACCURACY AND OFFSET CONTROL The balanced input stage of a wideband voltage-feedback op amp allows good output dc accuracy in a wide variety of applications. The power-supply current trim for the OPA2890 gives even tighter control than comparable amplifiers. Although the high-speed input stage does require relatively high input bias current (typically 5µA out of each input terminal), the close matching between them may be used to reduce the output dc error caused by this current. The total output offset voltage may be considerably reduced by matching the dc source resistances appearing at the two inputs. This matching reduces the output dc error resulting from the input bias currents to the offset current times the feedback resistor. Evaluating the configuration of Figure 49, and using worst-case +25°C input offset voltage and current specifications, gives a worst-case output offset voltage equal to: ±(NG ´ VOS(MAX)) ± (RF ´ IOS(MAX)) = ±(2 ´ 5mV) ± (750W ´ 1.6mA) = ±11.2mV with -(NG = noninverting signal gain) A fine-scale output offset null, or dc operating point adjustment, is often required. Numerous techniques are available for introducing dc offset control into an op amp circuit. Most of these techniques eventually reduce to adding a dc current through the feedback resistor. In selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. If the signal path is intended to be noninverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the noninverting input may be considered. However, the dc offset voltage on the summing junction sets up a dc current back into the source that must be considered. Applying an offset adjustment to the inverting op amp input can change the noise gain and frequency response flatness. For a DC-coupled inverting amplifier, Figure 61 shows one example of an offset adjustment technique that has minimal impact on the signal frequency response. In this case, the dc offsetting current is brought into the inverting input node through resistor values that are much larger than the signal path resistors. This configuration ensures that the adjustment circuit has minimal effect on the loop gain and thus, the frequency response. +5V Power-supply decoupling not shown. 261W 0.1mF 1/2 OPA2890 VO -5V RG 375W +5V 5kW RF 750W VI 20kW ±200mV Output Adjustment 10kW 0.1mF VO 5kW VI =- RF RG = -2 -5V Figure 61. DC-Coupled, Inverting Gain of –2, with Offset Adjustment DISABLE OPERATION (MSOP-10 Package Only) The OPA2890IDGS provides an optional disable feature that can be used either to reduce system power or to implement a simple channel multiplexing operation. If the DIS control pin is left unconnected, the OPA2890IDGS operates normally. To disable, the control pin must be asserted LOW. Figure 62 shows a simplified internal circuit for the disable control feature. +VS 50kW Q1 200kW VDIS 2MW IS Control -VS Figure 62. Simplified Disable Control Circuit Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 25 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 In normal operation, base current to Q1 is provided through the 2MΩ resistor, while the emitter current through the 50kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in the Q1 emitter. As VDIS is pulled LOW, additional current is pulled through the 50kΩ resistor, eventually turning on those two diodes (≈30µA). At this point, any further current pulled out of VDIS goes through those diodes holding the emitter-base voltage of Q1 at approximately 0V. This current shuts off the collector current out of Q1, turning the amplifier off. The supply currents in the disable mode are only those required to operate the circuit of Figure 62. Additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). When disabled, the output and input nodes go to a high-impedance state. If the OPA2890 is operating at a gain of +1V/V, the device shows a very high impedance at the output and exceptional signal isolation. If operating at a gain greater than +1V/V, the total feedback network resistance (RF + RG) appears as the impedance looking back into the output, but the circuit still shows very high forward and reverse isolation. If configured as an inverting amplifier, the input and output are connected through the feedback network resistance (RF + RG) and the isolation is very poor as a result. THERMAL ANALYSIS Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load; for a grounded resistive load, PDL is at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this condition, PDL = VS2/(4 × RL), where RL includes feedback network loading. Note that it is the power in the output stage and not into the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA2890ID (SO-8 package) in the circuit of Figure 49 operating at the maximum specified ambient temperature of +85°C and with both outputs driving a grounded 20Ω load to +2.5V. 2 PD = 10V ´ 2.5mA + 2[5 /(4 ´ (75W || 1.5kW))] = 200mW Maximum TJ = +85°C + (0.2W ´ 125°C/W) = 110°C This absolute worst-case condition does not exceed the specified maximum junction temperature. Actual PDL is normally less than that considered here. Carefully consider maximum TJ in your application. Maximum desired junction temperature sets the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed +150°C. 26 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 BOARD LAYOUT GUIDELINES Achieving optimum performance with a high-frequency amplifier such as the OPA2890 requires careful attention to board layout parasitics and external component types. Recommendations that optimize performance include: a) Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25in, or 6.35mm) from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. An optional supply decoupling capacitor (0.1µF) across the two power supplies (for bipolar operation) improves 2nd-harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These capacitors may be placed somewhat farther from the device and may be shared among several devices in the same area of the printed circuit board (PCB). c) Careful selection and placement of external components preserves the high-frequency performance of the OPA2890. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axially-leaded resistors can also provide good high-frequency performance. Again, keep the leads and PCB traces as short as possible. Never use wirewound type resistors in a high-frequency application. Because the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 1.5kΩ, this parasitic capacitance can add a pole and/or zero below 500MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load driving considerations. The 750Ω feedback used in the Electrical Characteristics is a good starting point for design. Note that a 0Ω feedback resistor is suggested for the unity-gain follower application. d) Connections to other wideband devices on the board may be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils, or 1.27mm to 2.54mm) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plots of Figure 15 and Figure 36. Low parasitic capacitive loads (< 3pF) may not need an RS because the OPA2890 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin; see Figure 61). If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined (based on board material and trace dimensions), a matching series resistor into the trace from the output of the OPA2890 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. e) Socketing a high-speed part such as the OPA2890 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network that can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA2890 onto the board. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 27 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 INPUT AND ESD PROTECTION +VCC The OPA2890 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 63. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (for example, in systems with ±15V supply parts driving into the OPA2890), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. 28 External Pin Internal Circuitry -VCC Figure 63. Internal ESD Protection Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 OPA2890 www.ti.com SBOS364A – DECEMBER 2007 – REVISED DECEMBER 2007 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (December, 2007) to Revision A ............................................................................................... Page • Corrected CMRR characteristic values.................................................................................................................................. 3 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA2890 29 PACKAGE OPTION ADDENDUM www.ti.com 17-Dec-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty OPA2890ID ACTIVE SOIC D 8 OPA2890IDGSR ACTIVE MSOP DGS OPA2890IDGST ACTIVE MSOP OPA2890IDR ACTIVE SOIC 75 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Dec-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant OPA2890IDGST DGS 10 SITE 41 180 12 5.3 3.4 1.4 8 12 Q1 OPA2890IDR D 8 SITE 41 330 12 6.4 5.2 2.1 8 12 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Dec-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) OPA2890IDGST DGS 10 SITE 41 184.0 184.0 50.0 OPA2890IDR D 8 SITE 41 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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