TI P82B96DR

P82B96
DUAL BIDIRECTIONAL BUS BUFFER
www.ti.com
SCPS144B – MAY 2006 – REVISED JULY 2007
FEATURES
•
•
•
•
•
•
Operating Power-Supply Voltage Range
of 2 V to 15 V
Can Interface Between I2C Buses Operating at
Different Logic Levels (2 V to 15 V)
Supports Bidirectional Data Transfer of I2C
Bus Signals
Allows Bus Capacitance of 400 pF on the Main
I2C Bus (Sx/Sy Side) and 4000 pF on the
Transmission Side (Tx/Ty)
Outputs on the Transmission Side (Tx/Ty)
Have High Sink Capability for Driving
Low-Impedance or High-Capacitive Buses
I2C Bus Signals Can Be Split Into Pairs of
•
•
•
•
Forward (Tx/Ty) and Reverse (Rx/Ry) Signals
for Interface With Optoelectrical Isolators and
Similar Devices That Need Unidirectional
Input and Output Signal Paths
400-kHz Fast I2C Bus Operation Over at Least
20 Meters of Wire
Low Standby Current Consumption
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 3500-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D PACKAGE
(TOP VIEW)
P PACKAGE
(TOP VIEW)
Sx
1
8
VCC
Rx
2
7
Sy
Tx
3
6
Ry
GND
4
5
Ty
PW PACKAGE
(TOP VIEW)
Sx
Rx
1
8
2
7
VCC
Sy
Tx
3
6
Ry
GND
4
5
Ty
Sx
Rx
Tx
GND
8
7
6
5
1
2
3
4
DGK PACKAGE
(TOP VIEW)
VCC
Sy
Ry
Ty
Sx
Rx
Tx
GND
1
2
3
4
8
7
6
5
VCC
Sy
Ry
Ty
DESCRIPTION/ORDERING INFORMATION
The P82B96 is a bipolar device that supports bidirectional data transfer between the normal I2C bus and a range
of other bus configurations with different voltage and current levels. It can function as the interface without any
limitations on the normal I2C operation and clock speed.
ORDERING INFORMATION
PACKAGE (1) (2)
TA
PDIP – P
SOIC – D
–40°C to 85°C
TSSOP – PW
VSSOP – DGK
(1)
(2)
ORDERABLE PART NUMBER
Tube of 50
P82B96P
Reel of 2000
P82B96DR
Tube of 75
P82B96D
Reel of 2000
P82B96PWR
Tube of 150
P82B96PW
Reel of 2500
P82B96DGKR
TOP-SIDE MARKING
P82B96P
PG96
PG96
7DS
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
www.ti.com
SCPS144B – MAY 2006 – REVISED JULY 2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
One of the advantages of the P82B96 is that it can isolate bus capacitance such that the total loading (devices
and trace lengths) of the new bus or remote I2C nodes are not apparent to other I2C buses (or nodes). This
device also adds minimal loading to I2C node where it is positioned. Any restrictions on the number of I2C
devices in a system, or the physical separation between them, are virtually eliminated.
The P82B96 easily can transmit SDA/SCL signals via balanced transmission lines (twisted pairs) or with
galvanic isolation (optocoupling), because separate directional Tx and Rx signals are provided. The Tx and Rx
signals may be connected directly (without causing bus latching), to provide an alternative bidirectional signal
line with I2C properties.
Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design does not support this configuration.
Bidirectional I2C signals do not allow any direction control pin so, instead, slightly different logic low-voltage
levels are used at Sx/Sy to avoid latching of this buffer. A regular I2C low applied at the Rx/Ry of a P82B96 is
propagated to Sx/Sy as a buffered low with a slightly higher voltage level. If this special buffered low is applied
to the Sx/Sy of another P82B96, the second P82B96 does not recognize it as a regular I2C bus low and does
not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to similar buffers that rely
on special logic thresholds for their operation, such as the PCA9515A.
The Sx/Sy side is intended only for, and compatible with, the normal I2C logic voltage levels of I2C master and
slave devices or Tx/Rx signals of a second P82B96, if required. The Tx/Rx and Ty/Ry I/O pins use the standard
I2C logic voltage levels of all I2C parts. If Rx and Tx are connected, Sx can function as either the SDA or SCL
line. Similarly, if Ry and Ty are connected, Sy can function as either the SDA or SCL line. There are no
restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or
multi-point configuration with the Tx/Rx and Ty/Ry I/O pins on the common bus, and the Sx/Sy side connected
to the line-card slave devices.
TERMINAL FUNCTIONS
2
NO.
NAME
1
Sx
Serial data bus or SDA. Connect to VCC of I2C master through a pullup resistor.
DESCRIPTION
2
Rx
Receive signal. Connect to VCC of P82B96 through a pullup resistor.
3
Tx
Transmit signal. Connect to VCC of P82B96 through a pullup resistor.
4
GND
5
Ty
Transmit signal. Connect to VCC of P82B96 through a pullup resistor.
6
Ry
Receive signal. Connect to VCC of P82B96 through a pullup resistor.
7
Sy
Serial clock bus or SCL. Connect to VCC of I2C master through a pullup resistor.
8
VCC
Supply voltage
Ground
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P82B96
DUAL BIDIRECTIONAL BUS BUFFER
www.ti.com
SCPS144B – MAY 2006 – REVISED JULY 2007
FUNCTIONAL BLOCK DIAGRAM
VCC (2–15 V)
8
Sx (SDA)
3
1
2
Sy (SCL)
5
7
6
Tx (TxD, SDA)
Rx (RxD, SDA)
Ty (TxD, SCL)
Ry (RxD, SCL)
P82B96
4
GND
Functional Description
Sx and Sy
The I2C pins, Sx and Sy, are designed to interface with a normal I2C bus. The logic threshold-voltage levels on
the I2C bus are independent of the supply VCC. The maximum I2C bus supply voltage is 15 V, and the specified
static sink current is 3 mA.
Sx and Sy have two identical buffers. Each buffer is made up of two logic signal paths. The first one, named Tx
or Ty, is a forward path from the I2C interface pin, which drives the buffered bus. The second one, named Rx or
Ry, is a reverse signal path from the buffered bus input to drive the I2C bus interface.
There are two purposes for these paths: to sense the voltage state of the I2C pin (Sx or Sy) and transmit this
state to Tx or Ty, respectively, and to detect the state of the Rx or Ry and pull the I2C pin low when Rx or Ry is
low.
Tx and Ty
Tx and Ty are open-collector outputs without ESD protection diodes to VCC. Each pin may be connected via a
pullup resistor to a supply voltage in excess of VCC, as long as the 15-V rating is not exceeded. Tx and Ty have
a larger current-sinking capability than a normal I2C device and can sink a static current of greater than 30 mA.
They also have dynamic pulldown capability of 100-mA, typically.
A logic low is transmitted to Tx or Ty only when the voltage at the I2C pin (Sx or Sy) is below 0.6 V. A logic low
at Rx or Ry causes the I2C bus (Sx or Sy) to be pulled to a logic low level in accordance with I2C requirements
(maximum 1.5 V in 5-V applications), but not low enough to be looped back to the Tx or Ty output and cause the
buffer to latch low.
The minimum low level that the P82B96 can achieve on the I2C bus by a low at Rx or Ry typically is 0.8 V.
If VCC fails, neither the I2C pins nor the Tx or Ty outputs are held low. Their open-collector configuration allows
them to be pulled up to the rated maximum of 15 V without VCC present. The input configuration on Sx, Sy, Rx,
and Ry also presents no loading of external signals when VCC is not present.
The effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than 4 pF for
all bus voltages and supply voltages, including VCC = 0 V.
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P82B96
DUAL BIDIRECTIONAL BUS BUFFER
www.ti.com
SCPS144B – MAY 2006 – REVISED JULY 2007
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
–0.3
18
Sx or Sy (SDA or SCL)
–0.3
18
Rx or Ry
–0.3
18
Sx or Sy (SDA or SCL)
–0.3
18
Tx or Ty
–0.3
18
Supply voltage range
VI
Voltage range on buffered input
VO
Voltage range on buffered output
IO
Continuous output current
ICC
Continuous current through VCC or GND
Sx or Sy
250
Tx or Ty
250
250
D package
V
V
V
mA
mA
97
P package
Package thermal impedance (2)
θJA
UNIT
85
PW package
149
DGK package
172
°C/W
Tstg
Storage temperature range
–55
125
°C
TA
Operating free-air temperature range
–40
85
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
VCC
4
Supply voltage
IOL
Low-level output current
VIOmax
Maximum input/output voltage level
VILdiff
Low-level input voltage difference
TA
Operating free-air temperature
MIN
MAX
2
15
Sx, Sy
VSx, VSy = 1 V, VRx, VRy ≤ 0.42 V
3
Tx, Ty
VSx, VSy = 0.4 V, VTx, VTy = 0.4 V
30
Sx, Sy
VTx, VTy = 0.4 V
15
Tx, Ty
VSx, VSy = 0.4 V
15
Sx, Sy
–40
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UNIT
V
mA
V
0.4
V
85
°C
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
www.ti.com
SCPS144B – MAY 2006 – REVISED JULY 2007
Electrical Characteristics
VCC = 2.3 V to 2.7 V, voltages are specified with respect to GND (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
ΔV/ΔTIN
Temperature coefficient of
input thresholds
Sx, Sy
VOL
Low-level output voltage
Sx, Sy
ΔV/ΔTOUT
Temperature coefficient of
output low levels (3)
Sx, Sy
ICC
Quiescent supply current
ΔICC
Additional supply current
per pin low
Dynamic output sink
capability on I2C bus
IIOS
Sx, Sy
Tx, Ty
Leakage current
on buffered bus
Input current
from buffered bus
II
Leakage current
on buffered bus input
Sx, Sy
Rx, Ry
VIT
ISx, ISy = 3 mA
ISx, ISy = 0.2 mA
Input threshold
0.88
1
0.73
0.79
VSx, VSy > 2 V,
VRx, VRy = low
7
VSx, VSy = 2.5 V,
VRx, VRy = high
VTx, VTy > 1 V,
VSx, VSy = low on
I2C bus = 0.4 V
mV/°C
1.8
2
mA
1.7
2.75
3
mA
18
5.5
1
100
mA
1
60
0.1
Bus low, VRx,
VRy = high
–1
1
Bus low, VRx,
VRy = 0.4 V
–1
1
1
1.5
Input logic level low
threshold (4)
on normal I2C bus
0.65
0.6
1
1
μA
μA
(2)
0.7
(2)
0.65
V
0.58 VCC
Input threshold
μA
mA
VTx, VTy = VCC =
2.5 V,
VSx, VSy = high
Input logic level high
threshold (4)
on normal I2C bus
V
0.9
0.1
60
UNIT
(2)
(2)
–1.8
0.58 VCC
0.5 VCC
Input logic level low
0.42 VCC
VIOdiff
Input/output logic level
difference (5)
Sx, Sy
(VSx output low
at 3 mA) –
(VSx input high max)
for I2C applications
VIOrel
VCC voltage at which all
buses are released
Sx, Sy
Tx, Ty
Sx, Sy are low, VCC
ramping, voltage on
Tx, Ty lowered until
released
ΔV/ΔTREL
Temperature coefficient of release
voltage
–4
Cin
Input capacitance
2.5
(1)
(2)
(3)
(4)
(5)
MAX
mV/°C
0.8
ISx, ISy = 0.2 mA
Input logic level high
Rx, Ry
MIN
0.67
VRx, VRy = VCC
Sx, Sy
TA = –40°C to 85°C
MAX
–2
Tx, Ty
IIOT
Input current from I2C bus
TYP (1)
Sx = Sy = VCC
Leakage current on I2C bus
Dynamic output sink
capability on buffered bus
TA = 25°C
MIN
100
1
Rx, Ry
150
0.42 VCC
100
mV
1
V
mV/°C
4
4
pF
Typical value is at VCC = 2.5 V, TA = 25°C
See the Typical Characteristics section of this data sheet.
The output logic low depends on the sink current.
The input logic threshold is independent of the supply voltage.
The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for VSX output low always exceeds the
minimum VSx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.
While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices should never be linked,
because the resulting system would be very susceptible to induced noise and would not support all I2C operating modes.
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P82B96
DUAL BIDIRECTIONAL BUS BUFFER
www.ti.com
SCPS144B – MAY 2006 – REVISED JULY 2007
Electrical Characteristics
VCC = 3 V to 3.6 V, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ΔV/ΔTIN
Temperature
coefficient of
input thresholds
Sx, Sy
VOL
Low-level output
voltage
Sx, Sy
ΔV/ΔTOUT
Temperature
coefficient of
output low
levels (3)
Sx, Sy
ICC
Quiescent supply current
ΔICC
Additional supply
current per pin
low
Dynamic output
sink capability
on I2C bus
IIOS
IIOT
Sx, Sy
ISx, ISy = 0.2 mA
VSx, VSy > 2 V,
VRx, VRy = low
VTx, VTy > 1 V,
VSx, VSy = low on I2C
bus = 0.4 V
Sx, Sy
Leakage current
on buffered bus
input
1
0.67
0.73
0.79
7
V
mV/°C
0.9
1.8
2
mA
1.7
2.75
3
mA
18
0.1
60
UNIT
(2)
(2)
–1.8
5.7
1
100
mA
1
60
0.1
Bus low, VRx,
VRy = high
–1
1
Bus low, VRx,
VRy = 0.4 V
–1
1
1
1.5
1
μA
mA
VTx, VTy = VCC =
3.3 V, VSx, VSy = high
VRx, VRy = VCC
Input threshold
Input logic-level high
threshold (4)
on normal I2C bus
Input logic-level low
threshold (4)
on normal I2C bus
Input logic level high
Rx, Ry
0.65
0.6
1
μA
μA
VIOdiff
Input/output logic
level difference (5)
Sx, Sy
(VSx output low
at 3 mA) –
(VSx input high max)
for I2C applications
VIOrel
VCC voltage at
which all buses
are released
Sx, Sy
Tx, Ty
Sx, Sy are low, VCC
ramping, voltage on
Tx, Ty lowered until
released
(2)
V
0.58 VCC
Input threshold
(2)
0.7
0.65
0.58 VCC
0.5 VCC
Input logic level low
6
MAX
Rx, Ry
Sx, Sy
(1)
(2)
(3)
(4)
(5)
MIN
mV/°C
0.88
Sx = Sy = VCC
Dynamic output
sink capability
on buffered bus
Tx, Ty
TA = –40°C to 85°C
MAX
0.8
ISx, ISy = 0.2 mA
VSx, VSy = 5 V,
VRx, VRy = high
Input current
from buffered bus
VIT
ISx, ISy = 3 mA
Tx, Ty
Leakage current
on buffered bus
II
TYP (1)
–2
Leakage current
on I2C bus
Input current
from I2C bus
TA = 25°C
MIN
0.42 VCC
100
1
150
0.42 VCC
100
1
mV
V
Typical value is at VCC = 3.3 V, TA = 25°C
See the Typical Characteristics section of this data sheet.
The output logic low depends on the sink current.
The input logic threshold is independent of the supply voltage.
The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for VSX output low always exceeds the
minimum VSx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.
While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices never should be linked,
because the resulting system would be very susceptible to induced noise and would not support all I2C operating modes.
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P82B96
DUAL BIDIRECTIONAL BUS BUFFER
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SCPS144B – MAY 2006 – REVISED JULY 2007
Electrical Characteristics (continued)
VCC = 3 V to 3.6 V, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
MIN
TYP
(1)
ΔV/ΔTREL
Temperature coefficient of
release voltage
–4
Cin
Input capacitance
2.5
Rx, Ry
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TA = –40°C to 85°C
MAX
MIN
MAX
UNIT
mV/°C
4
4
pF
7
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
www.ti.com
SCPS144B – MAY 2006 – REVISED JULY 2007
Electrical Characteristics
VCC = 4.5 V to 5.5 V, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ΔV/ΔTIN
Temperature
coefficient of
input thresholds
Sx, Sy
VOL
Low-level output
voltage
Sx, Sy
ΔV/ΔTOUT
Temperature
coefficient of
output low
levels (3)
Sx, Sy
ICC
Quiescent supply current
ΔICC
Additional supply
current
per pin low
Dynamic output
sink capability
on I2C bus
IIOS
IIOT
Sx, Sy
ISx, ISy = 0.2 mA
VSx, VSy > 2 V,
VRx, VRy = low
VTx, VTy > 1 V,
VSx, VSy = low on
I2C bus = 0.4 V
Sx, Sy
Leakage current
on buffered bus
input
1
0.67
0.73
0.79
7
V
mV/°C
0.9
1.8
2
mA
1.7
2.75
3
mA
18
0.1
60
UNIT
(2)
(2)
–1.8
6
1
100
mA
1
60
0.1
Bus low, VRx,
VRy = high
–1
1
Bus low, VRx,
VRy = 0.4 V
–1
1
1
1.5
1
μA
mA
VTx, VTy = VCC =
5 V, VSx, VSy = high
VRx, VRy = VCC
Input threshold
Input logic-level high
threshold (4)
on normal I2C bus
Input logic-level low
threshold (4)
on normal I2C bus
Input logic level high
Rx, Ry
0.65
0.6
1
μA
μA
VIOdiff
Input/output logic
level difference (5)
Sx, Sy
(VSx output low at
3 mA) –
(VSx input high max)
for I2C applications
VIOrel
VCC voltage at
which all buses
are released
Sx, Sy
Tx, Ty
Sx, Sy are low, VCC
ramping, voltage on
Tx, Ty lowered until
released
(2)
V
0.58 VCC
Input threshold
(2)
0.7
0.65
0.58 VCC
0.5 VCC
Input logic level low
8
MAX
Rx, Ry
Sx, Sy
(1)
(2)
(3)
(4)
(5)
MIN
mV/°C
0.88
Sx = Sy = VCC
Dynamic output
sink capability
on buffered bus
Tx, Ty
TA = –40°C to 85°C
MAX
0.8
ISx, ISy = 0.2 mA
VSx, VSy = 5 V,
VRx, VRy = high
Input current
from buffered bus
VIT
ISx, ISy = 3 mA
Tx, Ty
Leakage current
on buffered bus
II
TYP (1)
–2
Leakage current
on I2C bus
Input current
from I2C bus
TA = 25°C
MIN
0.42 VCC
100
1
150
0.42 VCC
100
1
mV
V
Typical value is at VCC = 5 V, TA = 25°C
See the Typical Characteristics section of this data sheet.
The output logic low depends on the sink current.
The input logic threshold is independent of the supply voltage.
The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for VSX output low always exceeds the
minimum VSx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.
While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices never should be linked,
because the resulting system would be very susceptible to induced noise and would not support all I2C operating modes.
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DUAL BIDIRECTIONAL BUS BUFFER
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SCPS144B – MAY 2006 – REVISED JULY 2007
Electrical Characteristics (continued)
VCC = 4.5 V to 5.5 V, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
MIN
TYP
(1)
ΔV/ΔTREL
Temperature coefficient of
release voltage
–4
Cin
Input capacitance Rx, Ry
2.5
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TA = –40°C to 85°C
MAX
MIN
MAX
UNIT
mV/°C
4
4
pF
9
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
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SCPS144B – MAY 2006 – REVISED JULY 2007
Electrical Characteristics
VCC = 15 V, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ΔV/ΔTIN
Temperature
coefficient of
input thresholds
Sx, Sy
VOL
Low-level output
voltage
Sx, Sy
ΔV/ΔTOUT
Temperature
coefficient of
output low
levels (3)
Sx, Sy
ICC
Quiescent supply
current
ΔICC
Additional supply
current
per pin low
Dynamic output
sink capability
on I2C bus
IIOS
IIOT
Sx, Sy
ISx, ISy = 0.2 mA
VSx, VSy > 2 V,
VRx, VRy = low
Dynamic output
sink capability
on buffered bus
VTx, VTy > 1 V,
VSx, VSy = low on
I2C bus = 0.4 V
Sx, Sy
Leakage current
on buffered bus
input
0.67
0.73
0.79
Rx, Ry
10
mV/°C
1.8
2
mA
1.7
2.75
3
mA
18
0.1
60
V
0.9
6.5
1
100
mA
1
60
0.1
Bus low, VRx,
VRy = high
–1
1
Bus low, VRx,
VRy = 0.4 V
–1
1
1
1.5
1
μA
mA
VTx, VTy = VCC =
15 V,
VSx, VSy = high
Input logic-level high
threshold (4)
on normal I2C bus
0.65
Input logic-level high
threshold (4)
on normal I2C bus
0.6
1
μA
μA
Input logic level high
0.58 VCC
Input threshold
Sx, Sy
(VSx output low at
3 mA) –
(VSx input high max)
for I2C applications
(2)
0.7
(2)
0.65
V
0.58 VCC
0.5 VCC
Input logic level low
(1)
(2)
(3)
(4)
(5)
(2)
(2)
–1.8
7
UNIT
mV/°C
1
VRx, VRy = VCC
Input threshold
Input/output logic
level difference (5)
MAX
Rx, Ry
Sx, Sy
VIOdiff
MIN
0.88
ISx, ISy = 0.2 mA
VSx, VSy = 15 V,
VRx, VRy = high
Tx, Ty
TA = –40°C to 85°C
MAX
0.8
Tx, Ty
Input current
from buffered bus
VIT
ISx, ISy = 3 mA
Sx = Sy = VCC
Leakage current
on buffered bus
II
TYP (1)
–2
Leakage current
on I2C bus
Input current
from I2C bus
TA = 25°C
MIN
0.42 VCC
100
150
0.42 VCC
100
mV
Typical value is at VCC = 15 V, TA = 25°C
See the Typical Characteristics section of this data sheet.
The output logic low depends on the sink current.
The input logic threshold is independent of the supply voltage.
The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for VSX output low always exceeds the
minimum VSx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.
While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices never should be linked,
because the resulting system would be very susceptible to induced noise and would not support all I2C operating modes.
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Electrical Characteristics (continued)
VCC = 15 V, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Sx, Sy are low, VCC
ramping, voltage on
Tx, Ty lowered until
released
TA = 25°C
MIN
TYP
(1)
VIOrel
VCC voltage at
which all buses
are released
ΔV/ΔTREL
Temperature coefficient of
release voltage
–4
Cin
Input capacitance Rx, Ry
2.5
Sx, Sy
Tx, Ty
TA = –40°C to 85°C
MAX
MIN
1
UNIT
MAX
1
V
mV/°C
4
4
pF
Switching Characteristics
VCC = 5 V, TA = 25°C, no capacitive loads, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
TYP UNIT
tpzl
Buffer delay time on falling
input (1)
VSx (or VSy) = input switching
threshold
VTx (or VTy) output falling
50% of VLOAD
RTx pullup = 160 Ω,
CTx = 7 pF + board
trace capacitance
70
ns
tplz
Buffer delay time on rising
input (2)
VSx (or VSy) = input switching
threshold
VTx (or VTy) output
reaching 50% of VLOAD
RTx pullup = 160 Ω,
CTx = 7 pF + board
trace capacitance
90
ns
tpzl
Buffer delay time on falling
input (3)
VRx (or VRy) = input switching
threshold
VSx (or VSy) output falling
50% of VLOAD
RSx pullup = 1500 Ω,
CTx = 7 pF + board
trace capacitance
250
ns
tplz
Buffer delay time on rising
input (4)
VRx (or VRy) = input switching
threshold
VSx (or VSy) output
reaching 50% of VLOAD
RSx pullup = 1500 Ω,
CTx = 7 pF + board
trace capacitance
270
ns
(1)
(2)
(3)
(4)
The fall time of VTx from 5 V to 2.5 V in the test is approximately 15 ns.
The fall time of VSx from 5 V to 2.5 V in the test is approximately 50 ns.
The rise time of VTx from 0 V to 2.5 V in the test is approximately 20 ns.
The rise time of VSx from 0.9 V to 2.5 V in the test is approximately 70 ns.
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DUAL BIDIRECTIONAL BUS BUFFER
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SCPS144B – MAY 2006 – REVISED JULY 2007
TYPICAL CHARACTERISTICS
VOL AT Sx
vs
JUNCTION TEMPERATURE
IOL = 0.2 mA
VOL AT Sx
vs
JUNCTION TEMPERATURE
IOL = 3 mA
1200
800
600
Typical
0
25
Typical
800
600
Minimum
400
-50 –25
Maximum
1000
Maximum
VOL – mV
VOL – mV
1000
Minimum
400
-50 –25
50 75 100 125
0
VIH(min) AT Sx
vs
JUNCTION TEMPERATURE
1000
1000
800
800
VIH(min) – mV
VIL(max) – mV
VIL(max) AT Sx
vs
JUNCTION TEMPERATURE
600
400
0
600
400
200
-50 –25
25 50 75 100 125
Tj – °C
VCC(max)
vs
JUNCTION TEMPERATURE
1400
VCC(max) – mV
1200
1000
800
600
400
-50 –25
12
50 75 100 125
Tj – °C
Tj – °C
200
-50 –25
25
0
25 50 75 100 125
Tj – °C
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0
25 50 75 100 125
Tj – °C
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
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SCPS144B – MAY 2006 – REVISED JULY 2007
PARAMETER MEASUREMENT INFORMATION
VCC
VIN
VCC
VOUT
PULSE
GENERATOR
RL = 160 to 1500 W
S1
DUT
GND
CL = Probe and jig capacitance
(see Note A)
RT
TEST
S1
tPLZ/tPZL
VCC
TEST CIRCUIT FOR OPEN-DRAIN OUTPUT
VCC
0.6 V
0V
Sx or Sy
tPZL
tPLZ
VCC
0.5 ´ VCC
Tx or Ty
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
Figure 1. Test Circuit and Voltage Waveforms
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DUAL BIDIRECTIONAL BUS BUFFER
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SCPS144B – MAY 2006 – REVISED JULY 2007
APPLICATION INFORMATION
Typical Applications
Figure 2 through Figure 4 show typical applications for the P82B96.
VCC (2–15V)
5V
R1
Tx
(SDA)
2
IC
SDA
SDA
(New Levels)
Rx
(SDA)
1/2 PB2B96
Figure 2. Interfacing I2C Bus With Different Logic Levels
VCC1
VCC
R4
R2
R5
R3
I2C
SDA
5V
Rx
(SDA)
R1
2
IC
SDA
Tx
(SDA)
1/2 P82B96
Figure 3. Galvanic Isolation of I2C Nodes
Main Enclosure
Remote-Control Enclosure
12 V
12 V
3.3–5 V
3.3–5 V
Long Cables
SCL
SCL
3.3–5 V
12 V
3.3–5 V
SDA
SDA
P82B96
P82B96
Figure 4. Long-Distance I2C Communications
14
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DUAL BIDIRECTIONAL BUS BUFFER
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SCPS144B – MAY 2006 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
Figure 5 shows how a master I2C bus can be protected against short circuits or failures in applications that
involve plug/socket connections and long cables that may become damaged. A simple circuit is added to
monitor the SDA bus and, if its low time exceeds the design value, disconnect the master bus. P82B96 frees all
of its I/Os if its supply is removed, so one option is to connect its VCC to the output of a logic gate from, for
example, the LVC family. The SDA and SCL lines could be timed, and VCC disabled via the gate, if a line
exceeds a design value of the low period. If the supply voltage of logic gates restricts the choice of VCC supply,
the low-cost discrete circuit in Figure 5 can be used. If the SDA line is held low, the 100-nF capacitor charges,
and Ry is pulled toward VCC. When it exceeds VCC/2, Ry sets Sy high, which effectively releases it.
V
VCC
Rx
SCL
Sx
100 kW
+V Cable Drive
100 nF
VCC1
+V Cable Drive
VCC2
VCC
BC
847B
3-m to 20-m Cables
Rx
Sx
Tx
Tx
SCL
2
Ty
2
I C/DDC
Master
2
I C/DDC
4700 W
Ty
Ry
SDA
Sy
I C/DDC
Slave
Ry
Sy
SDA
470 kW
BC
847B
P82B96
P82B96
470 kW
GND
Monitor/Flat TV
GND
PC/TV Receiver/Decoder Box
R
G
B
Video Signals
Figure 5. Extending DCC Bus
In this example, the SCL line is made unidirectional by tying Rx to VCC. The state of the buffered SCL line
cannot affect the master clock line, which is allowed when clock stretching is not required. It is simple to add an
additional transistor or diode to control the Rx input in the same way as Ry, when necessary. The +V cable drive
can be any voltage up to 15 V, and the bus may be run at a lower impedance by selecting pullup resistors for a
static sink current up to 30 mA. VCC1 and VCC2 may be chosen to suit the connected devices. Because DDC
uses relatively low speeds (<100 kHz), the cable length is not restricted to 20 m by the I2C signaling, but it may
be limited by the video signaling.
Figure 6 and Table 1 show that P82B96 can achieve high clock rates over long cables. While calculating with
lumped wiring capacitance yields reasonable approximations to actual timing; even 25 m of cable is better
treated using transmission line theory. Flat ribbon cables connected as shown, with the bus signals on the outer
edge, have a characteristic impedance in the range 100–200 Ω. For simplicity, they cannot be terminated in their
characteristic impedance, but a practical compromise is to use the minimum pullup allowed for P82B96 and
place half this termination at each end of the cable. When each pullup is below 330 Ω, the rising-edge
waveforms have their first voltage step level above the logic threshold at Rx, and cable timing calculations can
be based on the fast rise/fall times of resistive loading, plus simple one-way propagation delays. When the
pullup is larger, but below 750 Ω, the threshold at Rx is crossed after one signal reflection. So, at the sending
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DUAL BIDIRECTIONAL BUS BUFFER
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SCPS144B – MAY 2006 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
end, it is crossed after two times the one-way propagation delay and, at the receiving end, after three times that
propagation delay. For flat cables with partial plastic dielectric insulation (by using outer cores) the one-way
propagation delays are about 5 ns/m. The 10% to 90% rise and fall times on the cable are between 20 ns and
50 ns, so their delay contributions are small. There is ringing on falling edges that can be damped, if required,
using Schottky diodes, as shown.
+V Cable Drive
VCC1
R2
VCC2
R2
R2
VCC
SCL
Sx
I2C
MASTER
SDA
Sy
R1
R1
R1
R1
R2
VCC
Rx
Rx
Tx
Tx
Ty
Ty
Ry
Ry
Sx
SCL
I2C
SLAVE(S)
Sy
SDA
Cable
P82B96
C2
P82B96
Propagation
Delay = 5 ns/m
C2
C2
C2
GND
GND
BAT54A
BAT54A
Figure 6. Driving Ribbon or Flat Telephone Cables
Table 1. Bus Capabilities
MASTER SCL
PULSE
DURATION
(ns)
BUS
CLOCK
SPEED
(kHz)
MAXIMUM
SLAVE
RESPONSE
DELAY
4000
120
(2)
600
2600
185
(2)
125
600
1500
390
(2)
15
600
1000
500
600 ns
VCC1
(V)
+V
CABLE
(V)
VCC2
(V)
R1
(Ω)
R2
(kΩ)
C2
(pF)
HIGH
LOW
5
12
5
750
2.2
400
250
(1)
1250
600
5
12
5
750
2.2
220
100
(1)
500
3.3
5
3.3
330
1
220
25
1 nF
3.3
5
3.3
330
1
100
3
120 pF
(1)
(2)
CABLE
CABLE
CABLE
LENGTH
DELAY
CAPACITANCE
(m)
(ns)
Not applicable; calculations are delay based.
Normal 400-kHz bus specification
When the master SCL high and low periods can be programmed separately, the timings can allow for bus
delays. The low period should be programmed to achieve the minimum 1300 ns plus the net delay in the slave
response data signal caused by bus and buffer delays. The longest data delay is the sum of the delay of the
falling edge of SCL from master to slave and the delay of the rising edge of SDA from slave data to master.
Because the buffer stretches the programmed SCL low period, the actual SCL frequency is lower than
calculated from the programmed clock periods. In the example for the 25-m cable in Table 1, the clock is
stretched 400 ns, the falling edge of SCL is delayed 490 ns, and the SDA rising edge is delayed 570 ns. The
required additional low period is (490 + 570) = 1060 ns and the I2C bus specifications already include an
allowance for a worst-case bus rise time (0% to 70%) of 425 ns. The bus rise time can be 300 ns (30% to 70%),
which means it can be 425 ns (0% to 70%). The 25-m cable delay times include all rise and fall times.
Therefore, the device only needs to be programmed with an additional (1060 – 400 – 425) = 235 ns, making a
total programmed low period 1535 ns. The programmed low is stretched by 400 ns to yield an actual bus low
time of 1935 ns, which, allowing the minimum high period of 600 ns, yields a cycle period of 2535 ns or 394 kHz.
16
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SCPS144B – MAY 2006 – REVISED JULY 2007
Note that, in both the 100-m and 250-m examples, the capacitive loading on the I2C buses at each end is within
the maximum allowed Standard mode loading of 400 pF, but exceeds the Fast mode limit. This is an example of
a hybrid mode, because it relies on the response delays of Fast mode parts, but uses (allowable) Standard
mode bus loadings with rise times that contribute significantly to the system delays. The cables cause large
propagation delays. Therefore, these systems must operate well below the 400-kHz limit, but illustrate how they
still can exceed the 100-kHz limit, provided all parts are capable of Fast mode operation. The fastest example
illustrates how the 400-kHz limit can be exceeded, provided master and slave parts have delay specifications
smaller than the maximum allowed. Many TI slaves have delays shorter than 600 ns, but none have that
specified.
Calculating System Delays and Bus-Clock Frequency for Fast Mode System
Figure 7 through Figure 9 show the P82B96 used to drive extended bus wiring, with relatively large capacitance,
linking two Fast mode I2C bus nodes. It includes simplified expressions for making the relevant timing
calculations for 3.3-/5-V operation. Because the buffers and the wiring introduce timing delays, it may be
necessary to decrease the nominal SCL frequency below 400 kHz. In most cases, the actual bus frequency is
lower than the nominal master timing, due to bit-wise stretching of the clock periods.
Buffered Expansion Bus
Local Master Bus
Remote Slave Bus
VCCB
VCCM
MASTER
VCCS
Rb
Rm
SCL
Sx
I2C
P82B96
Tx/Rx
Rs
SCL
SLAVE
Sx
Tx/Rx
P82B96
Cb = Buffered Bus
Wiring Capacitance
Cm = Master Bus
Capacitance
Cs = Slave Bus
Capacitance
I2C
GND
Falling edge of SCL at master is delayed by the buffers and bus fall times.
9
Effective Delay of SCL at Slave = 255 + 17 VCCM + (2.5 + 4 × 10 Cb) VCCB (ns)
C = F, V = Volts
Figure 7.
Buffered Expansion Bus
Local Master Bus
VCCB
VCCM
MASTER
SCL
Rb
Rm
Sx
P82B96
Tx/Rx
Tx/Rx
2
IC
Cm = Master Bus
Capacitance
Cb = Buffered Bus
Wiring Capacitance
GND
Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times.
Effective delay of SCL at master = 270 + RmCm + 0.7RbCb (ns)
C = F, R = Ω
Figure 8.
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SCPS144B – MAY 2006 – REVISED JULY 2007
Buffered Expansion Bus
Local Master Bus
VCCM
Remote Slave Bus
VCCS
VCCB
MASTER
SDA
Rm
Rs
Rb
Sx
P82B96
Tx/Rx
Tx/Rx
P82B96
SDA
SLAVE
Sx
I2C
I2C
Cm = Master Bus
Capacitance
Cb = Buffered Bus
Wiring Capacitance
Cs = Slave Bus
Capacitance
GND
Rising edge of SDA at slave is delayed by the buffers and bus rise times.
Effective delay of SDA at master = 270 + 0.2RsCs + 0.7(RbCb + RmCm) (ns)
C = F, R = Ω
Figure 9.
The delay factors involved in calculation of the allowed bus speed are:
1. The propagation delay of the master signal through the buffers and wiring to the slave. The important
delay is that of the falling edge of SCL, because this edge requests the data or ACK from a slave.
2. The effective stretching of the nominal low period of SCL at the master, caused by the buffer and bus rise
times.
3. The propagation delay of the slave response signal through the buffers and wiring back to the master.
The important delay is that of a rising edge in the SDA signal. Rising edges always are slower and,
therefore, are delayed by a longer time than falling edges. (The rising edges are limited by the passive
pullup, while falling edges actively are driven.)
The timing requirement in any I2C system is that a slave’s data response (which is provided in response to a
falling edge of SCL) must be received at the master before the end of the corresponding low period of SCL as it
appears on the bus wiring at the master. Because all slaves, as a minimum, satisfy the worst-case timing
requirements of a 400-kHz part, they must provide their response within the minimum allowed clock low period
of 1300 ns. Therefore, in systems that introduce additional delays, it is necessary only to extend that minimum
clock low period by any effective delay of the slave response. The effective delay of the slave's response equals
the total delays in SCL falling edge from the master reaching the slave (A) minus the effective delay (stretch) of
the SCL rising edge (B) plus total delays in the slave response data, carried on SDA, and reaching the master
(C).
The master microcontroller should be programmed to produce a nominal SCL low period
of (1300 + A – B + C) ns and should be programmed to produce the nominal minimum SCL high period of
600 ns. Then, a check should be made to ensure the cycle time is not shorter than the minimum 2500 ns. If
found to be necessary, increase either clock period.
Due to clock stretching, the SCL cycle time always is longer than (600 + 1300 + A + C) ns.
18
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SCPS144B – MAY 2006 – REVISED JULY 2007
Sample Calculations
The master bus has an RmCm product of 100 ns and VCCM = 5 V.
The buffered bus has a capacitance of 1 nF and a pullup resistor of 160 Ω to 5 V, giving an RbCb product of
160 ns. The slave bus also has an RsCs product of 100 ns.
The master low period should be programmed to be ≥(1300 + 372.5 – 482 + 472) ns, which calculates to
≥1662.5 ns.
The master high period may be programmed to the minimum 600 ns. The nominal master clock period is
≥(1662.5 + 600) ns = 2262.5 ns, equivalent to a frequency of 442 kHz.
The
actual
bus-clock
period,
including
the
482-ns
clock
stretch
effect,
is
(nominal + stretch) = (2262.5 + 482) ns or ≥2745 ns, equivalent to an allowable frequency of 364 kHz.
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19
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jul-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
P82B96D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P82B96DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P82B96DGKR
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P82B96DGKRG4
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P82B96DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P82B96DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P82B96P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
P82B96PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
P82B96PW
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P82B96PWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P82B96PWR
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P82B96PWRG4
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jul-2007
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
P82B96DGKR
Package Package Pins
Type Drawing
MSOP
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
P82B96DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
P82B96PWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
P82B96DGKR
MSOP
DGK
8
2500
358.0
335.0
35.0
P82B96DR
SOIC
D
8
2500
346.0
346.0
29.0
P82B96PWR
TSSOP
PW
8
2000
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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