ONSEMI NCP5215

NCP5215
Dual Synchronous Buck
Controller for Notebook
Power System
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MARKING
DIAGRAM
QFN40
MN SUFFIX
CASE 488AR
A
WL
YY
WW
G
Features
• Wide Input Voltage Range: 4.5 V to 24 V
• Adjustable Output Voltage Range: 0.8 V to 3.0 V
• Selectable Nominal Fixed Switching Frequency:
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
31 TG1
32 SWN1
33 CS1+
34 CS1−/Vo1
35 ILMT1
36 VDRP1
37 FB1
38 INV1
39 COMP1
40 TRESET1
PIN CONNECTIONS
FSET
1
30 BST1
VCC
2
29 VCCP1
AGND
3
28 BG1
VREF
4
27 PGND1
PGOOD1
5
PGOOD2
6
EN1
7
24 PGND2
EN2
8
23 BG2
SS1
9
22 VCCP2
26 VIN
NCP5215
25 FPWM#
TG2 20
SWN2 19
CS2+ 18
CS2−/Vo2 17
ILIM2 16
VDRP2 15
21 BST2
FB2 14
SS2 10
COMP2 12
200 kHz, 300 kHz, and 400 kHz
180° Interleaved Operation Function between the Two Channels
Programmable Adaptive−Voltage−Positioning (AVP) Operation
Programmable Transient−Response−Enhancement (TRE) Control
Power Saving Operation under Light Load Condition
Input Feedforward Voltage Mode Control
Resistive or Inductor’s DCR Current Sensing
1% Internal 0.8 V Reference
External Soft−Start Operation
Output Discharge and Soft−Stop
Built−in Gate Drivers
Input Supplies Undervoltage Lockout
Output Overvoltage and Undervoltage Protections
Accurate Overcurrent Protection
Thermal Shutdown Protection
QFN40 Package
This is a Pb−Free Device
TRESET2 11
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NCP5215
AWLYYWWG
1 40
INV2 13
The NCP5215, a high−efficiency and fast−transient−response
dual−channel buck controller, provides a multifunctional power
solution for notebook power system. 180o interleaved operation
function between the two channels has capabilities of reducing the
common input capacitor requirement and improving noise immunity.
Adaptive−Voltage−Positioning (AVP) control reduces the
requirement of output filter capacitors. Programmable power−saving
operation ensures high efficiency over entire load range. Input
feedforward voltage−mode control is employed to deal with wide
input voltage range. Transient−Response−Enhancement (TRE)
control for the both channels enables fast transient response.
(Top View)
Typical Applications
• Notebook Computers
• CPU Chipset Power Supplies
ORDERING INFORMATION
Device
Package
Shipping
NCP5215MNR2G
QFN40
(Pb−Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2008
October, 2008 − Rev. 5
1
Publication Order Number:
NCP5215/D
NCP5215
TRESET1
CS1+
40
TRE1
5VCC
33
30
CS1−/Vo1
34
12
Ohm
Vo1
FB1
RAMP GENERATOR
DSCH1
INV1
VDRP1
COMP1
SS1
VREF
EN1
ILIM1
FPWM
5VCC
VCC
FSET
AGND
VREF
Vin
VIN
PGOOD1
PGOOD2
CCM1
38
CS2+
COMP1
27
39
OVP1
CLK
9
CLK1
VIN
Over Current
Detector 1
INV2
VDRP2
COMP2
SS2
VREF
EN2
ILIM2
SWN1
VCCP1
5VCC
Vo1
BG1
PGND1
EN_DRV1
Vin
OC1
THERMAL
SHUTDOWN
TSD
FB1
EN1
2
5VCC
OC1
1
NCP5215
Digital Counter &
180o Phase Shift
OSC
DSCH1
and
PGOOD1
CONTROL LOGIC
FB2
0.8V
4
Vin
PROTECTION
3
EN2
OC2
26
DSCH2
5
PGOOD2
6
11
CLK2
VIN
FPWM
OVP2
EN_DRV2
TRE2
5VCC
18
21
RAMP GENERATOR
DSCH2
FB2
14
CCM2
GATE
&
2
20
DRIVER
LSEN2
2
COMP2
24
VREF
10
16
22
SWN2
12
8
19
23
13
15
PWM2
PWM LOGIC
CDIFF2
VREF
CS1−
VREF
25
12
Ohm
FB2
CS1+
TG1
VCC
CDIFF1
35
BST1
FPWM
Soft Start 1
7
32
28
VREF
36
31
29
SWN1
CS2−/Vo2
17
Vo2
1
LSEN1
1
CLK
TRESET2
DRIVER
PWM LOGIC
CDIFF1
VREF
GATE
&
FB1
37
PWM1
Vin
Soft Start 2
CDIFF2
Over Current
Detector 2
OC2
Figure 1. Internal Block Diagram and Typical Application
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2
Vin
BST2
CS2+
TG2
CS2−
SWN2
VCCP2
5VCC
BG2
PGND2
Vo2
NCP5215
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Description
1
FSET
Frequency SET Programmable pin of switching frequency for two channels.
2
VCC
VCC This pin powers the control section of IC.
3
AGND
Analog Ground Low noise ground for control section of IC.
4
VREF
Reference Voltage Output Internal 0.8 V reference output.
5
PGOOD1
Power GOOD 1 Power good indicator of the output voltage of Channel 1. (Open drained)
6
PGOOD2
Power GOOD 2 Power good indicator of the output voltage of Channel 2. (Open drained)
7
EN1
Enable 1 Enable logic input of Channel 1.
8
EN2
Enable 2 Enable logic input of Channel 2.
9
SS1
Soft−Start 1 Soft−starting programmable pin of Channel 1.
10
SS2
Soft Start 2 Soft−starting programmable pin of Channel 2.
11
TRESET2
12
COMP2
13
INV2
Inverting Input 2 Error amplifier’s inverting input pin of Channel 2.
14
FB2
Feedback 2 Output voltage feedback of Channel 2.
15
VDRP2
Voltage Droop 2 Channel 2 voltage droop output to the compensation. This pin is used to program the
adaptive−voltage−position (AVP) function for Channel 2.
16
ILMT2
Current Limit 2 Current limit programmable pin of Channel 2.
17
CS2− / Vo2
18
CS2+
Current Sense 2+ Channel 2 inductor current differential sense non−inverting input.
19
SWN2
Switch Node 2 Switch node between the top MOSFET and bottom MOSFET of Channel 2.
20
TG2
Top Gate 2 Gate driver output of the top N−Channel MOSFET for Channel 2.
21
BST2
BOOTSTRAP Connection 2 Channel 2 top gate driver input supply, a bootstrap capacitor connection
between SWN2 and this pin.
22
VCCP2
Transient Response Enhancement SET 2 Channel 2 Transient−Response−Enhancement (TRE)
programmable pin.
COMP2 Output of the error amplifier of Channel 2.
Current Sense 2− Channel 2 inductor current differential sense inverting input.
VCC Power 2 This pin powers the bottom gate driver of Channel 2.
23
BG2
24
PGND2
Power Ground 2 Ground reference and high−current return path for the bottom gate driver of Channel 2.
25
FPWM#
Forced PWM Forced PWM enable logic input. Low to enable forced PWM mode and disable power−saving
mode for both channels.
26
Vin
27
PGND1
Bottom Gate 2 Gate driver output of the bottom N−Channel MOSFET for Channel 2.
Vin Input voltage monitor input.
Power Ground 1 Ground reference and high−current return path for the bottom gate driver of Channel 1.
28
BG1
29
VCCP1
Bottom Gate 1 Gate driver output of the bottom N−Channel MOSFET for Channel 1.
30
BST1
BOOTSTRAP Connection 1 Channel 1 top gate driver input supply, a bootstrap capacitor connection
between SWN1 and this pin.
31
TG1
Top Gate 1 Gate driver output of the top N−Channel MOSFET for Channel 1.
32
SWN1
Switch Node 1 Switch node between the top MOSFET and bottom MOSFET of Channel 1.
33
CS1+
Current Sense 1+ Channel 1 inductor current differential sense non−inverting input.
34
CS1− / Vo1
35
ILMT1
Current Limit 1 Current limit programmable pin of Channel 1.
36
VDRP1
Voltage Droop 1 Channel 1 voltage droop output to the compensation. This pin is used to program the
Adaptive−Voltage−Position (AVP) function for Channel 1.
37
FB1
Feedback 1 Output voltage feedback of Channel 1.
38
INV1
Inverting Input 1 Error amplifier’s inverting input pin of Channel 1.
39
COMP1
40
TRESET1
VCC Power 1 This pin powers the bottom gate driver of Channel 1.
Current Sense 1− Channel 1 inductor current differential sense inverting input.
COMP1 Output of the error amplifier of Channel 1.
Transient Response Enhancement SET 1 Channel 1 Transient−Response−Enhancement (TRE)
program pin.
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3
NCP5215
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC, VCCP1,
VCCP2
−0.3, 6.0
V
VBST1 − VSWN1,
VBST2 − VSWN2,
VTG1 − VSWN1,
VTG2 − VSWN2,
−0.3, 6.0
V
Vin
−0.3, 27
V
VSWN1, VSWN2
−4.0 (<100 ns),
−0.3 (dc), 32
V
PGND1, PGND2 to AGND
VGND
−0.3, 0.3
V
Thermal Characteristics
Thermal Resistance, Junction−to−Air (Pad soldered to PCB)
RqJA
36
°C/W
Operating Junction Temperature Range
TJ
−40 to +150
°C
Operating Ambient Temperature Range
TA
−40 to +85
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Moisture Sensitivity Level
MSL
1
−
Power Supply Voltages to AGND
High−Side Gate Driver Supplies: BST1 to SWN1, BST2 to SWN2
High−Side FET Gate Driver Voltages: TG1 to SWN1, TG2 to SWN2
Input Voltage Sense Inputs to AGND
Switch Nodes
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device contains ESD protection and exceeds the following tests:
Human Body Model (HBM) ≤2.0kV per JEDEC standard: JESD22−A114.
Machine Model (MM) =≤200V per JEDEC standard: JESD22−A115, except Pin 17 and Pin 34, which are ≤150V.
2. Latchup Current Maximum Rating: ≤150mA per JEDEC standard: JESD78.
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NCP5215
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VIN = 12 V, FSET = 5.0 V, Fsw = 300 kHz, TA = −40°C to 85°C, unless otherwise
noted.)
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Voltage
Vin
−
4.5
−
24
V
VCC Operating Voltage
VCC
−
4.5
5.0
5.5
V
VCCP1 Operating Voltage
VCCP1
−
4.5
5.0
5.5
V
VCCP2 Operating Voltage
VCCP2
−
4.5
5.0
5.5
V
VCC Quiescent Supply Current in Normal
Operation
IVCC_N
VEN1 = VEN2 = 5.0 V,
VFPWM# = 0 V TG1, BG1, TG2,
and BG2 are open
−
3.0
6.0
mA
VCC Quiescent Supply Current in
Power−Saving Operation
IVCC_PS
VEN1 = VEN2 = 5.0 V,
VFPWM# = 5.0 V TG1, BG1,
TG2, and BG2 are open
−
3.0
6.0
mA
VCC Shutdown Current
IVCC_SD
VEN1 = VEN2 = 0 V
−
−
10
mA
Characteristic
SUPPLY VOLTAGE
SUPPLY CURRENT
VCCP Quiescent Supply Current in Normal
Operation
IVCCP1_N,
IVCCP2_N
VEN1 = VEN2 = 5.0 V,
VFPWM# = 0 V TG1, BG1, TG2,
and BG2 are open
−
1.2
2.0
mA
VCCP Shutdown Current
IVCCP1_SD,
IVCCP2_SD
VEN1 = VEN2 = 0 V
−
−
10
mA
VEN1 = VEN2 = 5.0 V,
VFPWM# = 0 V TG1, BG1, TG2,
and BG2 are open
−
1.0
2.0
mA
IBST1_SD,
IBST2_SD
VEN1 = VEN2 = 0 V
−
−
5.0
mA
VCC Start Threshold
VCCUV+
VCC and VCCP are connected to
the same voltage source
4.05
4.25
4.48
V
VCC UVLO Hysteresis
VCChys
−
200
275
400
mV
Power Good Higher Threshold
VPGH
With Respect to Error Comparator
Threshold of 0.8 V
−
112
−
%
Power Good Lower Threshold
VPGL
With Respect to Error Comparator
Threshold of 0.8 V
−
88
−
%
FBOVPth
With respect to Error Comparator
Threshold of 0.8 V
113
117
121
%
Overvoltage Fault Propagation Delay
−
FB forced 2% above trip threshold
−
1.5
−
ms
Output Undervoltage Trip Threshold
FBUVPth
With respect to Error Comparator
Threshold of 0.8 V
63
68
73
%
Output Undervoltage Protection Blanking
Time
UVPTblk
(Note 3)
−
16/fsw
−
s
0.796
0.792
0.8
−
0.804
0.808
V
Ivref = 0 to 100 mA
−
−
4.0
mV
Vref rises 10%
20
−
−
mA
VILIM = 0.4 V
72
80
88
mV
(Note 3)
−
−
0.8
V
BST Quiescent Supply Current in Normal
Operation
IBST1_N, IBST2_N
BST Shutdown Current
VOLTAGE−MONITOR
Output Overvoltage Trip Threshold
VREF OUTPUT
Reference Voltage
Vref
Reference Load Regulation
TA = 25°C
TA = −40 to 85°C
DVref
Sinking Current
Isink_VREF
CURRENT LIMIT
Current Limit Threshold
V((CS+)−(CS−))
ILIM Setting Range
RangeILIM
3. Guaranteed by design, not tested in production.
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NCP5215
ELECTRICAL CHARACTERISTICS (continued) (VCC = 5.0 V, VIN = 12 V, FSET = 5.0 V, Fsw = 300 kHz, TA = −40°C to 85°C, unless
otherwise noted)
Symbol
Characteristic
Test Conditions
Min
Typ
Max
Unit
THERMAL SHUTDOWN
Thermal Shutdown
Thermal Shutdown Hysteresis
Tsd
(Note 4)
−
150
−
°C
Tsdhys
(Note 4)
−
30
−
°C
FSET pin open loop (TA = 25°C)
160
200
240
kHz
Pull high FSET pin (TA = 25°C)
(TA = −40°C to 85°C)
262.5
255
300
−
337.5
345
kHz
Pull low FSET pin (TA = 25°C)
340
400
460
kHz
3.0
4.0
5.0
mA
−
0.9
−
V
OSCILLATOR
Operation Frequency
Fsw
SOFT−START
ISS
Soft−Start Source Current
Soft−Start Complete Threshold
−
VSSTh
(Note 4)
SWITCHING REGULATORS
Main Ramp Amplitude Voltage
Vramp
VIN = 5.0 V (Note 4)
−
1.25
−
V
Maximum Duty Cycle
Dmax
VIN = 5.0 V
−
92
−
%
VIN = 12 V
−
48
−
%
VIN = 24 V
−
27
−
%
GATE DRIVERS
TG Gate Pull−HIGH Resistance
RH_TG1, RH_TG2
VBST−VSWN = 5.0 V,
VTG−VSWN = 4.0 V
−
1.5
4.0
W
TG Gate Pull−LOW Resistance
RL_TG1, RL_TG2
VBST−VSWN = 5.0 V,
VTG−VSWN = 1.0 V
−
1.5
4.0
W
BG Gate Pull−HIGH Resistance
RH_BG1, RH_BG2
VCCP = 5.0 V, VBG = 4.0 V
−
1.5
4.0
W
BG Gate Pull−LOW Resistance
RL_BG1, RL_BG2
VCCP = 5.0 V, VBG = 1.0 V
−
0.5
1.5
W
TLH
BG Falling to TG Rising
−
42
−
ns
THL
TG Falling to BG Rising
−
34
−
−200
−
200
nA
−
−
3.0
V
0.6
−
1.0
V
(CS+)−(CS−) = 0 V, no connection
from VDRP pin to VREF
−1.0
−
1.0
mA
(CS+)−(CS−) = 20 mV
2.35
2.6
2.85
V/V
From VDRP to VREF
2.4
2.65
2.9
kW
Dead Time
DIFFERENTIAL CURRENT ERROR AMPLIFIER
CS−IIB
Input Bias Current
CS+ to CS− Input Signal Range
VCS_MAX
Output Voltage Swing
VOS_DRP
Offset Current at VDRP
Ioffset_DRP
[(CS+)−(CS−)] to VDRP Gain
Gain_CS
((V_VDRP−Vref)/
((CS+)−(CS−)))
Internal Droop Resistance
RDRP
−
Refer to AGND
(Note 4)
4. Guaranteed by design, not tested in production.
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NCP5215
ELECTRICAL CHARACTERISTICS (continued) (VCC = 5.0 V, VIN = 12 V, FSET = 5.0 V, Fsw = 300 kHz, TA = −40°C to 85°C, unless
otherwise noted)
Symbol
Test Conditions
Min
Typ
Max
Unit
GAIN_VEA
(Note 5)
−
80
−
dB
Unity Gain Bandwidth
Ft_VEA
(Note 5)
−
13
−
MHz
Slew Rate
SR_VEA
(Note 5)
(COMP PIN TO GND = 100 pF)
−
1.0
−
V/ms
VINV = 0.8 V
−
−
0.5
mA
1.0
−
3.0
V
Characteristic
VOLTAGE ERROR AMPLIFIER
DC Gain
Inverting Input Current
IINV1, IINV2
Output Voltage Swing
VOS_EA
Source Current
Sink Current
−
Isource_EA
COMP = 3.0 V
2.0
4.0
−
mA
Isink_EA
COMP = 1.0 V
1.5
2.0
−
mA
CONTROL SECTION
VEN1, VEN2 Threshold High
VEN1_H, VEN2_H
−
1.4
−
−
V
VEN1, VEN2 Threshold Low
VEN1_L, VEN2_L
−
−
−
0.5
V
VEN1, VEN2 Source Current
IEN1_SOURCE,
IEN2_SOURCE
−
−
−
0.5
mA
VEN1, VEN2 Sink Current
IEN1_SINK,
IEN2_SINK
−
−
−
0.5
mA
VFPWM# Threshold High
VFPWM_H
−
1.4
−
−
V
VFPWM# Threshold Low
VFPWM_L
−
−
−
0.5
V
VFPWM# Source Current
IFPWM_SOURCE
−
−
−
0.5
mA
VFPWM# Sink Current
IFPWM_SINK
−
−
−
0.5
mA
PGOOD Pin ON Resistance
PGOOD_R
−
25
−
W
PGOOD Pin OFF Current
PGOOD_LK
−
−
−
1.0
mA
Output Discharge On−Resistance
Rdischarge
−
−
12
−
W
System Restart Threshold of the Output
Voltage
Vth_SRST
−
0.2
0.3
0.4
V
ITRE
−
3.0
4.0
5.0
mA
I_PGOOD = 5.0 mA
OUTPUT DISCHARGE MODE
TRE OFFSET
TRESET Offset Current
5. Guaranteed by design, not tested in production.
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NCP5215
TYPICAL OPERATING CHARACTERISTICS
FSW, SWITCHING FREQUENCY (kHz)
306
0.802
0.801
0.8
0.799
0.798
10
35
60
85
302
300
298
296
294
−40
35
60
Figure 2. Reference Voltage vs. Ambient
Temperature
Figure 3. Switching Frequency vs. Ambient
Temperature
4.2
2.8
4.1
4
3.9
3.8
−15
10
35
60
85
85
2.7
2.6
2.5
2.4
2.3
−40
−15
10
35
60
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 4. Soft−Start Current vs. Ambient
Temperature
Figure 5. VDRP Gain vs. Ambient Temperature
85
4.3
2.8
4.2
2.7
4.1
2.6
2.5
4
3.9
2.4
2.3
−40
10
TA, AMBIENT TEMPERATURE (°C)
2.9
2.9
−15
TA, AMBIENT TEMPERATURE (°C)
4.3
3.7
−40
RDRP, INTERNAL DROOP
RESISTANCE (kW)
−15
Gain_CS, VCRP GAIN (V/V)
ISS, SOFT−START CURRENT (mA)
0.797
−40
304
ITRE, TRESET OFFSET CURRENT
(mA)
VREF, REFERENCE VOLTAGE (V)
0.803
3.8
−15
10
35
60
TA, AMBIENT TEMPERATURE (°C)
85
3.7
−40
Figure 6. Internal Droop Resistance vs.
Ambient Temperature
−15
10
35
60
TA, AMBIENT TEMPERATURE (°C)
Figure 7. TRESET Offset Current vs. Ambient
Temperature
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85
NCP5215
1.54
1.1
1.52
1.09
VO, OUTPUT VOLTAGE (V)
VO, OUTPUT VOLTAGE (V)
TYPICAL OPERATING CHARACTERISTICS
1.5
1.48
1.46
1.44
VIN = 20 V, PS
VIN = 12 V, PS
VIN = 9 V, PS
VIN = 20 V, FPWM
VIN = 12 V, FPWM
VIN = 9 V, FPWM
1.42
1.4
1.38
0
1
2
3
4
5
6
7
VIN = 20 V, PS
VIN = 12 V, PS
VIN = 9 V, PS
VIN = 20 V, FPWM
VIN = 12 V, FPWM
VIN = 9 V, FPWM
1.04
1.03
0
1
2
3
4
5
6
7
Figure 8. Output Voltage vs. Output Current
(VO = 1.5 V, without AVP Function)
Figure 9. Output Voltage vs. Output Current (Vo
= 1.05 V, Without AVP Function)
8
1.1
VIN = 20 V, PS
VIN = 12 V, PS
VIN = 9 V, PS
VIN = 20 V, FPWM
VIN = 12 V, FPWM
VIN = 9 V, FPWM
1.5
1.48
1.46
1.44
1.42
1.4
1
2
3
4
5
6
7
VIN = 20 V, PS
VIN = 12 V, PS
VIN = 9 V, PS
VIN = 20 V, FPWM
VIN = 12 V, FPWM
VIN = 9 V, FPWM
1.09
VO, OUTPUT VOLTAGE (V)
VO, OUTPUT VOLTAGE (V)
1.05
IO, OUTPUT CURRENT (A)
1.08
1.07
1.06
1.05
1.04
1.03
1.02
8
0
1
2
3
4
5
6
7
IO, OUTPUT CURRENT (A)
IO, OUTPUT CURRENT (A)
Figure 10. Output Voltage vs. Output Current
(VO = 1.5 V, with AVP Function)
Figure 11. Output Voltage vs. Output Current
(VO = 1.05 V, with AVP Function)
8
400
FSW, SWITCHING FREQUENCY (kHz)
400
FSW, SWITCHING FREQUENCY (kHz)
1.06
IO, OUTPUT CURRENT (A)
1.52
350
300
250
200
150
VIN = 20 V, PS
VIN = 12 V, PS
VIN = 9 V, PS
VIN = 20 V, FPWM
VIN = 12 V, FPWM
VIN = 9 V, FPWM
100
50
0
0
1.07
1.02
8
1.54
1.38
0
1.08
1
2
3
4
5
6
7
8
350
300
250
200
150
VIN = 20 V, PS
VIN = 12 V, PS
VIN = 9 V, PS
VIN = 20 V, FPWM
VIN = 12 V, FPWM
VIN = 9 V, FPWM
100
50
0
0
1
2
3
4
5
6
7
IO, OUTPUT CURRENT (A)
IO, OUTPUT CURRENT (A)
Figure 12. Switching Frequency vs. Output
Current (VO = 1.5 V)
Figure 13. Switching Frequency vs. Output
Current (VO = 1.05 V)
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8
NCP5215
TYPICAL OPERATING CHARACTERISTICS
100
100
VIN = 20 V, PS
9 V, PS
80
EFFICIENCY (%)
EFFICIENCY (%)
80
12 V, PS
20 V, FPWM
60
12 V, FPWM
40
9 V, FPWM
VIN = 20 V, PS
9 V, PS
20 V, FPWM
60
12 V, FPWM
40
9 V, FPWM
20
20
0
0.01
12 V, PS
0.1
1
IO, OUTPUT CURRENT (A)
0
0.01
10
Figure 14. Efficiency vs. Output Current
(VO = 1.5 V)
0.1
1
IO, OUTPUT CURRENT (A)
Figure 15. Efficiency vs. Output Current
(VO = 1.05 V)
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10
NCP5215
TYPICAL OPERATING CHARACTERISTICS
Top: Vin, Input Voltage Ripple, (100mV/div)
Middle: SWN1, CH1 Switching Node Voltage, (10V/div)
Bottom: SWN2, CH2 Switching Node Voltage, (10V/div)
Time: 2ms/div
Top: SWN1, CH1 Switching Node Voltage, (10V/div)
Middle 1: Vo1, CH1 Output Voltage Ripple, (50mV/div)
Middle 2: SWN2, CH2 Switching Node Voltage, (10V/div)
Bottom: Vo2, CH2 Output Voltage Ripple, (50mV/div)
Time: 2ms/div
Figure 16. Input Voltage Ripple with
Interleaved Operation (VO1 = 1.5 V, IO1 = 4 A,
VO2 = 1.05 V, IO2 = 6 A)
Figure 17. Output Voltage Ripple with
Interleaved Operation (VO1 = 1.5 V, IO1 = 4 A,
VO2 = 1.05 V, IO2 = 6 A)
Top: EN1, CH1 Enable Signal, (5V/div)
Middle 1: PGOOD1, CH1 Power Good Signal, (5V/div)
Middle 2: SWN1, CH1 Switching Node Voltage, (10V/div)
Bottom: VO1, CH1 Output Voltage, (1V/div)
Time: 200ms/div
Top: EN2, CH2 Enable Signal, (5V/div)
Middle 1: PGOOD2, CH2 Power Good Signal, (5V/div)
Middle 2: SWN2, CH2 Switching Node Voltage, (10V/div)
Bottom: VO2, CH2 Output Voltage, (1V/div)
Time: 200ms/div
Top: EN1, CH1 Enable Signal, (5V/div)
Middle 1: PGOOD1, CH1 Power Good Signal, (5V/div)
Middle 2: SWN1, CH1 Switching Node Voltage, (10V/div)
Bottom: VO1, CH1 Output Voltage, (1V/div)
Time: 5ms/div
Top: EN2, CH2 Enable Signal, (5V/div)
Middle 1: PGOOD2, CH2 Power Good Signal, (5V/div)
Middle 2: SWN2, CH2 Switching Node Voltage, (10V/div)
Bottom: Vo2, CH2 Output Voltage, (1V/div)
Time: 5ms/div
Figure 18. Powerup Operation (VO1 = 1.5 V,
IO1 = 4 A)
Figure 19. Powerup Operation (VO2 = 1.05 V,
IO2 = 6 A)
Figure 20. Powerdown Operation (VO1 = 1.5 V,
IO1 = 0 A, FPWM)
Figure 21. Powerdown Operation
(VO2 = 1.05 V, IO2 = 0 A, FPWM)
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NCP5215
TYPICAL OPERATING CHARACTERISTICS
Top: Vo1, CH1 Output Voltage Ripple, (50mV/div)
Middle: Io1, CH1 Output Current, (5A/div)
Bottom: SWN1, CH1 Switching Node Voltage, (10V/div)
Time: 20ms/div
Top: Vo2, CH2 Output Voltage Ripple, (50mV/div)
Middle: Io2, CH2 Output Current, (5A/div)
Bottom: SWN2, CH2 Switching Node Voltage, (10V/div)
Time: 20ms/div
Figure 22. Load Transient Response with
FPWM Operation (VO1 = 1.5 V,
IO1 = 0 A−4 A−0 A)
Figure 23. Load Transient Response with
FPWM Operation (VO2 = 1.05 V, IO2 =
0 A−6 A−0 A)
Top: Vo1, CH1 Output Voltage Ripple, (50mV/div)
Middle: Io1, CH1 Output Current, (5A/div)
Bottom: SWN1, CH1 Switching Node Voltage, (10V/div)
Time: 50ms/div
Top: Vo2, CH2 Output Voltage Ripple, (50mV/div)
Middle: Io2, CH2 Output Current, (5A/div)
Bottom: SWN2, CH2 Switching Node Voltage, (10V/div)
Time: 50ms/div
Top: FPWM#, FPWM# Signal, (5V/div)
Middle 1: Vo1, CH1 Output Voltage Ripple, (50mV/div)
Middle 2: iL1, CH1 Inductor Current, (5A/div)
Bottom: SWN1, CH1 Switching Node Voltage, (10V/div)
Time: 50ms/div
Top: FPWM#, FPWM# Signal, (5V/div)
Middle 1: Vo2, CH2 Output Voltage Ripple, (50mV/div)
Middle 2: iL2, CH2 Inductor Current, (5A/div)
Bottom: SWN2, CH2 Switching Node Voltage, (10V/div)
Time: 50ms/div
Figure 24. Load Transient Response with
Skip−Mode Operation (VO1 = 1.5 V, IO1 =
0.1 A−4 A−0.1 A)
Figure 25. Load Transient Response with
Skip−Mode Operation (VO2 = 1.05 V, IO2 =
0.1 A−6 A−0.1 A)
Figure 26. On−Line Mode−Changing Operation
(VO1 = 1.5 V, IO1 = 0.2 A, FPWM−Skip
Mode−FPWM)
Figure 27. On−Line Mode−Changing Operation
(VO2 = 1.05 V, IO2 = 0.2 A, FPWM−Skip
Mode−FPWM)
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NCP5215
OPERATION DESCRIPTION
General
1.2MHz
The
NCP5215,
a
high−efficiency
and
fast−transient−response dual−channel buck controller,
provides a multifunctional power solution for notebook
power system. 180° interleaved operation function
between the two channels has capabilities of reducing the
common input capacitor requirement and improving noise
immunity. Adaptive−Voltage−Positioning (AVP) control
reduces the requirement of output filter capacitors.
Programmable power−saving operation ensures high
efficiency over entire load range. Input feedforward
voltage−mode control is employed to deal with wide input
voltage range. Transient−Response−Enhancement (TRE)
control for the both channels enables fast transient
response.
CLK1
OSC
(4*FSW)
GND
Fsw (kHz)
200
300
400
Interleaved in CCM
300kHz
PWM2
1.2MHz
Figure 28. Internal Clocks in the NCP5215 as FSW =
300 kHz
Light−Load Pulse−Skipping Operation (Skip Mode)
If the skip mode is enabled by pulling high FPWM# pin,
the NCP5215 works in pulse−skipping enabled operation
(PS).
In medium and high load range, the converter still runs
in CCM, and the switching frequency is fixed as the
selected frequency. If both channels run in CCM, they
operate interleaved.
In light load range, the converter will enter skip mode if
negative inductor current appears continuously. In the skip
mode, the bottom MOSFET will be turned off when the
inductor current is going negative. The top MOSFET’s
on−time is fixed to around 1.5 times as the on−time in
CCM. The NCP5215 continuously monitors the voltage at
FB pin and comparing to the voltage at VDRP Pin. When
the FB voltage drops below the VDRP voltage, a fixed
on−time will be initiated at the time of the next coming
high−frequency clock edge, which can be either rising edge
or falling edge. The minimum off−time is half
high−frequency cycle.
When the load increases and the inductor current
becomes continuous, the controller will automatically
return to fixed−frequency operation and be synchronized to
the normal operation clock.
Table 1. SWITCHING FREQUENCY SELECTION
VCC
Digital Counter & 180°
Phase Shift
CLK2
The NCP5215 operates at a pin−selectable normal
operation switching frequency, allowing 200 kHz,
300 kHz, or 400 kHz. As shown in Table 1, the connection
of the pin FSET determines normal operation frequency in
continuous−conduction−mode (CCM).
Float
1.2MHz
300kHz
High Sampling
Rate
PWM Operation
FSET Pin
PWM1
Fast
Response
To speed up transient response and increase sampling
rate, an internal high−frequency clock is employed, which
frequency is four times of the selected normal operating
frequency. As an instance, if the FSET pin is connected to
VCC, the normal switching frequency is set to 300 kHz. The
internal high−frequency clock is 1.2 MHz. Figure 28
shows internal clocks of the NCP5215 in this case. The
1.2MHz high−frequency clock with 50% duty−ratio
introduced to the two PWM channels. A digital circuitry
generates two interleaved 300 kHz clocks using the
1.2 MHz clock and output them to the two PWM channels
as normal operation clocks in CCM, respectively.
Forced−PWM Operation (FPWM Mode)
If the FPWM# pin is pulled low, the NCP5215 works
under forced−PWM operation and thus always in CCM.
The two channels always run in selected fixed frequency
and 180° interleaved operation. In this mode, the low−side
gate−drive signal is forced to be the complement of the
high−side gate−drive signal. This mode allows reverse
inductor current, in such a way that it provides more
accurate voltage regulation and fast transient response.
During soft−start operation, the NCP5215 automatically
runs in FPWM mode regardless of the FPWM# pin’s setting
to guarantee smooth powerup.
Transient Response Enhancement (TRE)
In the skip mode, the operation of the NCP5215 is similar
to constant on−time scheme. The response time of the
controller is between half to one cycle of the
high−frequency clock. However, for a conventional
trailing−edge PWM controller in CCM, the fastest
response time is one switching cycle in the worst case. To
further improve transient response in CCM, a transient
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NCP5215
response enhancement circuitry is introduced to the
NCP5215.
In CCM operation, the controller continuously monitors
the output voltage (COMP) of the error amplifier to detect
load transient events. As shown in Figure 1, there is a
threshold voltage in each channel made in a way that a
filtered COMP signal pluses an adjustable offset voltage,
which is set by an external resistor. Once large load
transient occurs, the COMP signal is possible to exceed the
threshold and then TRE signal will be high in a short period,
which is typically around one normal switching cycle. In
this short period, the controller will be running at high
frequency and therefore has faster response. After that the
controller comes back to normal switching frequency
operation. Figure 29 shows TRE effect on a load transient
response.
where ITRE is a sourcing current out the TRESET pin. A
recommended value for Vth_TRE is around 1.5 times of
peak−to−peak value of the COMP signal in CCM
operation. The higher Vth_TRE, the lower sensitivity to load
transient. The TRE function can be disabled by pulling
high the TRESET pin to VCC or just leaving it float.
Adaptive Voltage Positioning (AVP)
For applications with fast transient currents, adaptive
voltage positioning can reduce peak−to−peak output
voltage deviations due to load transients and allow use of
a smaller output filter. Adaptive voltage positioning sets
output voltage higher than nominal at light loads, and
output voltage is allowed limited sag when the load current
is applied. Upon removal of the load, output voltage returns
no higher than the original level, allowing one output
transient peak to be canceled over a load stepup and release
cycle.
+5% x VO
VO with AVP
VO without AVP
Figure 30. Adaptive Voltage Positioning
Figure 30 shows how AVP works. The waveform labeled
“Vo without AVP” shows output voltage waveform in a
converter without AVP. On the left, the output voltage sags
when the output current is stepped up and later overshoots
when current is stepped back down. With AVP, the
peak−to−peak excursions are cut around in half. The
controller can be configured to adjust the output voltage
based on the output current of the converter as shown in
Figure 31. In order to realize the AVP function, a resistor
is connected between VREF and VDRP. During no−load
conditions, the VDRP Pin voltage stays at the same voltage
level as the VREF. As the output current increases, the
VDRP Pin voltage decreases. This causes VOUT to droop
according to a loadline set by the resistor.
In the NCP5215, the output current of each channel is
sensed differentially. A high gain and low offset−voltage
differential amplifier in each channel allows
low−resistance current−sensing resistor or low−DCR
inductor to be used to minimize power dissipation. For
lossless inductor current sensing as shown in Figure 31, the
sensing RC network should satisfy
Top: Vo (50mV/div), Middle: Transient signal (20V/div),
Bottom: SWN (10V/div), Time: (10us/div)
(a) TRE disabled
Top: Vo (50mV/div), Middle: Transient signal (20V/div),
Bottom: SWN (10V/div), Time: (10us/div)
(b) TRE enabled
Figure 29. Transient Response Comparison on TRE
The internal offset voltage of the TRE threshold is set by
an external resistor RTRE connected from the TRESET Pin
to AGND.
Vth_TRE +
I TRE @ R TRE
4
RCS
C CS +
L
DCR
(eq. 2)
where DCR is a DC resistance of a inductor, and normally
Ccs is selected to be around 0.1 mF. In high accuracy
(eq. 1)
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NCP5215
If an additional current sensing resistor (RCS) is employed
to improve accuracy, as shown in Figure 32, the load line
resistance can be calculated by
applications, to compensate measurement error caused by
temperature, an additional resistance network including a
negative−temperature−coefficient (NTC) thermistor can
be connected with CCS in parallel.
RLL + R CS Gain_CS @
RDRP_ext
VO0
(eq. 6)
@
R DRP_int ) R DRP_ext V REF
The AVP function can be easily disabled by shorting
VDRP pin and VREF pin together.
Control Logic
The internal control logic is powered by VCC. Figure 33
shows a power−up and powerdown timing diagram for
each channel. Figure 34 shows a state diagram for each
channel.
The NCP5215 continuously monitors VCC and VIN level
with an undervoltage lockout (UVLO) function. If both
VCC and VIN are in operation range, and output voltage is
below 0.3 V, the converter has a soft−start after ENBL
signal goes high. The soft−start time is programmed by an
external capacitor CSS connected from the SS Pin to
AGND, which can be calculated by
Figure 31. Programmable AVP with Lossless Inductor
Current Sensing
tSS +
VO + V O0 * I O @ R LL
The NCP5215 protects power system if overcurrent
occurs. The current through each channel is continuously
monitored with the differential current sense. Current limit
threshold is related to an external voltage at the ILIM pin,
which is normally produced by an external resistor divider
(Ril1 and Ril2) connected from the VREF pin to AGND. The
current−limit threshold for peak current is set by
(eq. 3)
where Io is load current, no−load output voltage VO0 is set
by the external resistor divider, that is
RFO
RFG
Ǔ
@ VREF
(eq. 4)
RFO is a resistor connected between the output and the FB
pin, and RFG is a resistor connected between the FB Pin to
AGND. The load−line impedance RLL by the AVP function
is given by
RLL + DCR Gain_CS @
R DRP_ext
RDRP_int ) RDRP_ext
(eq. 7)
I SS
Overcurrent Protection (OCP)
The output voltage with AVP is
ǒ
CSS
where ISS is a sourcing current output from the SS pin.
When the ENBL goes low, or the internal fault latch is set
by over current or output undervoltage, the device operates
in soft stop and output discharge mode. The output is
discharged to GND through an internal 12 W switch
connected from the CS−/Vo pin to the PGND Pin, until the
output voltage decreases to 0.3 V. Also if restart the system
when the output voltage is still above 0.3 V, the device will
discharge the output voltage to 0.3 V first and then start
soft−start.
Figure 32. Figure 32. Programmable AVP with
Resistive Current Sensing
VO0 + 1 )
0.8
ILIM(Peak) + 0.2 @
ǒRil1 ) Ril2Ǔ @ DCR
(eq. 8)
or
(eq. 5)
@
R il2 @ V REF
ILIM(Peak) + 0.2 @
VO0
VREF
Ril2 @ VREF
ǒRil1 ) Ril2Ǔ @ RCS
(eq. 9)
If inductor current exceeds the current threshold
continuously, the top gate drive will be turned off
cycle−by−cycle. In the meanwhile, an internal fault timer
will be triggered to count normal operation clock. After 16
continuous clock pulses, if the fault still exists the part
latches off, both the top gate drive and the bottom gate drive
where DCR is DC resistance of the inductor, Gain_CS is a
gain from [(CS+)−(CS−)] to (VDRP−VREF), RDRP_int is a
internal resistance connected between the output reference
and the VDRP Pin, RDRP_ext is a external resistance
connected between the output reference and the VDRP pin.
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15
NCP5215
are turned off and their outputs are float. The fault remains
set until the system has shutdown and re−applied power or
the enable input signal to the regulator controller has
toggled states.
voltage level. If the output voltage is below this threshold,
a UV fault is set. If an OV protection is set before, the
bottom gate drive is forced high. If no OV protection set,
an internal fault timer will be triggered to count normal
operation clock. After 16 continuous clock pulses, if the
fault still exists the part latches off, both the top gate drive
and the bottom gate drive are turned off and their outputs
are float. The fault remains set until the system has
shutdown and re−applied power or the enable input signal
to the regulator controller has toggled states.
Overvoltage Protection (OVP)
An OVP circuit monitors the output voltages to prevent
from over voltage. OVP limit is typically 117% of the
nominal output voltage level. If the output voltage is above
this threshold, an OV fault is set, the top gate drive is turned
OFF, and then the bottom gate drive is latched ON to
discharge the output. The fault remains set until the system
has shutdown and re−applied power or the enable input
signal to the regulator controller has toggled states.
Thermal Protection
The NCP5215 has a thermal shutdown protection to
protect the device from overheating when the die
temperature exceeds 150°C. Once the thermal protection is
triggered, the fault state can be ended by re−applying VCC,
VIN, or ENBL when the temperature drops down below
120°C.
Undervoltage Protection (UVP)
A UVP circuit monitors the output voltages to detect
undervoltage. UVP limit is 68% of the nominal output
VCCA
tSFT_START
VIN
ENBL
Vo
PGOOD
32 Cycles
VCCA goes
above 4.4V to
enable the IC
PGOOD Goes High
ENBL goes high. Vo is enabled but not
actived until VIN goes above 3.5V.
Soft−Start
Completed
PGOOD Goes Low
Figure 33. Powerup and Powerdown Timing Diagram per Channel
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NCP5215
Power Up
Re−apply
VCC or VIN or ENBL
VCC > 4.25V ?
& VIN > 4.0V ?
& ENBL= HIGH ?
yes
Vo Discharge
Mode
no
& no OV
TG Latch Off
BG Latch On
Vo < 0.3V
OV
yes
VCC < 4.0V
or VIN < 3.5V
or ENBL = LOW
OVP
OV
Soft Start and
Normal Operation
OC
OCP
UV
TG & BG
Latch Off
UVP
Vo Discharge
Mode
Figure 34. State Diagram per Channel
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NCP5215
0.1uF
10uF
L2
1.5uH
M4
5VCC
1uF
Db2
1uF
BAT54WT1
BST2
BG2
VCCP2
PGND2
VIN
FPWM#
PGND1
BG1
BST1
VCCP1
TG2 20
SWN2 19
PGOOD1
PGOOD2
EN1
EN2
SS1
3
4
5
6
7
8
9
PGND
Figure 35. Typical Application Schematic Diagram
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R24
36k
SS2
4.7nF
68pF
1uF
Rt2
1uF
Css2
200k
Cref
10
4.7nF
Ccf
Css1
20
TRESET2 11
R23
VREF
2
13k
C23
AGND
1
3k
C22 R22
VCC
Rcf
100k
Rdp2
820pF 910
FSET
COMP2 12
EN2
Rt1
390k
68pF
5VCC
Ril21
36k
Cdp2
R21
INV2 13
39 COMP1
11k
R14
38 INV1
Ril22
47pF
FB2 14
40 TRESET1
C11
1nF 750
10k
VDRP2 15
37 FB1
R11
220pF
NCP5215MNR2G
36 VDRP1
47pF
ILIM2 16
C21
35 ILIM1
EN1
82k
Cdp1
VREF
CS2−/Vo2 17
PGOOD2
Ril12
100k
Rdp1
CS2+ 18
34 CS1−/Vo1
PGOOD1
Ril11
Cb2
0.1uF
33 CS1+
C13 R13
220uF*2 10uF
PGND
32 SWN1
VREF
Co21
5VCC
30 29 28 27 26 25 24 23 22 21
31 TG1
75k
Co2
220pF 200k
Cb1
0.1uF
R12
Cs2
0.1uF
Cpf2
FPWM#
Cpf1
Db1
BAT54WT1
C12
Vo2
1.05V/6A
PGND
PGND
2k
Rs2
10uF
M2
4.3k
M3
Cin2
Rif
Cs1
10uF 220uF
Cin1
Cif
Co1
Co11
NTMS4705N
Rs1
1.5V / 5A
3.6k
Vo1
NTMS4705N NTMS4705N
M1
L1
2.2uH
15nF 20
NTMS4705N
Vin
NCP5215
Table 2. BILL OF MATERIALS FOR THE TYPICAL APPLICATION
Item
PCS
Part
Reference
1
1
IC1
2
4
M1, M2,
M3, M4
3
2
Db1, Db2
4
2
Cdp1,
Cdp2
MLCC Cap 50V, $5%, Char:
COG
47pF
C11, C22
MLCC Cap 50V, $5%, Char:
COG
68pF
MLCC Cap 50V, $5%, Char:
COG
220pF
MLCC Cap 50V, $5%, Char:
COG
820pF
MLCC Cap 50V, $5%, Char:
COG
1000pF
CSS1,
CSS2
MLCC Cap 50V, $10%, Char:
X7R
4700pF
CIF
MLCC Cap 50V, $10%, Char:
X7R
15nF
Cb1, Cb2,
Cs1, Cs2
MLCC Cap 16V, $10%, Char:
X7R
0.1mF
Ccf, Cpf1,
Cpf2, Cref
MLCC Cap 25V, $10%, Char:
X5R
1mF
Co11,
Co21
MLCC Cap 10V, $20%, Char:
X7R
10mF
MLCC Cap 25V, $20%, Char:
X7R
10mF
SP−Cap/Polymer Aluminum Capacitors, 22 mF, 2 V, ESR =
12 mW
5
6
7
8
9
10
11
12
13
2
2
1
1
2
1
4
4
2
C12, C22
C23
C13
Description
Value
NCP5215
Package
QFN40
Part Number
Manufacturer
NCP5215MNR2G
ON Semiconductor
Power MOSFET 30 V, 12 A,
Single N−Channel SO−8
SO8
NTMS4705N
ON Semiconductor
Schottky Diode, 30V
SC70
BAT54WT1G
ON Semiconductor
0603
ECJ1VB1H470J
Panasonic
C1608C0G1H470J
TDK
ECJ1VB1H680J
Panasonic
C1608C0G1H680J
TDK
ECJ1VC1H221J
Panasonic
C1608C0G1H221J
TDK
ECJ1VC1H821J
Panasonic
C1608C0G1H821J
TDK
ECJ1VC1H102J
Panasonic
C1608C0G1H102J
TDK
ECJ1VB1H472K
Panasonic
C1608X7R1H472K
TDK
ECJ1VB1H153K
Panasonic
C1608X7R1H153K
TDK
ECJ1VB1C104K
Panasonic
C1608X7R1H104K
TDK
ECJ2FB1E105K
Panasonic
C3216X5R1H105K
TDK
ECJ3YB1C106M
Panasonic
C3216X7R1C106M
TDK
1812
C4532X7R1E106M
TDK
220mF
7343
EEFUD0D221XR
Panasonic
0603
0603
0603
0603
0603
0603
0603
0805
0805
14
2
CIN1,
CIN2
15
3
Co1, Co2
(x2)
16
2
Rcf, Rif
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
20W
0603
ERJ3EKF20R0V
Panasonic
17
1
R13
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
750W
0603
ERJ3EKF7500V
Panasonic
18
1
R23
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
910W
0603
ERJ3EKF9100V
Panasonic
19
1
Rdp1
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
2kW
0603
ERJ3EKF2001V
Panasonic
20
1
Rdp2
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
3kW
0603
ERJ3EKF3001V
Panasonic
21
1
RS1
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
3.6kW
0603
ERJ3EKF3601V
Panasonic
22
1
RS2
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
4.3kW
0603
ERJ3EKF4301V
Panasonic
23
1
R11
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
10kW
0603
ERJ3EKF1002V
Panasonic
http://onsemi.com
19
NCP5215
Item
PCS
Part
Reference
24
1
R14
25
1
26
Description
Value
Package
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
11kW
0603
ERJ3EKF1102V
Panasonic
R21
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
13kW
0603
ERJ3EKF1302V
Panasonic
2
R24, Ril22
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
36kW
0603
ERJ3EKF3602V
Panasonic
27
1
R12
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
75kW
0603
ERJ3EKF7502V
Panasonic
28
1
Ril12
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
82kW
0603
ERJ3EKF8202V
Panasonic
29
2
Ril11,
Ril21
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
100kW
0603
ERJ3EKF1003V
Panasonic
30
2
R22, Rt2
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
200kW
0603
ERJ3EKF2003V
Panasonic
31
1
Rt1
Thick Film Chip Resistors,
Power Rating 0.1W, Tol: $1%
390kW
0603
ERJ3EKF3903V
Panasonic
32
1
L1
Power Choke Coil, DCR =
7.0mW, IDC = 12A, ISAT = 27A
2.2mH
PCMC104T−2R2MN
Cyntec
33
1
L2
Power Choke Coil, DCR =
4.2mW, IDC = 16A, ISAT = 33A
1.5mH
PCMC104T−1R5MN
Cyntec
http://onsemi.com
20
Part Number
Manufacturer
NCP5215
PACKAGE DIMENSIONS
QFN40 6x6, 0.5P
MN SUFFIX
CASE 488AR−01
ISSUE A
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
D
PIN ONE
LOCATION
2X
0.15 C
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30mm FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A B
E
DIM
A
A1
A3
b
D
D2
E
E2
e
L
K
TOP VIEW
0.15 C
(A3)
0.10 C
A
40X
SIDE VIEW A1
0.08 C
C
D2
L
40X
11
SOLDERING FOOTPRINT*
SEATING
PLANE
6.30
K
20
4.20
40X
21
10
40X
0.65
EXPOSED PAD
1
E2
40X b
0.10 C A B
0.05 C
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
6.00 BSC
4.00
4.20
6.00 BSC
4.00
4.20
0.50 BSC
0.30
0.50
0.20
−−−
1
4.20 6.30
30
40
31
e
36X
BOTTOM VIEW
40X
0.30
36X
0.50 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Phone: 81−3−5773−3850
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21
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loca
Sales Representative
NCP5215/D