ONSEMI NCP5890MUTXG

NCP5890
Light Management IC
Dedicated for LCD
Backlighting and Multi-LED
Fun Light Applications
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The NCP5890 is part of the Light Management IC (LMIC) family. It
is a fully programmable subsystem that manages multiple illumination
functions integrated into the silicon.
Features
1
UQFN16
MU SUFFIX
CASE 523AF
MARKING DIAGRAM
5890
ALYWG
G
5890
A
L
Y
W
G
Typical Applications
• Portable Back Light & Keyboard
• Digital Cellular Phone Camera Photo Flash
4.7 mF/6.3 V
15
2
3
2
4
R3
4
SCL
Vos
SDA
VSB
PWM1
22 k
GND
5
220 k
AMBS
R1
R2
GND
2.2 mF
12 k
7
16 R5
470R
I2CADR
R4
C4
13
PWM2
PWM3
IREF
6
IPK
22 k
AGND
8
FB
PGND
14
GND
D1
D2
D3
12
D4
PERIPHERALS
1
GND
D8
Lx
Vbat
1.0 mF/50 V
11
D5
10
D6
9
I−Load Max = 25 mA
SDA
4.7 mF
U1
NCP5890
C2
DISPLAY
1
SCL
SFH5711
U3
Log
NSR0240P2
L1
C1
GND
(Note: Microdot may be in either location)
SCL
SDA
I2CADR
VSB
Lx
+Vbat
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Vos
Vbat
PGND
•
•
34 V Output Voltage Capability
Include Three Independent PWM to Control LED Segments
2.7 to 5.5 V Input Voltage Range
90% Peak Efficiency with 4.7 mH / 150 mW Inductor
Gradual Dimming Built−in
Integrated Ambient Light Sensing Adjusts Backlight Contrast
Built−in I2C Address Extension
Tight 1% I−LED Tolerance
True Cut Off Function Minimizes Load Leakage Current in
Shutdown
Ultra Thin 0.5 mm QFN16 Package
This is a PB−Free Device
1
PWM1
PWM2
PWM3
FB
AMBS
IPK
IREF
AGND
•
•
•
•
•
•
•
•
•
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCP5890MUTXG
UQFN16
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
GND
Figure 1. Typical Multiple White LED Application
© Semiconductor Components Industries, LLC, 2009
July, 2009 − Rev. 1
1
Publication Order Number:
NCP5890/D
NCP5890
+Vbat
L1
C1
4.7uF/6.3V
D8
4.7uH
GND
15
Lx
13
Vos
Thermal Shutdown
IPK
22k
6
PWM BOOST
CONTROLLER
I−PEAK
REF.
Gradual Dimming
Embedded
GND
I2CADR
2
I2C Port
DIGITAL CONTROL
3
GND
GND
U3
1
R2
IREF
12k
7
2
R3
AMBS
220k
22k
C4 2.2 mF
AGND
GND
5
160 Hz
I−LED
REFERENCE
D3
12
D4
PWM2
11
D5
PWM3
10
D6
FB
I−LED
9
Vdrop =
400 mV max
Vbat
4
R4
4
160 Hz
PWM2
PWM3
VSB
SFH5711
Log
160 Hz
1Hz
PWM1
14
PWM1
PERIPHERALS
SDA
1
PGND
GND
160 Hz
SCL
D1
D2
GND
I−Load
Max = 25 mA GND
DISPLAY
R1
16
OVP Detection
Under Voltage
Detection
1.0 mF/50 V
C2
NSR0240P2
AMBIENT
LIGHT
MONITORING
GND
GND
GND
8
Figure 2. Simplified Block Diagram
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2
NCP5890
SCL
SDA
I2C Port
BOOST CONVERTER
PWM0
PWM0 Drive
PWM1
PWM1 Drive
PWM2
PWM2 Drive
GRDIMT
I−LED min
I−LED max
DIGITAL COMPARATOR
Low I−LED
3 bits
5 bits
DIGITAL COMPARATOR
High I−LED
5 bits
PHGAIN
Log
4
DIGITAL
COUNTER
& PROCESSING
ANALOG
MONITORING
Low Pass
Filter
1 2
Photo Sense
I−LED
5 bits
1.3MHz oscillator
Clock Selection
1 kHz oscillator
PHTIM
Figure 3. Basic NCP5890 Structure
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3
1
GND
I−LED CONTROL
NCP5890
PIN DESCRIPTIONS
PIN
Name
Type
Description
1
SCL
INPUT,
DIGITAL
This pin carries the I2C clock to control the DC/DC converter and is used to set up the output current and the photo sensor. The SCL clock is associated with the SDA signal.
2
SDA
INPUT,
DIGITAL
This pin carries the data provided by the I2C protocol. The content of the SDA byte is used to program the mode of operation and to set up the output current.
3
I2CADR
INPUT,
DIGITAL
This pin is used to select the I2C address of the NCP5890:
I2CADR = Low ³ address = %0111 0010 = $72
I2CADR = High ³ address = %0111 0100 = $74
In order to avoid any risk during the operation, the digital levels are intended to be hardwired prior to
power up the system.
4
VSB
POWER,
OUTPUT
This pin provides a switched voltage, derived from the Vbat supply, to bias the external photo sense.
The current capability of this voltage is 2 mA.
The VSB switch output is open when the Shutdown mode has been engaged.
5
AMBS
INPUT,
ANALOG
This pin senses the voltage developed across the external Photo Bias resistor. Since this is a very
high impedance input, care must be observed to minimize the leakage current and the noise that
may influence the photo sense analog function. The bias parameters associated with the AMBS pin
are reloaded when the chip resumes from Shutdown to Normal operation.
6
IPK
INPUT,
ANALOG
This pin provides the inductor peak current during normal operation. In no case shall the voltage at
IPK pin be forced either higher or lower than the 1144 mV provided by the internal reference.
7
IREF
INPUT,
ANALOG
This pin provides the reference current, based on the internal band−gap voltage reference, to control the output current flowing in the LED. A 1% tolerance, or better, resistor shall be used to get the
highest accuracy of the LED biases. An external current source can be used to bias this pin to dim
the light coming out of the LED.
In no case shall the voltage at IREF pin be forced either higher or lower than the 1144 mV provided
by the internal reference.
8
AGND
POWER
This pin is the GROUND signal for the analog and digital blocks and must be connected to the system ground. A ground plane is strongly recommended.
9
FB
INPUT,
ANALOG
This pin is the current sense of the series arranged LED. The built−in current mirror will automatically adapt the voltage drop across this pin (typically 400 mV).
10
PWM3
INPUT,
ANALOG
This pin provides a PWM control of the LED connected between PWM3−FB. The PWM is programmed by the I2C port and preset to zero upon power ON.
11
PWM2
INPUT,
ANALOG
This pin provides a PWM control of the LED connected between PWM2. The PWM is programmed
by the I2C port and preset to zero upon power ON.
12
PWM1
INPUT,
ANALOG
This pin provides a PWM control of the LED connected between PWM1. The PWM is programmed
by the I2C port and preset to zero upon power ON.
13
Lx
POWER
The external inductor shall be connected between this pin (drain of the internal Power switch) and
Vbat. The voltage is internally clamped at 34 V under worst case conditions. The external Schottky
diode shall be connected as close as possible to this pin. See Note 1 for ESR recommendations.
14
PGND
POWER
This pin is the GROUND reference for the DC/DC converter and the output current control. The pin
must be connected to the system ground, a ground plane is strongly recommended.
15
VBAT
INPUT,
POWER
Input Battery voltage to supply the analog , the digital blocks and the main Power switch driver. The
pin must be decoupled to ground by a 10 mF ceramic capacitor.
16
Vos
INPUT,
POWER
This pin senses the output voltage supplied by the DC/DC converter. The Vos pin must be bypassed by 1.0 mF/50 V ceramic capacitor located as close as possible to the pin to properly bypass
the output voltage to ground. The circuit will not operate without such bypass capacitor connected to
the Vos pin.
The output voltage is internally clamped to 34 V maximum in the event of a no load situation.
NOTE: Due to the very fast dV/dt transient developed during the operation, using a low pass filter is
strongly recommended as depicted in the schematic diagram Figure 1.
1. Using low ESR ceramic capacitor and low DCR inductor is mandatory to optimize the DC/DC efficiency
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NCP5890
MAXIMUM RATINGS (Note 2)
Rating
Symbol
VBAT
Power Supply
VLX
Output Switching Voltage
SCL, SDA
Digital Input Voltage
Digital Input Current
Value
Unit
−0.3 < V < 7.0
V
34
V
−0.3 < V < VBAT
1
V
mA
ESD
Human Body Model: R = 1500 W, C = 100 pF (Note 3)
Machine Model
2
200
kV
V
PD
Rqjc
Rqja
UQFN16 package − Power Dissipation @ TA = +85°C (Note 4)
LLGA16 package − Thermal Resistance Junction to Case
LLGA16 package − Thermal Resistance Junction to Air
300
50
130
mW
°C/W
°C/W
TA
Operating Ambient Temperature Range
−40 to +85
°C
TJ
Operating Junction Temperature Range
−40 to +125
°C
+150
°C
−65 to + 150
°C
±100
mA
TJmax
Maximum Junction Temperature
Tstg
Storage Temperature Range
Latch−up current maximum rating per JEDEC standard: JESD78.
2. Maximum electrical ratings define the values beyond which permanent damage(s) may occur internally to the chip whatever the operating
temperature may be.
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114
Machine Model (MM) ±200 V per JEDEC standard: JESD22−A115
4. The maximum package power dissipation limit must not be exceeded.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
POWER SUPPLY SECTION: (Typical values are referenced to Ta = +25°C, Min & Max values are referenced −40°C to +85°C ambient
temperature, unless otherwise noted),operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.
Pin
Symbol
15
Vbat
15
VUVLO
15
VUVLOHY
13
13
Rating
Min
Power Supply
2.7
Power Supply Input Voltage (See Figure 22)
2.0
Under Voltage Hysterisis, negative going slope
150
Iout
Continuous load DC current, Vout pin
@ 3.0 V < Vbat < 5.5 V, Cout = 1.0 mF
25
Isw
Output Leakage Current (Lx pin) @ Iout = 0, Vout = 35 V
Vout
Output Voltage Compliance (OVP)
30
OVP Output Voltage Hysterisis
1.0
VoutHY
Typ
2.2
Max
Unit
5.5
V
2.4
V
270
mV
mA
32
200
nA
34
V
1.8
V
Tstart
DC/DC Start time (Cout = 1.0 mF) 3.0 V < Vbat = nominal < 5.5 V from last
ACK bit to full load operation
15
Istdb
Stand By Current, Vbat = 3.6 V, Iout = 0 mA
@SCL = SDA = H (no port activity)
15
Iop
Operating Current, @ Iout = 0 mA, Vbat = 3.6 V
13
IPK
Maximum Inductor Peak Current @ R = 13 kW
13
ITOL
Output Current Tolerance @Vbat = 3.6V, ILED = 10 mA
−25°C < TA < 85°C
13
Fpwr
Boost Operating Frequency (0°C < TA < 85°C)
TSD
Thermal Shutdown Protection
160
°C
TSDH
Thermal Shutdown Protection Hysteresis
30
°C
EPWR
Efficiency @ Vbat = 3.6 V, ESR ≤ 150 mW
Coilcraft = LPO3310−472ML, Cout = 1.0 mF
I−LED = 10 mA, Vf = 2.85 V
I−LED = 25 mA, Vf = 3.4 V (Note 6)
75
80
%
%
Power Switch NMOS RDS(on)
500
mW
RDS(on)
600
ms
1.0
2.0
−10%
6. Note 1: using low DCR inductor with low eddy current losses is mandatory to get the high efficiency operation
5
mA
+10%
1.3
mA
%
±1
1.13
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855
mA
1.47
MHz
NCP5890
ANALOG SECTION: (Typical values are referenced to TA = +25°C, Min & Max values are referenced −40°C to +85°C ambient
temperature, unless otherwise noted), operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.
Pin
Symbol
Rating
Min
Typ
Max
Unit
7
IREF
Reference Current @ Vref = 1144 mV (Note 8)
6
IPK
Reference Current @ Vref = 1144 mV (Note 8)
1
100
mA
1
100
mA
kref
Reference Current to ILED peak current ratio
250
kpk
Reference Current to Inductor peak current ratio
9700
7
VREF
Reference Voltage (Note 8)
−3%
1144
+3%
mV
6
VREFK
Reference Voltage (Note 8)
−10%
1144
+10%
mV
9
VFB
Feedback Voltage @ ILED = 25 mA (Note 9)
MDCY
Boost Operating Maximum Duty Cycle (0°C < TA < 85°C)
9
ILKGM
Current Mirror Leakage Current
10, 11, 12
Fpwm
Low Frequency PWM Clock (derived from Fpwr/8192)
140
Low Frequency Clock (derived from Fpwr/8192)
VVSD
Photo sense bias supply @ Ibias = 1 mA
4
RVSD
Photo sense bias supply internal impedance
4
ISDUSD
FLF
4
90
425
mV
94
%
200
nA
185
Hz
0.6
20
Hz
2.5
Vbat
V
100
nA
1.5
V
160
30
W
Photo sense leakage current (Note 11)
GAMB0.25
Photo sense internal Gain 1/4
0.25
GAMB0.50
Photo sense internal Gain 1/2
0.5
GAMB01
Photo sense internal Gain 1
1
GAMB02
Photo sense internal Gain 2
2
GAMB04
Photo sense internal Gain 4
4
5
Viph
Photo sense input voltage (Note 10)
10
BVpwm2
Breakdown Voltage pin 10 to pin 10 (Note 11)
9
V
11
BVpwm2
Breakdown Voltage pin 11 to Pin 12 (Note 11)
9
V
12
BVpwm1
Breakdown voltage pin 12 to GND (Note 11)
9
V
7. The overall output current tolerance depends upon the accuracy of the external resistor. Using 1% or better resistor is recommended.
8. The external circuit must not force the IREF or IPK pin voltage either higher or lower than the specified voltage. The reference voltage applies
to both IREF and IPK pins.
9. This parameter guarantees the function for production test purposes.
10. The ambient sense linearity is guaranteed when the voltage at the output of the internal amplifier is limited to 1.5 V. This voltage is equal to the
input voltage times the programmed gain. Beyond this value, the operational amplifier is in the saturation region and the linearity is no longer
guaranteed.
11. Parameter guaranteed by design, not tested in production.
DIGITAL PARAMETERS SECTION: (Typical values are referenced to Ta = +25°C, Min & Max values are referenced −40°C to +85°C
ambient temperature, unless otherwise noted), operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.
Pin
Symbol
1
FSCK
1,2
VIH
Positive going Input High Voltage Threshold, SCL, SDA signals
1,2
VIL
Negative going Input High Voltage Threshold, SCL, SDA signals
2
CIN
SDA Input Capacitance
3
VIHD
I2C address extension
3
VILD
I2C address extension
NOTE:
Rating
Min
Typ
Max
Unit
400
kHz
1.6
VBAT
V
0
0.4
V
15
pF
Vbat*0.7
Vbat+0.3V
V
0
0.3
V
Input I2C clock frequency
10
Digital inputs undershoot < − 0.30 V to ground, Digital inputs overshoot < 0.30 V to VBAT
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6
NCP5890
Vbat
DC/DC OPERATION
The boost converter is based on a PWM structure to
generate the output voltage necessary to drive the series
arranged LED. The system includes an open load detection
to avoid over voltage situation when the LED are
disconnected from the Vout pin. A built−in circuit prevent
high inrush current when the system is powered.
The ILED is regulated by means of a built−in current
mirror controlled by the digital content of the ILEDREG
register. With a typical 1.3 Mhz operation frequency, the
converter can run at full power with a tiny 4.7 mH inductor.
However, care must be observed, at DCR level, to optimize
the total DC/DC conversion efficiency. In particular, the
ferrite material shall have limited eddy current losses at
high frequency. Depending upon the type of material, the
eddy losses in the inductor can range from a low 40 mW to
a high 250 mW under the same bias and load conditions.
The ILED current is regulated by the means of internal
current mirror connected to the FB pin. The voltage at this
pin can vary between a low 100 mV to a 1.5 V maximum,
depending upon the ILED current amplitude. Typically, the
FB voltage will be 425 mV under normal operation.
2
CONTROLLER
Current Sense 1
+ H1
COILCRAFT
VLS3010T−4R7MR80
TDK
D5
H
C1
470 nF
M8
2
D6
3
D2
1
D4
FEEDBACK
Vbat
I1
Iref
3
M9
1
2
2
3
M10
1
Figure 4. Simplified Boost Structure
Manufacturers
LPO3310−472ML
−
DNSR0320MW2T1
D3
Table 1. Recommended Inductor Manufacturers
Part Number
L1
4.7uH
Vbat
Vbat = 3.6 V
ILED = 25 mA
Figure 5. Typical Switching Operation
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NCP5890
Although the total ohmic resistance plays an important
role in the losses developed in the converter, the switching
losses are key when the operating frequency is beyond a
few kilohertz range. To minimize such losses, the internal
power NMOS is designed to minimize the dI/dt, thus
minimizing the I*V crossing time. As a consequence, the
slope of the positive going voltage −VLX− present at the Lx
pin is very fast as well and an overshoot is created since the
Schottky rectifier has an intrinsic turn-on time: the voltage
keeps going until the diode turns−on, clamping the VLX
voltage at the output value. Such a mechanism is depicted
in Figure 6. The proposed Schottky, depicted in the
schematic Figure 1, is a good alternative to minimize such
an overshoot.
On the other hand, the same overshoot is propagated to
the Vout voltage when the system operates under open load
condition. As a consequence, it is strongly recommended
to implement a simple filter, built with a small footprint
resistor, to makes sure that no any uncontrolled operation
of the high sensitive pin Vos will happen under the worst
case conditions: see Figure 1, resistor R5.
Figure 6. Typical Turn On Time of the Schottky Rectifier
I2C Protocol
The standard I2C protocol is used to transfer the data
from the MCU to the NCP5890. Leaving aside the
Acknowledge bit, the NCP5890 chip does not return data
back to the MCU.
The physical address of the NCP5890 can be selected as
0111 001X or 0111 010X (the X being the Read / Write
identifier as defined by the I2C specification) depending
upon the digital status present at the I2CADR pin:
To set up a new output current value, a full frame will be
sent by the MCU. The frame contains three consecutive
bytes and shall fulfill the I2C specifications (see Figure 7):
− First byte: I2C address, write ³ $72
(assuming I2CADR = Low)
− Second byte: register selection ³ %0000 XXXX =
internal register address
− Third byte: DATA ³ %XXXX XXXX = function /
output current value
An infinite number of register selection / data pair can be
send on the I2C port once the physical address has been
decoded (see Figure 8). The transmission ends when the
STOP signal is send by the SCL/SDA digital code.
I2CADR = Low ³ address = %0111 0010 = $72
I2CADR = High ³ address = %0111 0100 = $74
In order to avoid any risk during the operation, the digital
level at the I2CADR pin must be hardwired either to GND
or to Vbat prior to power up the system.
The first byte of the I2C frame shall be selected address
($72 or $74) when a Write is send to the chip.
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NCP5890
SCL
B7 B6 B5 B4 B3 B2 B1 B0 ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK B7 B6 B5 B4 B3 B2 B1 B0 ACK
SDA
I2C Address
Start Conditions
Register Selection
DATA
Stop conditions
Figure 7. Single Frame I2C Sequence
SCL
SDA
I2C Address
Register Selection
DATA Register
N sequences
Register Selection
DATA Register
Figure 8. Multi Frames I2C Sequence
On the other hand, although the chip does not handle the
Read operation, care must be observed since sending a
Read command ($73 or $75) is equivalent to a Write
command and the selected register will be updated
accordingly.
The last code $0F is reserved for ON Semiconductor to
control the manufacturing test and access to this register is not
permitted outside the ON Semiconductor final test facilities.
Shutdown and True Cut−off
To shutdown the device the user must write $00 in
Register Selection. When in shutdown condition, FB pin is
turned in impedance and truly isolates the load from the
battery. The NCP5980 is immediately turn on when one of
the Register Selection from $01 to $0F is active to point a
given DATA Register.
Registers Setup Selection
The Register Selection follows the I2C address of a new
frame and must be followed by the DATA Register. The
content of the Register Selection byte is not stored into the
chip and a new one must be sent for every DATA upload.
Table 2. Register Selection
Register Functions
Register
Address
SDN
$00
Select I−LED current setup and immediate LED update
ILEDREG[4..0]
$01
Select I−LED target Gradual Dimming command UP
GDIM−UP[4..0]
$02
GDIM−DWN[4..0]
$03
Set Timing & Start gradual Dimming Sequence
TDIM[4..0]
$04
Select PWM0 register
PWM0[4..0]
$05
Select PWM1 register
PWM1[4..0]
$06
Select PWM2 register
PWM2[4..0]
$07
Shutdown the chip
Select I−LED target Gradual Dimming command DOWN
Set up Photo sense input stage gain
PHGAIN[4..0]
$08
Set up Photo Sense I−LED minimum value
PHMIN[3..0]
$09
Set up Photo Sense timing
PHCLK[5..0]
$0A
RFU
$0B
RFU
$0C
RFU
$0D
RFU
$0E
Reserved for manufacturing test: do not access
FTEST[7..0]
$0F
ILED Current
The ILED current depends upon the reference current
(IREF pin ) and the digital contents of the ILEDREG
register. The I2C port is used to program the ILED current
by writing to the ILEDREG register. The load current is
derived from the 1144 mV reference voltage associated to
the external resistor connected across IREF pin and Ground
(see Figure 9). The maximum ILED current is given by the
internal current mirror ratio (multiplier − k−) equal to 250.
In other words, to get a 25 mA maximum, with a 100% full
range (ILEDREG = $1F), the reference current should be
25 mA/250 = 100 mA. This current is used to calculate the
resistor connected between the IREF pin and GND: RREF
= 1.144 / 100e−6 = 11.44 kW. In any case, no voltage shall
be forced at IREF pin, either downward or upward.
The tolerance of the external resistor must be 1% or
better, with a 100 ppm thermal coefficient, to get the
expected overall tolerance.
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9
NCP5890
+Vbat
ILED
Digital
Control
ILED
1144 mV
U2
R2
12k
GND
I2C
1
GND
Figure 9. Basic Reference Current Source
NOTE:
The IREF pin must never be biased by an external voltage higher than 1144 mV.
The ILED current is given by Table 3 as a percentage of the maximum programmed ILED value (100% will give 25 mA
when Iref = 100 mA).
Table 3. Output Current (%) versus ILED Step Value
Step # ($)
Iout %
Step # ($)
Iout %
Step # ($)
Iout %
Step # ($)
Iout %
00
0.00
08
1.40
10
6.24
18
27.48
01
0.42
09
1.70
11
7.52
19
33.03
02
0.49
0A
2.00
12
9.11
1A
39.72
03
0.57
0B
2.42
13
10.92
1B
47.72
04
0.72
0C
2.99
14
13.08
1C
57.47
05
0.87
0D
3.63
15
15.80
1D
69.18
06
1.02
0E
4.35
16
18.97
1E
83.20
07
1.17
0F
5.22
17
22.86
1F
100.00
100
Iout(%)
10
1
0.1
0
5
10
15
20
STEP
25
30
35
Figure 10. Typical Iout (%) versus ILED Step Value
$01 ILEDREG[0..4] I−LED Peak Current
B7
B6
B5
B4
B3
B2
B1
B0
step
−
−
−
ILED16
ILED8
ILED4
ILED2
ILED1
RESET
0
0
0
0
0
0
0
0
Bits [B7:B5] : RFU
Bits [B4:B0] : ILED peak current setup
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NCP5890
Inductor Peak Current
1. The target current level (either upward or
downward)
2. The time per step
When a new gradual dimming sequence is requested, the
output current changes, according to the exponential curve,
from the existing start value to the end value. The end
current value is defined by the contents of the Upward
(GDIM−UP) or Downward (GDIM−DWN) register, the
width of each step is defined by the TDIM register, the
number of steps being in the 1 to 32 range ($00 to $1F). In
the event of a software error, the system checks that neither
the maximum output current (25 mA), nor the zero level
are forced out of their respective bounds. Similarly,
software errors shall not force NCP5890 into an
uncontrolled mode of operation.
The dimming is built with 32 steps and the time delay
encoded into DATA register which is the third byte upload
by I2C transmission.
When the gradual dimming is not requested (register
selection = $01), the output current is set up to the level
defined by the contents of the related register upon
acknowledge of the output current byte.
The gradual dimming sequence must be set up before a
new output current data byte is sent to the NCP5890. At this
point, the brightness sequence takes place when the new
data byte is acknowledged by the internal I2C decoder.
Since the six registers are loaded on independent byte flow
associated to the I2C address, any parameter of the
NCP5890 chip can be updated ahead of the next function.
This safety feature is clamping the maximum current
allowed in the inductor according to external RPCA resistor,
which is connected between IPK input and the ground.
The maximum IPK current is given by the internal current
mirror ratio (multiplier − kk −) typically equal to 9700. In
other words, to get a 855 mA maximum peak current in the
inductor, the reference current should be 850 mA/9700 =
87.6 mA. This current is used to calculate the resistor
connected between the IPK pin and GND: RREF = 1.144 /
87.6e−6 = 13 kW.
The concept depicted in the ILED current paragraph
applies as well and care must be observed to avoid any
voltage source connection to the IPK pin.
Gradual Dimming
The purpose of this function is to gradually Increase or
Decrease the brightness of the backlight / keyboard LED
upon command from the external MCU. The function is
activated and controlled by means of the I2C protocol.
The period (either upward or downward) is equal to the
time defined for each step, multiplied by the number of
steps. The number of step is derived from the value
associated with the target current.
To operate such a function, the MCU will provide two
information:
$02 GDIM−UP[4..0] and $03 GDIM−DWN[4..0] Gradual Dimming Target
B7
B6
B5
B4
B3
B2
B1
B0
ms
−
−
−
ILED5
ILED4
ILED3
ILED2
ILED1
RESET
0
0
0
0
0
0
0
0
Bits [B7:B5] : RFU
Bits [B4:B0] : ILED peak current setup or Gradual Dimming Timing
− Second byte = 0000 0010 ³ select an ILED target
UPWARD sequence
− Third byte = 0000 1111 ³ set I−LED =
2.51% of the maximum range
− First Byte = 0111 0000 ³ I2C address
(assuming I2CADR = Low)
− Second byte = 0000 0100 ³ set Timing and start the
sequence
− Third byte = 0000 0010 ³ set Timing per step =
20 ms/step
The number of steps for a given sequence, depends upon
the start and end output current range: since the IPEAK
value is encoded in the ILEDREG [4:0] binary scale, a
maximum of 31 steps is achievable during a gradual
dimming operation.
To select the direction of the gradual dimming (either
Upward or Downward), one shall set−up the appropriate
register before to activate the sequence as depicted in the
example here below:
− First Byte = 0111 0000 ³ I2C address
(assuming I2CADR = Low)
$04 TDIM[4..0] Gradual Dimming Time per Step
B7
B6
B5
B4
B3
B2
B1
B0
ms
0
0
0
200
100
50
25
12.5
RESET
0
0
0
0
0
0
0
0
Bits [B7:B5] : RFU
Bits [B4:B0] : Gradual Dimming Timing
NOTE:
bit B0 = 2^14/F, with F = operating frequency (1.3 MHz typical)
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NCP5890
Figure 11. Typical Gradual Dimming UPWARD
Figure 12. Typical Gradual Dimming DOWNWARD
Keyboard Dimming
The keyboard shares the same I−LED peak current with the backlight, but the built−in PWM structure makes possible a
dynamic independent control of three sets of LED. Each PWM is associated with a register, the IC port being used to update
the pulse modulation as requested by the application.
$05 PWM0[4..0] PWM0 Modulation
B7
B6
B5
B4
B3
B2
B1
B0
%
−
−
−
50
25
12.5
6.25
3.125
RESET
0
0
0
0
0
0
0
0
Bits [B7:B5] : RFU, Bits [B4:B0] : PWM0 setup
$06 PWM1[4..0] : PWM1 Modulation
B7
B6
B5
B4
B3
B2
B1
B0
%
−
−
−
50
25
12.5
6.25
3.125
RESET
0
0
0
0
0
0
0
0
Bits [B7:B5] : RFU, Bits [B4:B0] : PWM1 setup
$07 PWM2[4..0] : PWM2 Modulation
B7
B6
B5
B4
B3
B2
B1
B0
%
−
−
−
50
25
12.5
6.25
3.125
RESET
0
0
0
0
0
0
0
0
Bits [B7:B5] : RFU, Bits [B4:B0] : PWM2 setup
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NCP5890
Ambient Light Control
− upper I−LED as defined by the end user: the photo
sense cannot increase the I−LED above such a limit
− lower I−LED as defined by the end user: the photo
sense cannot reduce the back light current to zero.
When the photo sense activates the counter (in either
direction), a selectable low frequency clock drives the
counter, yielding a smooth and slow brightness variation.
The 100 Hz noise, coming from standard fluorescent
tubes, is filter out by means of an external network built
between the photo sensor and the AMBS pin. Generally
speaking, such a filter is built with a RC network designed
to cope with the electrical performances of the selected
photo sense. As a consequence, the AMBS pin is biased by
a low level voltage signal and processed accordingly the
ambient light control structure: see Figure 16.
The ambient light can be monitored, by an extra photo
diode, to automatically adjust the I−LED peak current as a
function of the ambient light. A dedicated I2C command is
used to activate or de−activate this function. On the other
hand, the end user shall set up the maximum I−LED current
by means of an I2C command. The photo sense is
automatically de−activated when an I2C command is send
through the port, and resume to the pre−programmed status
when the I2C command is completed.
The concept is based on analog monitoring of the I−LED
current and the photo sense feedback, associated to a
Up/Down counter to properly setup the contrast at display
level. The photo sense action is bounded by two limits:
VSB
+VBat
4
GAIN
SFH5711
U3
Log
1
VSB
4
R2
AMBS
220k
5
R/2
R
GND
2
R1 22k
C1
2.2uF
ANALOG
MONITORING
U1
GND
I2C
Digital Gain Adjust
GND
R/4
R
R/2
R
2R
4R
Figure 13. Basic Photo Sense Input Circuit
Since several types of photo sensor can be used in the final application, provisions have been taken into account to dynam−
ically adjust the gain of the photo current. Such capability is carried out by the internal register loaded through the I2C port.
$08 PHGAIN[0..4][7]
RESET
Gain
B7
B6
B5
B4
B3
B2
B1
B0
VSD
−
−
PHG5
PHG4
PHG3
PHG2
PHG1
0
0
0
0
0
0
0
0
4
2
1
0.50
0.25
Bit [B7] : Photo sense VSD bias control
Bit [B7] : B7 = 0 ³ VSD disconnected, photo sense function de−activated
Bit [B7] : B7 = 1 ³ VSD connected, photo sense function activated
Bits [B6:B5] : RFU
Bits [B4:B0] : Photo sensor gain adjust
The photo sensor no longer influences the I−LED when the gain is setup to $00. On the other hand, the five bits can be
digitally combined to get different gain in the range 0 to 7.75.
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NCP5890
When the photo sense returns a lower ambient light level
in comparison to the maximum level set up by the user, the
I−LED decreases with a timing defined by an I2C
command. Such a timing is derived from the Low
Frequency clock and selected by the PHTIM register (see
Figure 14).
$0A PHTIM[0..5]
RESET
B7
B6
B5
B4
B3
B2
B1
B0
−
−
PHT6
PHT5
PHT4
PHT3
PHT2
PHT1
0
0
0
0
0
0
0
0
Bits [B7] : RFU
Bits [B6] : RFU
Bits[B5:B0] :
PHT1 = T = 50 ms/step
PHT2 = T = 100 ms/step
PHT3 = T = 200 ms/step
PHT4 = T = 400 ms/step
PHT5 = T = 800 ms/step
PHT6 = T = 1600 ms/step
Note: the bits cannot be combined to generate a different timing.
In addition, the positive and negative slopes of the I-LED current are intentionally different. In order to generate a smooth
transition of the backlight from maximum toward the minimum calculated by the photo sense, the timing of the negative
going slope is twice the timing of the positive going slope.
Phot Sense AMBS
I−LED maximum
I−LED minimum
PHTIM
16ms to 7500ms
PHTIM
16ms to 7500ms
Figure 14. Basic Photo Sense Timing
The rise and fall time of the I−LED current are
programmable (according to the PHTIM register contain).
The timing is defined by the PHTIM[B5:B0] bits
multiplied by the number of steps necessary to reduce /
increase the I−LED form one value to the next limit.
On the other hand, the I−LED cannot be reduce to zero
during the Photo sense operation: the contain of the
PHMIN[B3:B0] register limits the low end current when
the photo sensor is in a dark environment.
$09 PHMIN[0..7]
B7
B6
B5
B4
B3
B2
B1
B0
step
−
−
−
−
PHM4
PHM3
PHM2
PHM1
RESET
0
0
0
0
0
0
0
0
Bits [B7:B4] : RFU
Bits[B3:B0] : set up the I−LED minimum value, according to the exponential table.
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14
NCP5890
ILED Max
(25 mA, programmable)
Ambient Light
Gradual Dimming:
Photo sense
de−activated
I−setup
ILED Min (Programmable)
Photo Sense
The photo sense register is loaded with the I2C content
Ambient Light < I2C ILED : the Photo sense controls the ILED
The Photo Sense cannot force t he ILED below the pre−programmed minimum level
The Photo Sense controls ILED within the Imin and I−setup limits
When a Downward Gradual Dimming is engaged, the ILED is reduced from the level
defined by the Photo sense to the lower value defined by the gradual dimming register containt.
Figure 15. Basic Gradual Dimming and Photo Sense Operation Strategy
Figure 16. Basic Ambient Photo Sense Regulation (PSPICE simulation)
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15
NCP5890
PWM Sequence
The three PWM can be controlled according to one of the
possible sequence depicted in Figure 17. In all cases, the
Main Display is powered first.
Strategy #1: the three PWM are fully synchronized and
share the same timings, the rise and fall time being
identical. At this point, the feedback voltage will rapidly
swap from a low 400 mV (normal operation) to the large Vf
span coming from the three LED added in series.
Strategy #2: the three PWM share the same rise and fall
time, the sequence being synchronized but delayed until
the previous LED is at full power (PWM = 100%). This is
the most stable sequence, from a human eye stand point,
since we have a minimum blinking (one Vf variation only).
Strategy #3: the three PWM share the same rise and fall
time but they can be activated independently.
Startegy#4: the three PWM operate randomly: the
NCP5890 is capable of operating under such conditions,
but care must be observed since such random PWM (as
depicted by the circles) might be a stress from a human eye
stand point.
Main Display
PWM1
Strategy #1
PWM2
PWM3
PWM1
Strategy #2
PWM2
PWM3
PWM1
Strategy #3
PWM2
PWM3
PWM1
Strategy #4
PWM2
PWM3
Figure 17. Basic PWM Sequences
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16
NCP5890
In addition, the first PWM structure can control two LED in series as depicted in Figure 18. The next PWM pin is limited
to 9.5 V and cannot accommodate over voltage during the operation.
D1
I−Load Max = 25mA
D2
D3
Vout
16
PWM1
12
PWM#1 DRIVER
D4
DZ1
9.5V
D5
PWM2
PWM#2 DRIVER
11
DZ2
9.5V
GND
PWM3
10
DZ3
9.5V
PWM#3 DRIVER
IREF
D6
GND
D7
FB
9
GND
Figure 18. Basic PWM Internal Voltage Clamps
+Vbat
L1
C1
4.7 mF/6.3 V
GND
15
1
SCL
2
SDA
3
SFH5711
U3
Log
1
2
GND
4.7 mF
U1
NCP5890
R1
R2
2.2 mF
12 k
7
D11
Lx
Vbat
SCL
Vos
SDA
VSB
IREF
6
IPK
22 k
AGND
8
PWM1
PWM2
PWM3
FB
PGND
14
C2
D1
GND
D3
16
R5
D4
12
D5
11
D7
10
D8
9
GND
Figure 19. Serial PWM#1 Extension LED
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17
1.0 mF/50 V
D2
13
I2CADR
22 k
GND
R4
5
220 k
AMBS
C4
GND
4
R3
4
MBR0540
D6
NCP5890
+Vbat
L1
C1
4.7 mF/6.3 V
GND
15
1
SCL
2
SDA
3
SFH5711
U3
Log
1
NSR0130M2T5G
GND
4
R3
4.7 mF
U1
NCP5890
Lx
Vbat
SCL
Vos
SDA
VSB
PWM1
2
C4
2.2 mF
R1
12 k
7
GND
PWM3
IREF
6
IPK
22 k
AGND
8
R2
PWM2
FB
PGND
14
GND
D2
16
D3
R9
1.0 mF/50 V
D1
13
I2CADR
22 k
GND
R4
5
220 k
AMBS
4
D11
C2
R5
D4
12
D5
100R
D6
100R
R6
11
R7
10
9
D7
100R
D8
100R
R8
D9
GND
Figure 20. Paralleling Extension LED
ESD PROTECTION CIRCUIT
Although the structures are capable to handle the ESD
stresses (as defined by the JEDEC specifications), no
current or voltage, either DC or AC, beyond the maximum
ratings specifications shall be applied to any pin.
Depending upon the function of the pin, different
circuitry is applied. The basic structures are illustrated in
Figure 21.
+Vcc
D1
Vsw pin
FET_P
DRIVER
I/O Pin
FET_N
D2
Standard Low
Voltage Structure
GND
High Voltage
Structure
FET_N
GND
GND
Figure 21. Typical ESD Protection Structures
UNDERVOLTAGE LOCKOUT
The system resumes to normal operation when the input
voltage increases by the minimum value plus the hysteresis
as specified in the data sheet.
The VUVLO circuit is used to disconnect the chip when
the input voltage is below the minimum operating value.
Vbat
D1
Vz45V
Hysteresis
VUVLO
Engage the shutdown mode
Resume to normal operation
Figure 22. Undervoltage Lockout Basic Mechanism
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NCP5890
PACKAGE DIMENSIONS
UQFN16 3x3, 0.5P
CASE 523AF−01
ISSUE O
A
D
ÇÇÇ
ÇÇÇ
ÇÇÇ
PIN ONE
REFERENCE
2X
B
L
DETAIL A
OPTIONAL CONSTRUCTION
2X SCALE
E
DETAIL B
OPTIONAL CONSTRUCTION
4X SCALE
TOP VIEW
17X
A
DETAIL B
0.05 C
0.05 C
A1
NOTE 4
MILLIMETERS
MIN
MAX
0.45
0.60
0.00
0.05
0.127 REF
0.20
0.30
3.00 BSC
1.60
1.80
3.00 BSC
1.60
1.80
0.50 BSC
0.20
−−−
0.30
0.50
SEATING
PLANE
SOLDERING FOOTPRINT*
D2
0.50
PITCH
K
5
e/2
A3
C
SIDE VIEW
DETAIL A
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
ÎÎ
0.10 C
2X
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
e
9
16X
E2
0.60
2X
1
16X
L
2X
1.55 3.30
13
16X
BOTTOM VIEW
b
0.10 C A B
0.05 C NOTE 3
1
16X
0.29
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP5890/D