Ordering number : ENA0569A LC74736PT CMOS IC On-Screen Display Controller Overview The LC74736PT is an on-screen display CMOS IC that displays characters and patterns on a TV screen under the control of a microcontroller. For QVGA display, the LC74736PT supports the use of both a 16 × 16 dot character font and a 16 × 16 dot graphic font with 16 colors. For WVGA display, the LC74736PT supports the use of both a 24 × 32 dot character font and a 24 × 32 dot graphic font with 16 colors. The LC74736PT can also implement extremely varied displays by the use of an external ROM. The LC74736PT supports both QVGA (480×234) and WVGA (800×480). Features (1) Screen structure Main: 2 screens (1 screen for WVGA display) 30 characters×15 lines (up to 450 characters) on a QVGA panel 33 characters×15 lines (up to 495 characters) on a WVGA panel (Up to 34 characters×18 lines) Wallpaper display screen: QVGA mode: maximum Permanent repetition of a 4×4 (horizontal×vertical) character pattern WVGA mode: maximum Permanent repetition of a 2×2 (horizontal×vertical) character pattern Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 60607HKIM 20061221-S00013 No.A0569-1/106 LC74736PT (2) Character structure QVGA mode: About 9MHz 16 dots (horizontal) ×16 dots (vertical): Character display 16 dots (horizontal) ×16 dots (vertical): Graphic glyph display WVGA mode: About 33.2MHz 24 dots (horizontal) ×32 dots (vertical): Character display 24 dots (horizontal) ×32 dots (vertical): Graphic glyph display Character display clock: LC oscillator (about 10MHz) External clock signal input (up to 40MHz) Built-in PLL (VCO) (7 to 40MHz) (3) Number of characters QVGA mode Up to 16384 characters when an external 16-bit 16M ROM is used. WVGA mode Up to 4096 characters when an external 16-bit 16M ROM is used. No internal ROM Internal character RAM QVGA: 4 characters, WVGA: 1 character (4) Character sizes: Four horizontal sizes (1×, 2×, 3×, and 4×) Four vertical sizes (1×, 2×, 3×, and 4×) (The character size is specified in line units.) (5) Display start positions: 1024 positions in the horizontal direction and 512 positions in the vertical direction. Setting units: Horizontal: 1 dot (in screen units) Vertical: 1 dot (in screen units) (6) Display functions • Blinking specification (in character units) Period: 1/64, 1/32, and 1/16 of the vertical sync signal (in screen units) Duty: Fixed at 50% • Box (raised or recessed) display Raised/recessed specification (in character units) Left: Off/on specification (in character units) Right: Off/on specification (in character units) Top: Off/on specification (in character units) Bottom: Off/on specification (in character units) • Border specification (in line units): Only valid with glyphs from the character font. (7) Color specification Character • Character color (in character units): 1 of 16 colors can be specified. • Character background color (in character units): 1 of 16 colors can be specified. • Border color (in line units): 1 of 16 colors can be specified. Graphic • 16 types can be specified by ROM data Graphic 2 • 16 types can be specified by ROM data 1 color type can be changed. Graphic 3 • 16 types can be specified by ROM data 1 color table type can be changed. • Box (raised or recessed) color (line units): 1 of 16 colors can be specified. • Background color (screen units): 1 of 16 colors can be specified. No.A0569-2/106 LC74736PT (8) Color table (palette) • Sixteen colors can be selected from a set of 4096 colors (One of which is specified to be transparent.) • Number of color tables: 4. This allows up to 64 colors to be displayed at the same time. (9) Wallpaper screen (Graphics glyphs only) Wallpaper display: Repeated display under the main screen (up to 4 characters horizontally by 4 characters vertically). Sprite character display: Displayed above the main screen (up to 4 characters horizontally by 4 characters vertically). (10) Line spacing control 0-15 scan lines (in line units) (11) Output Analog RGB output( to 20MHz) Digital RGB output (4 bits per color) BLK (OSD display period signal) Package: TQFP100 Voltage: 3.3V Package Dimensions unit : mm (typ) 3274 75 0.5 16.0 14.0 51 50 100 26 14.0 16.0 76 1 0.5 0.2 25 0.125 1.2max 0.1 (1.0) (1.0) SANYO : TQFP100(14X14) No.A0569-3/106 LC74736PT A18 A17 A16 VSS3 VDD3 A15 A14 A13 A12 A11 A10 A9 A8 VSS3 VDD3 A7 A6 A5 A4 A3 A2 A1 A0 VSS3 VDD3 Pin Assignment 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VSS1 1 75 A19 VDD1 2 74 CE OSCin 3 73 OE OSCout 4 72 VDD3 EXTclk 5 71 VSS3 CTRL1 6 70 VDD1 SCLK 7 69 VSS1 SIN 8 68 D0 CS 9 67 D1 VSYNC 10 66 D2 HSYNC 11 65 D3 TEST1 12 64 D4 LC74736PT TEST2 13 63 D5 RST 14 62 D6 CLKOUT 15 61 D7 VSS1 16 60 VDD1 NC 17 59 VSS1 NC 18 58 D8 NC 19 57 D9 NC 20 NC 21 56 D10 VSS4 22 PD0 23 54 D12 VCOR 24 VDD4 25 52 D14 55 D11 53 D13 51 D15 VSS2 VDD2 CCOMP RREF BOUT ROUT GOUT VSS1 HFTOT BLK BD0 BD1 BD2 BD3 GD0 VDD1 GD1 GD2 RD0 GD3 RD1 RD2 RD3 BFout BFin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Top view No.A0569-4/106 LC74736PT Pin Functions Pin No. Symbol 1 VSS1 Type Ground Functional description Connect a ground to this pin. (Digital system ground) 2 VDD1 Power supply (+3.3V) Digital system power supply: +3.3V 3 OSCin LC oscillator Connect to the character output dot clock generator oscillator coil and 4 OSCout 5 EXTclk External clock signal input 6 CTRL1 OSCin oscillator input control capacitor. Receives an external clock signal. Capacitor coupling, 50% duty cycle, 0.5Vp-p or higher Switches between external clock input mode and LC oscillator mode. Low: LC oscillator, high: external clock input MORE+ OR control with MORE+ command 7 SCLK Clock input Clock input for the serial data input system MORE+ (This input has hysteresis characteristics.) 8 SIN Data input Serial data input MORE+ (This input has hysteresis characteristics.) 9 CS Enable input Enable input for the serial data input system. Serial data input is enabled when this pin is set low. MORE+ (This input has hysteresis characteristics.) 10 VSYNC Vertical sync signal input Vertical sync signal input MORE+ (This input has hysteresis characteristics.) 11 HSYNC Horizontal sync signal input Horizontal sync signal input MORE+ (This input has hysteresis characteristics.) 12 TEST1 Test mode control 1 Test mode control 1 Low: normal operation, high: test mode MORE+ 13 TEST2 Test mode control 2 Test mode control 2 Low: normal operation, high: test mode (scan mode) MORE+ 14 RST Reset input 15 CLKOUT Clock output Clock output 16 VSS1 Ground Connect a ground to this pin. (Digital system ground) 17 NC 18 NC 19 NC 20 NC System reset input MORE+ (This input has hysteresis characteristics.) 21 NC 22 VSS4 23 PD0 Ground Connect a ground tro this pin. (PLL system power supply) PLL charge pump output Charge pump output Connect a LPF (lug lead filter) to this pin. PLL VCO control voltage input 24 VCOR VCO variable range adjustment Voltage input for internal VCO control Used to adjust variable voltage range of internal VCO. Connect a resistor to this pin. 25 VDD4 26 BFin 27 BFout 28 Power supply (+3.3V) PLL system power supply: +3.3V Amplifier input Oscillation input for external VCO Amplifier output Oscillation output for external VCO RD3 Rout output: bit 3 Rout output 29 RD2 Rout output: bit 2 This is a 4-bit digital output with values from 0000 to 1111. 30 RD1 Rout output: bit 1 31 RD0 Rout output: bit 0 32 GD3 Gout output: bit 3 Gout output 33 GD2 Gout output: bit 2 This is a 4-bit digital output with values from 0000 to 1111. 34 GD1 Gout output: bit 1 35 GD0 Gout output: bit 0 36 VDD1 Power supply (+3.3V) Digital system power supply: +3.3V Continued on next page. No.A0569-5/106 LC74736PT Continued from preceding page. Pin No. Symbol 37 BD3 Bout output: bit 3 Type Bout output Functional description 38 BD2 Bout output: bit 2 This is a 4-bit digital output with values from 0000 to 1111. 39 BD1 Bout output: bit 1 40 BD0 Bout output: bit 0 41 BLK Blanking signal output This signal indicates the OSD display period. 42 HFTOT Halftone control signal output OSD halftone period control signal 43 VSS1 Ground Connect a ground to this pin. (Digital system ground) 44 Rout Rout output: analog D/A converter (4 bits) output. Connect a resistor Ro to this pin. 45 Gout Gout output: analog D/A converter (4 bits) output. Connect a resistor Ro to this pin. 46 Bout Bout output: analog D/A converter (4 bits) output. Connect a resistor Ro to this pin. 47 RREF Reference resistor connection Connect a reference register to this pin. 48 VDD2 Power supply (+3.3V) D/A converter power supply: +3.3V 49 CCOMP Phase correction capacitor connection Capacitor connection: 1.5µF 50 VSS2 51 Synthesized in the next stage IC. Ground Connect a ground to this pin. (D/A converter ground) D15 Data input 15 ROM data input 15. MORE+ [MSB] 52 D14 Data input 14 ROM data input 14. MORE+ 53 D13 Data input 13 ROM data input 13. MORE+ 54 D12 Data input 12 ROM data input 12. MORE+ 55 D11 Data input 11 ROM data input 11. MORE+ [MSB] 56 D10 Data input 10 ROM data input 10. MORE+ 57 D9 Data input 9 ROM data input 9. MORE+ 58 D8 Data input 8 ROM data input 8. MORE+ Connect a ground to this pin. (Digital system ground) 59 VSS1 Ground 60 VDD1 Power supply (+3.3V) Digital system power supply: +3.3V 61 D7 Data input 7 ROM data input 7. MORE+ 62 D6 Data input 6 ROM data input 6. MORE+ 63 D5 Data input 5 ROM data input 5. MORE+ 64 D4 Data input 4 ROM data input 4. MORE+ 65 D3 Data input 3 ROM data input 3. MORE+ 66 D2 Data input 2 ROM data input 2. MORE+ 67 D1 Data input 1 ROM data input 1. MORE+ 68 D0 Data input 0 ROM data input 0. MORE+ [LSB][LSB] Connect a ground to this pin. (Digital system ground) 69 VSS1 Ground 70 VDD1 Power supply (+3.3V) Power supply: (+3.3V: Digital system) 71 VSS3 Ground Connect a ground to this pin. (External ROM output system ground) 72 VDD3 Power supply (+3.3 or +5.5V) Power supply (External ROM output system power supply) 73 OE Output enable ROM output enable output. This is an active low output. 74 CE Chip enable ROM chip enable output. This is an active low output. 75 A19 Address output 19 ROM address output 19 76 A18 Address output 18 ROM address output 18 77 A17 Address output 17 ROM address output 17 78 A16 Address output 16 ROM address output 16 79 VSS3 Ground Connect a ground to this pin. (External ROM output system ground) 80 VDD3 Power supply (+3.3 or +5.5V) Power supply (External ROM output system power supply) 81 A15 Address output 15 ROM address output 15 82 A14 Address output 14 ROM address output 14 83 A13 Address output 13 ROM address output 13 84 A12 Address output 12 ROM address output 12 85 A11 Address output 11 ROM address output 11 Continued on next page. No.A0569-6/106 LC74736PT Continued from preceding page. Pin No. Symbol 86 A10 Address output 10 Type ROM address output 10 Functional description 87 A9 Address output 9 ROM address output 9 88 A8 Address output 8 ROM address output 8 89 VSS3 Ground Connect a ground to this pin. (External ROM output system ground) 90 VDD3 Power supply (+3.3 or +5.5V) Power supply (External ROM output system power supply) 91 A7 Address output 7 ROM address output 7 92 A6 Address output 6 ROM address output 6 93 A5 Address output 5 ROM address output 5 94 A4 Address output 4 ROM address output 4 95 A3 Address output 3 ROM address output 3 96 A2 Address output 2 ROM address output 2 97 A1 Address output 1 ROM address output 1 98 A0 Address output 0 ROM address output 0 99 VSS3 Ground Connect a ground to this pin. (External ROM output system ground) 100 VDD3 Power supply (+3.3 or +5.5V) Power supply (External ROM output system power supply) Specifications Absolute Maximum Ratings at Ta=25°C Parameter Supply voltage Input voltage Symbol Unit VDD1 VDD1,VDD2, and VDD4 VSS-0.3 to VSS+4.6 VDD3 VSS-0.3 to VSS+6.0 V VSS-0.3 to VDD1+0.3 V HFTOT outputs VSS-0.3 to VDD1+0.3 V A0 to 19, CE, OE outputs VSS-0.3 to VDD3+0.3 V VOUT1 VOUT2 Maximum power dissipation Ratings VDD3 VIN Output voltage Conditions All input pins RD3 to RD0, GD3 to GD0, BD3 to BD0, BLK, Pd max 275 V mW Operating temperature Topr -40 to +85 °C Storage temperature Tstg -40 to +125 °C Recommended Operating Conditions Parameter Symbol Ratings Conditions min Supply voltage Input high-level voltage Input low-level voltage Oscillator frequency (LC) typ VDD1 VDD1, 2, and VDD4 3.0 3.3 3.6 V VDD3 VDD3 3.0 3.3 5.5 V VIH1 CTRL1, TEST1, TEST2 0.7VDD1 5.5 V VIH2 SCLK, SIN, CS, VSYNC, HSYNC, RST 0.8VDD1 5.5 V VIH3 D0 to D15 0.7VDD1 5.5 V VIL1 CTRL1, TEST1, TEST2 VSS-0.3 0.3VDD1 V VIL2 SCLK, SIN, CS, VSYNC, HSYNC, RST VSS-0.3 0.2VDD1 V VIH3 D0 to D11 VSS-0.3 0.3VDD1 V FOSC1 OSCin and OSCout oscillator pins 10 (LC oscillator) External clock input FOSC2 VIN1 OSCin, VDD1 = 3.3V VDD1 = 3.3V CTRL1 = high Oscillator frequency (VCO) FOSC3 VCO oscillator (internal) D/A converter (4-bit, 3 ch) Vrefda Reference voltage When maximum output voltage = 0.7V Unit max Rfda Output load resistance ROUT, GOUT, BOUT Rref Reference load resistance, RREF 33 0.5 7 MHz 40 MHz 3.3 Vp-p 40 MHz 1.1 120 V 225 1100 Ω Ω No.A0569-7/106 LC74736PT Electrical Characteristics at Ta = -40 to +85°C, VDD = 3.3V unless otherwise specified Parameter Symbol Pin Ratings Conditions min Output high-level VOH1 voltage RD3 to RD0, GD3 to GD0, BD3 to BD0, BLK, and HFTOT outputs Output low-level typ Unit max VDD1 = 3.0V IOH1 = -8mA VDD1 -0.8 V VOH2 A0 to A19, CE, and OE VDD3 = 3.0V IOH2 = -8mA VDD3 -0.8 V VOH3 A0 to A19, CE, and OE VDD3 = 4.5V IOH3 = -8mA VDD3 -0.8 V RD3 to RD0, GD3 to GD0, BD3 to VDD1 = 3.0V IOL1 = 8mA 0.4 V VOL1 voltage BD0, BLK, and HFTOT outputs VOL2 A0 to A19, CE, and OE VDD3 = 3.0V IOL2 = 8mA 0.4 V VOL3 A0 to A19, CE, and OE VDD3 = 4.5V IOL3 = 8mA 0.4 V CTRL1, TEST1, TEST2 SCLK, SIN, CS, VSYNC, HSYNC, VIN = VDD1 10 µA 10 µA Input current IIH1 RST Operating current IIH2 D0 to D15 VIN = VDD3 IIL1 CTRL1, TEST1, TEST2 SCLK, SIN, CS, VSYNC, HSYNC VIN = VSS IIL2 D0 to D15 VIN = VSS IDD1 VDD1 All outputs open drain -10 µA -10 µA OSCin: 20MHz D/A converter IDD2 VDD2 D/A on IDD3 VDD3 IDD4 VDD4 CLK Clock frequency Maximum output voltage VDD2 = 3.3V V min0 Minimum output voltage VDD2 = 3.3V 0.25 mA 22 mA 10 mA 22 mA 20 MHz 1.5 V VCO on V max 25 0 V Timing Characteristics OSD Write (See figure 1.) at Ta = -40 to +85°C, VDD1 = 3.3V ± 0.3V Parameter Symbol Ratings Conditions min Minimum input pulse width Data setup time Data hold time One word write time tw(sclk) SCLK typ Unit max 200 ns 1 µs 200 ns tw(cs) CS (The period CS is high) tsu(cs) CS tsu(sin) SIN 200 ns th(cs) CS 2 µs th(sin) SIN 200 ns tword The time to write 8 bits of data 4.2 µs 1 µs twt RAM data write time No.A0569-8/106 LC74736PT Supplementary Materials tw(cs) CS tsu(cs) tw(sclk) tw(sclk) th(cs) SCLK tsu(sin) th(sin) SIN CS tword twt SCLK 0 1 5 6 7 0 1 4 5 6 7 Figure 1 OSD Serial Data Input Timing No.A0569-9/106 LC74736PT System Block Diagram VDD1 to 4 VSS1 to 4 CS SIN 16-bits latch + command decoder Serial-toparallel converter SCLK RST Horizontal direction control register Horizontal direction counter HSYNC HBLK Address control circuit VRAM Vertical direction control register Vertical direction counter VSYNC VBLK Address control circuit OE,CE External ROM control circuit A0 to 19 D0 to 15 RAM and ROM read and write control FRAM RD3 to 0 Character size control OSCin GD3 to 0 Output control circuit BD3 to 0 BLK OSCout CTRL1 Timing generator HFTOT EXTCLK OUTR D/A CPout FC BFin BFout ROUT GOUT VCO PD CP BOUT CCOMP CVREF RREF VCOR No.A0569-10/106 LC74736PT Display Control Commands The display control commands have serial input format that consists of 8-bit units transmitted LSB first. A commands consists of a command identification code in the first byte and data in the second and following bytes. Both a first byte and a second byte (16 bits) must be transmitted for each command. Commands 10, 11, 12, 6C1, and 701 set the IC to continuous write mode. (Continuous write mode is cleared by setting the CS pin high.) Display Control Command Table First byte Command COMMAND00 Second byte Command identification code data Data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 0 0 0 V14 V13 V12 V11 V10 1 0 0 0 0 0 1 0 0 0 H15 H14 H13 H12 H11 H10 1 0 0 0 0 1 0 0 0 0 0 V24 V23 V22 V21 V20 1 0 0 0 0 1 1 0 0 0 H25 H24 H23 H22 H21 H20 1 0 0 0 1 0 0 0 SV1 SV0 0 0 0 0 SH1 SH0 1 0 0 1 0 0 RM2 RM1[1] HF1 HF0 at BXS BXL BXR BXU BXD [2] CB3 CB2 CB1 CB0 CC3 CC2 CC1 CC0 [3] 0 I/E MG1 MG0 RO1 RO0 (Write address) Main 1: V COMMAND01 (Write address) Main 1: H COMMAND02 (Write address) Main 2: V COMMAND03 (Write address) Main 2: H COMMAND04 (Write address) Sub COMMAND10 (Character write) Main 1 COMMAND11 1 0 0 1 0 1 [4] 0 0 C13 C12 C11 C10 C9 C8 [5] C7 C6 C5 C4 C3 C2 C1 C0 RM2 RM1[1] HF1 HF0 at BXS BXL BXR BXU BXD [2] CB3 CB2 CB1 CB0 CC3 CC2 CC1 CC0 [3] 0 I/E MG1 MG0 RO1 RO0 (Character write) Main 2 COMMAND12 1 0 0 1 1 0 0 0 C13 C12 C11 C10 C9 C8 [5] C7 C6 C5 C4 C3 C2 C1 C0 RM2 RM1[1] 0 0 0 0 0 0 0 0 [2] 0 0 0 0 0 0 0 0 [3] 0 I/E MG1 MG0 RO1 RO0 [4] 0 C12 C11 C10 C9 C8 C1 C0 [5] 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 (System control) COMMAND21 (Display control) COMMAND22 1 0 1 0 0 0 CTB1 CTB0 [4] (Character write) Sub COMMAND20 CTB1 CTB0 1 0 CTB1 CTB0 0 C7 C6 C5 C4 C3 C2 TST TST SYS FRM CT SRM MD2 MD1 RST ERS ERS ERS ER2 ERS1 BK BK BK BK DSP DSP DSP DSP 12 02 11 01 BG GS GM2 GM1 CKP VIP HIP 0 BLOP BLO 1 0 1 0 0 0 1 1 (Screen background color) COMMAND24 (I/O polarity control 2) BLO BLO 1 0 BGC BGC BGC BGC BGC BGC T1 T0 3 2 1 0 DPM DPM DA SBG GD GD MD SEL SL 2 1 DPM DPM HC1 1 0 1 0 0 1 0 0 MRM MRM 2 (I/O polarity control 1) COMMAND23 C13 HC0 VC GD CKOP 0 Continued on next page. No.A0569-11/106 LC74736PT Continued from preceding page. First byte Command COMMAND25 Second byte Command identification code data Data 7 6 5 4 3 2 1 0 7 6 1 0 1 0 0 1 0 1 CEH SL (Output control 1) COMMAND26 1 0 1 0 0 1 1 0 (Output control 2) COMMAND27 1 0 1 0 0 1 1 1 (Horizontal display start position: screen) STP OFF TBL KBL BL BL OTM ROT DOT 2 1 0 2 OFF OFF 0 HFT HFT HFT TOK TOK TOK TOK 2 1 0 CB4 CB3 CB2 CB1 HPS HPM HPM VPG VPS VPM VPM 0 9 9 29 19 8 8 28 18 1 0 1 0 1 0 0 1 0 SVH SVH SHH SHH 0 0 ML 1 0 1 0 1 0 1 0 1 0 1 0 0 HIN HI HI VI VI 0 0 DIN D1 D0 D1 D0 1 0 1 1 0 0 0 0 VPM VPM VPM VPM VPM VPM VPM VPM 17 16 15 14 1 12 11 10 1 0 1 1 0 0 1 1 0 1 1 0 1 0 HPM HPG 1 0 1 1 0 1 1 HPM HPM 17 16 15 14 13 12 11 10 0 VPM VPM VPM VPM VPM VPM VPM VPM 27 26 25 24 23 22 21 20 1 0 1 1 1 0 0 HPM HPM HPM CH 18 HPM HPM HPM HPM HPM HPM 27 26 25 24 23 22 21 20 0 VPS VPS VPS VPS VPS VPS VPS VPS 7 6 5 4 3 2 1 0 HPS HPS HPS HPS HPS HPS HPS HPS HPS HPM HPM HPM HPM 28 HPM HPM 1 0 1 1 1 0 1 8 7 6 5 4 3 2 1 0 1 0 1 1 1 1 0 0 VPG VPG VPG VPG VPG VPG VPG VPG 7 6 5 4 3 2 1 0 1 0 1 1 1 1 1 HPG HPG HPG HPG HPG HPG HPG HPG HPG 8 7 6 5 4 3 2 1 0 (Vertical display start positions: screen) COMMAND37 0 0 (Horizontal display start position: sub) COMMAND36 LCS 1 0 (Vertical display start positions: sub) COMMAND35 LCS SP2 1 (Horizontal display start position: main 2) COMMAND34 LCS PSL 0 (Vertical display start position: main 2) COMMAND33 VI SL 1 (Horizontal display start position: main 1) COMMAND32 0 0 (Vertical display start position: main 1) COMMAND31 TOK OTM OTM 1 OFF (Display area control 1) COMMAND30 2 HF (Output control 5) COMMAND2A 3 1 (Output control 4) COMMAND29 4 OFF (Output control 3) COMMAND28 5 Continued on next page. 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First byte Command COMMAND40 Second byte Command identification code data Data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 LSZ LSZ LSZ LSZ LSZ LSZ LSZ LSZ 7 6 5 4 3 2 1 0 LSZ LSZ LSZ LSZ LSZ LSZ LSZ LSZ 15 14 13 12 11 10 9 8 LSZ SZV1 SZV0 SZH1 SZH0 (Character size control) COMMAND41 main 1 (Character size control: line setting U) COMMAND42 main 1 1 1 0 0 0 0 1 0 (Character size control: line setting D) COMMAND43 main 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 LSZ 17 16 1 1 0 0 0 1 0 0 LSZ LSZ LSZ LSZ LSZ LSZ LSZ LSZ 7 6 5 4 3 2 1 0 1 1 0 0 0 1 0 1 LSZ LSZ LSZ LSZ LSZ LSZ LSZ LSZ 15 14 13 12 11 10 9 8 1 1 0 0 0 1 1 0 0 0 0 0 0 0 LSZ LSZ 17 16 (Character size control: line setting D2) COMMAND44 main 2 (Character size control: line setting U) COMMAND45 main 2 (Character size control: line setting D) COMMAND46 main 2 (Character size control: line setting D2) COMMAND50 1 1 0 1 0 0 0 0 (BOX control U) COMMAND51 1 1 0 1 0 0 0 1 (BOX control D) COMMAND52 main 1 1 1 0 1 0 0 1 0 (BOX control: line setting U) COMMAND53 main 1 1 1 0 1 0 0 1 1 (BOX control: line setting D) COMMAND54 main 1 BXL BXL BXU BXU BXU BXU BXU BXU W1 W0 CT1 CT0 C3 C2 C1 C0 BXR BXR BXD BXD BXD BXD BXD BXD W1 W0 CT1 CT0 C3 C2 C1 C0 LBX LBX LBX LBX LBX LBX LBX LBX 7 6 5 4 3 2 1 0 LBX LBX LBX LBX LBX LBX LBX LBX 15 14 13 12 11 10 9 8 LBX 1 1 0 1 0 1 0 0 0 0 0 0 0 0 LBX 17 16 1 1 0 1 0 1 0 1 LBX LBX LBX LBX LBX LBX LBX LBX 7 6 5 4 3 2 1 0 1 1 0 1 0 1 1 0 LBX LBX LBX LBX LBX LBX LBX LBX 15 14 13 12 11 10 9 8 1 1 0 1 0 1 1 1 0 0 0 0 0 0 LBX LBX 17 16 (BOX control: line setting D2) COMMAND55 main 2 (BOX control: line setting U) COMMAND56 main 2 (BOX control: line setting D) COMMAND57 main 2 (BOX control: line setting D2) Continued on next page. No.A0569-13/106 LC74736PT Continued from preceding page. First byte Command COMMAND58 Second byte Command identification code data Data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 0 1 1 0 0 0 0 GYB GS GS GY GY GY GY CK 1 0 3 2 1 0 BXD BXU GYH BXH FCH BXC BXC BXC W W SL SL SL 3 2 1 LGY LGY LGY LGY LGY LGY LGY LGY 7 6 5 4 3 2 1 0 LGY LGY LGY LGY LGY LGY LGY LGY (Line spacing control 1) COMMAND59 1 1 0 1 1 0 0 1 (Line spacing control 2) COMMAND5A main 1 1 1 0 1 1 0 1 0 (Line spacing control: line setting U) COMMAND5B main 1 1 1 0 1 1 0 1 1 15 14 13 12 11 10 9 8 1 1 0 1 1 1 0 0 0 0 0 0 0 0 LGY LGY 17 16 1 1 0 1 1 1 0 1 LGY LGY LGY LGY LGY LGY LGY LGY 7 6 5 4 3 2 1 0 1 1 0 1 1 1 1 0 LGY LGY LGY LGY LGY LGY LGY LGY 15 14 13 12 11 10 9 8 0 0 0 0 0 0 LGY LGY 17 16 (Line spacing control: line setting U) COMMAND5C main 1 (Line spacing control: line setting D2) COMMAND5D main 2 (Line spacing control: line setting U) COMMAND5E main 2 (Line spacing control: line setting D) COMMAND5F main 2 1 1 0 1 1 1 1 1 (Line spacing control: line setting D2) COMMAND60 1 1 1 0 0 0 0 0 BLK BLK (Border control) COMMAND61 main 1 1 1 1 0 0 0 0 1 (Border control: line setting U) COMMAND62 main 1 1 1 1 0 0 0 1 0 (Border control: line setting D) COMMAND63 main 1 EGC EGC EGC EGC EGC EGC T1 T0 3 2 1 0 LFC LFC LFC LFC LFC LFC LFC LFC 7 6 5 4 3 2 1 0 LFC LFC LFC LFC LFC LFC LFC LFC 15 14 13 12 11 10 9 8 LFC 1 1 1 0 0 0 1 1 0 0 0 0 0 0 LFC 17 16 1 1 1 0 0 1 0 0 LFC LFC LFC LFC LFC LFC LFC LFC 7 6 5 4 3 2 1 0 1 1 1 0 0 1 0 1 LFC LFC LFC LFC LFC LFC LFC LFC 15 14 13 12 11 10 9 8 1 1 1 0 0 1 1 0 0 0 0 0 0 0 LFC LFC 17 16 (Border control: line setting D2) COMMAND64 main 2 (Border control: line setting U) COMMAND65 main 2 (Border control: line setting D) COMMAND66 main 2 (Border control: line setting D2) COMMAND67 1 1 1 0 0 1 1 1 (PLL control 1) COMMAND68 1 1 1 0 1 0 0 0 EVO LC ECK VCO VCS VCS OFF OFF OFF OFF 1 0 1 0 0 0 0 DIV DIV DIV DIV DIV 12 11 10 9 8 (PLL control 2) COMMAND69 1 1 1 0 1 0 0 1 (PLL control 3) COMMAND6A 1 1 1 0 1 0 1 0 DIV DIV DIV DIV DIV DIV DIV DIV 7 6 5 4 3 2 1 0 0 HD DZ DZ HR DID DID DID SL 1 0 SL 2 1 0 0 CTN CTN CTA CTA CTA CTA 1 0 3 2 1 0 (PLL control 5) COMMAND6C0 1 1 1 0 1 1 0 0 CKSL CKSL 0 (Write address) Color table COMMAND6C1 (Data write) 1 1 1 0 1 1 1 RM3[1] [2] 0 0 HFT TOK TB3 TB2 TB1 TB0 TG3 TG2 TG1 TG0 TR3 TR2 TR1 TR0 Color table Continued on next page. No.A0569-14/106 LC74736PT Continued from preceding page. First byte Command Second byte Command identification code data COMMAND700 Data 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 1 0 0 0 0 FAD FAD FRN FRN FVA FVA FVA FVA 1 0 1 0 3 2 1 0 RM3[1] D15 D14 D13 D12 D11 D10 D9 D8 [2] D7 D6 D5 D4 D3 D2 D1 D0 0 0 CKO CKO S1 S0 (character ram1) writeaddress COMMAND701 1 1 1 1 0 0 1 (character ram2) write COMMAND710 1 1 1 1 0 1 0 0 (WVGA ROM) COMMAND711 1 1 1 1 0 1 0 1 1 1 1 1 0 1 1 0 RSTB 0 VCRS VCRS (PLL control 6) COMMAND712 0 WFC WRA WRA WRA MD M2 M1 M0 CP 0 CP CP 1 0 X2 I11 I0 STB RES SCP DIV GAN GAN GAN CP CP CP ECP 2 1 0 (PLL control 7) 1 COMMAND00 (Main screen 1: horizontal write address setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 0 identification code 6 - 0 Main screen 1 memory horizontal write address setting 5 - 0 4 - 0 3 - 0 2 - 0 1 - 0 0 - 0 Sub-identification code: 0 (2) Second byte DA0 to 7 Content Register State 7 - 0 6 - 0 5 - 0 4 V14 3 Notes Function 0 Main screen 1 memory line address [MSB] 1 (0 to 11, hexadecimal) V13 0 COM24-2: Line number specification 15 lines: 0E (hexadecimal) 18 lines: 11 (hexadecimal) 1 2 V12 0 1 V11 0 1 1 0 V10 0 [LSB] 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-15/106 LC74736PT 2 COMMAND01 (Main screen 1: vertical write address setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 0 identification code 6 - 0 Main screen 1 memory vertical write address setting 5 - 0 4 - 0 3 - 0 2 - 0 1 - 1 0 - 0 Sub-identification code: 1 (2) Second byte DA0 to 7 Content Register State 7 - 0 6 - 0 5 - 0 4 H15 4 0 Main screen 1 memory character position address [MSB] 1 (0 to 21, hexadecimal) H14 0 1 3 H13 0 2 H12 0 1 H11 0 0 H10 0 [LSB] 1 Notes Function COM23-2: Character number specification 30 characters: 1D (hexadecimal) 33 characters: 20 (hexadecimal) 34 characters: 21 (hexadecimal) 1 1 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-16/106 LC74736PT 3 COMMAND02 (Main screen 2: horizontal write address setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 0 identification code 6 - 0 Main screen 2 memory horizontal write address setting 5 - 0 4 - 0 3 - 0 2 - 1 1 - 0 0 - 0 Sub-identification code: 2 (2) Second byte DA0 to 7 Content Register State 7 - 0 6 - 0 5 - 0 4 V24 3 Notes Function 0 Main screen 2 memory line address [MSB] 1 (0 to 0E, hexadecimal) V23 0 COM24-2: Line number specification 15 lines: 0E (hexadecimal) 18 lines: 11 (hexadecimal) 1 2 V22 0 1 V21 0 0 V20 0 [LSB] 1 1 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-17/106 LC74736PT 4 COMMAND03 (Main screen 2: vertical write address setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 0 identification code 6 - 0 Main screen 2 memory vertical write address setting 5 - 0 4 - 0 3 - 0 2 - 1 1 - 1 0 - 0 Sub-identification code: 3 (2) Second byte DA0 to 7 Content Register State 7 - 0 6 - 0 5 - 0 4 H25 4 0 Main screen 2 memory character position address [MSB] 1 (0 to 21, hexadecimal) H24 0 1 3 H23 0 2 H22 0 1 H21 0 0 H20 0 [LSB] 1 Notes Function COM23-3: Character number specification 30 characters: 1D (hexadecimal) 33 characters: 20 (hexadecimal) 34 characters: 21 (hexadecimal) 1 1 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-18/106 LC74736PT 5 COMMAND04 (Subscreen write address setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 0 identification code 6 - 0 Subscreen write address setting 5 - 0 4 - 0 3 - 1 2 - 0 1 - 0 0 - 0 Sub-identification code: 4 (2) Second byte DA0 to 7 Content Register State 7 6 SV1 SV0 0 Subscreen memory line address 1 0 to 3 (hexadecimal) 0 Notes Function COM29-2: Line number specification 4 lines (maximum) 1 5 - 0 4 - 0 3 - 0 2 - 0 1 SH1 0 Subscreen memory character position address 1 0 to 3 (hexadecimal) 0 SH0 0 COM29-2: Character number specification 4 characters (maximum) 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-19/106 LC74736PT 6 COMMAND10 (Main screen 1 display character data write setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 1 identification code When this command has been issued, the IC 6 - 0 Display character data write setting 5 - 0 remains in display character data write mode until the CS pin is set high. 4 - 1 3 - 0 2 - 0 1 RM2 0 1 0 RM1 0 1 Sub-identification code: 0 RM2 RM1 0 0 Mode Continuous write mode selection [1][2][3][4][5] End 0 1 [1][2][3][4][5] Continuous 1 0 [3][4][5] Continuous 1 1 [2][3][4][5] Continuous (2) Second byte-[1] DA0 to 7 Content Register State 7 HFT1 0 1 6 HFT0 0 1 5 4 3 at BXS BXL HFT1 HFT0 0 None Graphic is processed as a character. 0 1 Character only COM59-2 1 0 Character background only 1 1 Character+Character background 0 Blinking off 1 Blinking on 0 Raised 1 Recessed 0 None 1 Box displayed None BXR 0 1 Box displayed 1 BXU 0 None 1 Box displayed 0 None 1 Box displayed BXD Halftone specification 0 2 0 Notes Function Blinking specification Box specification: raised/recessed Box specification: left side Box specification: right side Box specification: upper Box specification: down *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-20/106 LC74736PT (3) Second byte-[2] DA0 to 7 Content Register State Notes Function CB3 0 Character background color specification Character background color specification [MSB] 1 0000 to 1111, or 0 to F (hexadecimal) When a character glyph is specified, 6 CB2 0 5 CB1 0 7 1 of 16 colors may be selected. 1 1 4 3 2 CB0 0 [LSB] 1 CC3 0 Character color specification Character color specification [MSB] 1 0000 to 1111, or 0 to F (hexadecimal) When a character glyph is specified, CC2 0 1 of 16 colors may be selected. 1 1 CC1 0 0 CC0 0 [LSB] 1 1 (4) Second byte-[3] DA0 to 7 Content Register State 7 - 0 6 CTB1 0 1 5 CTB0 0 1 4 3 2 I/E M/G1 M/G0 CTB1 CTB0 Color table selection 0 0 Color table number 1 0 1 Color table number 2 1 0 Color table number 3 1 1 Color table number 4 0 Character RAM (internal) 1 External ROM 0 MG1 MG0 1 0 0 Character 0 1 Graphic 1(CB, CC invalid) 1 0 0 Notes Function 1 ROM selection Character/graphic specification Graphic 2 CTB address shown with CB 1 → Chantged to CTB address shown with CC 1 1 Graphic 3 CTBNo of address shown with CB → Changed to CTBNo shown with CC1, CC0 1 ROM1 0 1 0 ROM0 0 1 ROM1 ROM0 ROM area selection 0 0 ROM area number 1 0 1 ROM area number 2 1 0 ROM area number 3 1 1 ROM area number 4 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-21/106 LC74736PT (5) Second byte-[4] DA0 to 7 Content Register State 7 - 0 6 - 0 5 C13 0 4 [MSB] 1 C12 0 Notes Function Character code specification 1 3 C11 0 2 C10 0 1 C9 0 1 1 1 0 C8 0 1 (6) Second byte-[5] DA0 to 7 Content Register State 7 C7 0 1 6 C6 0 1 5 C5 0 1 4 C4 0 1 3 C3 0 Notes Function Character code Character code specification External ROM: 16384 characters 0000 to 3FFF (hexadecimal) 0 to 16383 Character RAM (internal): QVGA mode: 0 to 3, hexadecimal, 4 characters WVGA mode: 0 hexadecimal, 1 character * Transparent character specification I/E = 0 (Internal character RAM) M/G10 = 00 (Character) Code = FF (hexadecimal) 1 2 C2 0 1 C1 0 1 1 0 C0 0 [LSB] 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-22/106 LC74736PT 7 COMMAND11 (Main screen 2 display character data write setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 1 identification code When this command has been issued, the 6 - 0 Display character data write setting 5 - 0 IC remains in display character data write mode until the CS pin is set high. 4 - 1 3 - 0 2 - 0 1 RM2 0 1 0 RM1 0 1 Sub-identification code: 1 RM2 RM1 0 0 Mode Continuous write mode selection [1][2][3][4][5] End 0 1 [1][2][3][4][5] Continuous 1 0 [3][4][5] Continuous 1 1 [2][3][4][5] Continuous (2) Second byte-[1] DA0 to 7 Content Register State 7 HFT1 0 1 6 HFT0 0 1 5 4 3 at BXS BXL HFT1 HFT0 0 None Graphic is processed as a character. 0 1 Character only COM59-2 1 0 Character background only 1 1 Character+Character background 0 Blinking off 1 Blinking on 0 Raised 1 Recessed 0 None 1 Box displayed None BXR 0 1 Box displayed 1 BXU 0 None 1 Box displayed 0 None 1 Box displayed BXD Halftone specification 0 2 0 Notes Function Blinking specification Box specification: raised/recessed Box specification: left side Box specification: right side Box specification: upper Box specification: down *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-23/106 LC74736PT (3) Second byte-[2] DA0 to 7 Content Register State Notes Function CB3 0 Character background color specification Character background color specification [MSB] 1 0000 to 1111, or 0 to F (hexadecimal) When a character glyph is specified, 6 CB2 0 5 CB1 0 7 1 of 16 colors may be selected. 1 1 4 3 2 CB0 0 [LSB] 1 CC3 0 Character color specification Character color specification [MSB] 1 0000 to 1111, or 0 to F (hexadecimal) When a character glyph is specified, CC2 0 1 of 16 colors may be selected. 1 1 CC1 0 0 CC0 0 [LSB] 1 1 (4) Second byte-[3] DA0 to 7 Content Register State 7 - 0 6 CTB1 0 1 5 CTB0 0 1 4 3 2 I/E M/G1 M/G0 CTB1 CTB0 Color table selection 0 0 Color table number 1 0 1 Color table number 2 1 0 Color table number 3 1 1 Color table number 4 0 Character RAM (internal) 1 External ROM 0 MG1 MG0 1 0 0 Character 0 1 Graphic 1 (CB, CC invalid) 1 0 0 Notes Function 1 ROM selection Character/graphic specification Graphic 2 CTB address shown with CB 1 → Changed to CTB address shown with CC. 1 1 Graphic 3 CTBNo of address shown with CB. → Changed to CTBNo shown with CC1, CC0. 1 ROM1 0 1 0 ROM0 0 1 ROM1 ROM0 ROM area selection 0 0 ROM area number 1 0 1 ROM area number 2 1 0 ROM area number 3 1 1 ROM area number 4 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-24/106 LC74736PT (5) Second byte-[4] DA0 to 7 Content Register State 7 - 0 6 - 0 5 C13 0 4 [MSB] 1 C12 0 Notes Function Character code specification 1 3 C11 0 2 C10 0 1 C9 0 1 1 1 0 C8 0 1 (6) Second byte-[5] DA0 to 7 Content Register State 7 C7 0 1 6 C6 0 1 5 C5 0 1 4 C4 0 1 3 C3 0 Notes Function Character code Character code specification External ROM: 16384 characters 0000 to 3FFF (hexadecimal) 0 to 16383 Character RAM (internal): QVGA mode: 0 to 3, hexadecimal, 4 characters WVGA mode: 0 hexadecimal, 1 character * Transparent character specification I/E = 0 (Internal character RAM) M/G10 = 00 (Character) Code = FF (hexadecimal) 1 2 C2 0 1 C1 0 1 1 0 C0 0 [LSB] 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-25/106 LC74736PT 12 COMMAND12 (Subscreen display character data write setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 1 identification code When this command has been issued, the IC 6 - 0 Display character data write setting 5 - 0 remains in display character data write mode until the CS pin is set high. 4 - 1 3 - 1 2 - 0 1 RM2 0 1 0 RM1 0 1 Sub-identification code 2 RM2 RM1 0 0 Mode [1][2][3][4][5] Continuous write mode selection End 0 1 [1][2][3][4][5] Continuous 1 0 [3][4][5] Continuous 1 1 [2][3][4][5] Continuous (2) Second byte-[1] DA0 to 7 Content Register State 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 1 - 0 0 - 0 Notes Function (3) Second byte-[2] DA0 to 7 Content Register State 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 1 - 0 0 - 0 Notes Function *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-26/106 LC74736PT (4) Second byte-[3] DA0 to 7 Content Register State 7 - 6 CTB1 0 0 1 5 CTB0 0 1 4 3 I/E M/G1 M/G0 Color table selection CTB1 CTB0 0 0 Color table number 1 0 1 Color table number 2 1 0 Color table number 3 1 1 Color table number 4 0 Character RAM (internal) 1 External ROM 0 MG1 MG0 1 2 Notes Function 0 0 0 0 1 ROM selection Graphic only Character (only when transparent character is specified.) Graphic 1 only 1 1 1 - 0 0 - 0 (5) Second byte-[4] DA0 to 7 Content Register State 7 - 0 6 - 0 5 C13 0 4 [MSB] 1 C12 0 Notes Function Character code specification 1 3 C11 0 2 C10 0 1 C9 0 1 1 1 0 C8 0 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-27/106 LC74736PT (6) Second byte-[5] DA0 to 7 Content Register State 7 C7 0 1 6 C6 0 1 5 C5 0 1 4 C4 0 1 3 C3 0 Notes Function Character code Character code specification External ROM: 16384 characters 0000 to 3FFF (hexadecimal) 0 to 16383 Character RAM (internal): QVGA mode: 0 to 3, hexadecimal, 4 characters WVGA mode: 0 hexadecimal, 1 character * Transparent character specification I/E = 0 (Internal character RAM) M/G10 = 00 (Character) Code = FF (hexadecimal) 1 2 C2 0 1 1 C1 0 0 C0 0 [LSB] 1 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-28/106 LC74736PT 9 COMMAND20 (System control setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 2 identification code 6 - 0 System control settings 5 - 1 4 - 0 3 - 0 2 - 0 1 - 0 0 - 0 Sub-identification code 0 (2) Second byte DA0 to 7 Content Register State 7 6 5 Notes Function TST 0 Normal operation Do not use test mode. This bit must always MD2 1 Test mode 2 be set to 0. TST 0 Normal operation Do not use test mode. This bit must always MD1 1 Test mode 1 be set to 0. SYS 0 RST 1 The registers are reset when the CS pin is Reset all registers (All bits set to 0.) low. The reset state is cleared when the CS pin goes high. 4 FRM 0 ERS 1 Applications must provide a wait time of Erase FontRAM (Sets all values to 00.) about 1ms. Use DSPOFF to execute this operation. 3 CT 0 ERS 1 SRM 0 ERS 1 Applications must provide a wait time of Erase the color table. (Sets all values to 00.) about 1ms. Use DSPOFF to execute this operation. 2 1 0 MRM 0 ER2 1 MRM 0 ER1 1 Applications must provide a wait time of Erase sub-RAM. (Sets all values to 00.) about 1ms. Wallpaper Use DSPOFF to execute this operation. Applications must provide a wait time of Erase main RAM. (Sets all values to 00.) about 1ms. Main screen Use DSPOFF to execute this operation. Applications must provide a wait time of Erase main RAM. (Sets all values to 00.) about 1ms. Main screen Use DSPOFF to execute this operation. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-29/106 LC74736PT 10 COMMAND21 (Display control setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 2 identification code 6 - 0 Display control 5 - 1 4 - 0 3 - 0 2 - 0 1 - 0 0 - 1 Extended command 1 identification code (2) Second byte DA0 to 7 Content Register State 7 6 BK12 BK02 Notes Function 0 BK12 BK02 Blinking period Blinking period main 2 1 0 0 1/16 Specified for screen units. 0 1 1/32 1 0 1/64 0 BK11 BK01 Blinking period Blinking period main 1 1 0 0 1/16 Specified for screen units. 0 1 1/32 1 0 1/64 0 1 5 4 BK11 BK01 0 1 3 2 1 0 DSP 0 Display off BG 1 Display on DSP 0 Display off GS 1 Display on DSP 0 Display off GM2 1 Display on DSP 0 Display off GM1 1 Display on Screen background color Subscreen (wallpaper) Main screen 2 Main screen 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-30/106 LC74736PT 11 COMMAND22 (I/O polarity control 1 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 2 identification code 6 - 0 I/O polarity control 1 5 - 1 4 - 0 3 - 0 2 - 0 1 - 1 0 - 0 Extended command 2 identification code (2) Second byte DA0 to 7 Content Register State Notes Function 7 - 0 6 BLOP 0 BLK output: positive polarity 1 BLK output: negative polarity 0 BLO210 BLK output BLK output control 0 0 0 0 Normal character.+charcter background+graphic Character, character background, and 0 0 1 Character only graphic output control. 0 1 0 Character background only Border specification is enabled when 0 1 1 Graphic only character background output is selected. 1 0 0 Character+character background only 1 0 1 Character+graphic only 1 1 0 Character background+graphic only 5 4 BLO2 BLO1 1 3 BLO0 0 1 2 CKP 0 1 Clock input: negative polarity 1 VIP 0 VSYNC input: negative polarity 1 VSYNC input: positive polarity 0 HIP Clock input: positive polarity 0 HSYNC input: negative polarity 1 HSYNC input: positive polarity BLK output polarity selection Clock input polarity selection VSYNC input polarity selection HSYNC input polarity selection *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-31/106 LC74736PT 12 COMMAND23 (Screen background color setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 2 identification code 6 - 0 Screen background color 5 - 1 4 - 0 3 - 0 2 - 0 1 - 1 0 - 1 Extended command 3 identification code (2) Second byte DA0 to 7 Content Register State 7 DPM HC1 6 5 4 3 0 HC1 0 Characters Main screen display area specification 1 0 0 30 characters (1D, hexadecimal) Horizontal direction 0 1 33 characters (20, hexadecimal) 1 0 34 characters (21, hexadecimal) DPM 0 HC0 1 BGC 0 T1 T0 Color table setting Screen background color T1 1 0 0 Color table number 1 Color table setting 0 1 Color table number 2 1 0 Color table number 3 1 1 Color table number 4 BGC 0 T0 1 BGC3 0 1 2 Notes Function BGC2 0 Screen background color 0000 to 1111 Screen background color setting 1 of 16 colors may be selected. 0 to F (hexadecimal) 1 1 BGC1 0 0 BGC0 0 1 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-32/106 LC74736PT 13 COMMAND24 (I/O polarity control 2 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 2 identification code 6 - 0 I/O polarity control 2 5 - 1 4 - 0 3 - 0 2 - 1 1 - 0 0 - 0 Extended command 4 identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 4 DPM 0 Notes Function QVGA mode (16×16 dots) Display mode selection MD 1 WVGA mode (24×32 dots) DPM 0 15 lines Mmain screen display area specification VC 1 18 lines Vertical D/A converter use/no-use selection D/A 0 D/A on SEL 1 D/A off SBG 0 Repeated display (wallpaper) Subscreen display selection SL 1 Cursor display (sprite display) COM29-2: Display area specification QVGA: Horizontal 4 characters×Vertical 4 lines (maximum) WVGA: Horizontal 2 characters×Vertical 2 lines (maximum) 3 GD2 0 1 2 GD1 0 1 1 0 GD0 CKOP GD2 1 0 0 0 Screen display [upper⇔lower] 0 Main 1, Main 2, Wallpaper 0 0 1 Main 2, Main 1, Wallpaper 0 1 0 Wallpaper, Main 1, Main 2 0 1 1 Wallpaper, Main 2, Main 1 0 1 0 0 Main 1, Wallpaper, Main 2 1 1 0 1 Main 2, Wallpaper, Main 1 0 Clock output: positive polarity 1 Clock output: negative polarity Screen display order selection Clock output polarity selection *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-33/106 LC74736PT 14 COMMAND25 (Output control 1 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 2 identification code 6 - 0 Output control 1 5 - 1 4 - 0 3 - 0 2 - 1 1 - 0 0 - 1 Extended command 5 identification code (2) Second byte DA0 to 7 Content Register State 7 CEHSL 6 TOKSL 0 Notes Function CE pin Normal operation 1 CE pin held fixed at the high level 0 Normal mode Transparent mode specification 1 Transmissive mode Specifis effective color table with COMN27-2. The color specified at address 0 in color table No. 1 is displayed in the transmissive state. 5 4 VIPSL 0 Falling edge detection Selects the detection polarity for the VSYNC 1 Rising edge detection signal. LCS 0 LC oscillator: Normal operation (H sync) LC oscillator STOP control OF2 1 LC oscillator: STOP state (OFF) When external clock is input. RSTLC also 3 OTMD1 0 1 2 OTMD0 0 1 1 0 OTMD1 OTMD0 Output 0 0 Normal 0 1 Disabled 1 0 Disabled 1 1 High-impedance state A0 to A19, CE, OE output selection LCS 0 LC oscillator: Normal operation (H sync.) LC oscillator STOP control STP 1 LC oscillator: Always STOP state Enabled when display is off LCS 0 LC oscillator: Normal operation (H sync.) LC oscillator STOP control OFF 1 LC oscillator: STOP state (OFF) When external clock is input. LCSTOP only *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-34/106 LC74736PT 15 COMMAND26 (Output control 2 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 2 identification code 6 - 0 Output control 1 5 - 1 4 - 0 3 - 0 2 - 1 1 - 1 0 - 0 Extended command 6 identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 HFT 0 HFTOT output on OFF 1 HFTOT output off=low BLK 0 BLK output on OFF 1 BLK output off=low BLD2 0 BLD2 1 1 4 BLD1 0 1 3 BLD0 Notes Function 0 HFTOT output setting BLK output setting 0 BLK output delay 0 0 0 ±0 (analog) 0 0 1 +1 0 1 0 +2 0 1 1 -1 (digital) 1 0 0 -2 BLK output delay 1 2 1 OTM2 ROT 0 Output off=Low 1 Normal output 0 OFF External ROM address, OE, CE output CLKout output output control External ROM address output setting on 1 External ROM address, OE, CE output off=low 0 DOT 0 Digital RGB output on OFF 1 Digital RGB output off=low Digital RGB output setting *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-35/106 LC74736PT 16 COMMAND27 (Output control 3 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 2 identification code 6 - 0 Output control 1 5 - 1 4 - 0 3 - 0 2 - 1 1 - 1 0 - 1 Extended command 7 identification code (2) Second byte DA0 to 7 Content Register State 7 6 - 0 HFT 0 OD2 5 4 3 HFT 0 OD1 1 HFT 0 OD0 1 Notes Function HFTOD2 1 0 0 0 0 ±0 (analog) HFTOT output delay 0 0 1 +1 0 1 0 +2 0 1 1 -1 (digital) 1 0 0 -2 TOK 0 Address 0000: Normal color Transparent color specification or specifiable CB4 1 Address 0000: Transparent color color table No. 4 COM25-2 Enabled by setting TOKSL to 1. 2 TOK 0 Address 0000: Normal color Transparent color specification or specifiable CB3 1 Address 0000: Transparent color color table No. 3 COM25-2 Enabled by setting TOKSL to 1. 1 TOK 0 Address 0000: Norrmal color Transparent color specification or specifiable CB2 1 Address 0000: Transparent color color table No. 2 COM25-2 Enabled by setting TOKSL to 1. 0 TOK 0 Address 0000: Normal color Transparent color specification or specifiable CB1 1 Address 0000: Transparent color color table No. 1 COM25-2 Enabled by setting TOKSL to 1. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-36/106 LC74736PT 17 COMMAND28 (Output control 4 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 2 identification code 6 - 0 Output control 1 5 - 1 4 - 0 3 - 1 2 - 0 1 - 0 0 - 0 Extended command 8 identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 4 3 2 1 0 Notes Function HPG 0 9 Screen background color H position msb 0 1 Screen background color H position msb 1 HPS 0 Subscreen H position msb 0 9 1 Subscreen H position msb 1 HPM2 0 Main screen 2 H position msb 0 29 1 Main screen 2 H position msb 1 HPM1 0 Main screen 1 H position msb 0 19 1 Main screen 1 H position msb 1 VPG 0 Screen background V position msb 0 8 1 Screen background V position msb 1 VPS 0 Subscreen V position msb 0 8 1 Subscreen V position msb 1 VPM2 0 Main screen 2 V position msb 0 28 1 Main screen 2 V position msb 1 VPM1 0 Main screen 1 V position msb 0 18 1 Main screen 1 V position msb 1 H position screen background color msb H position subscreen msb H position main screen 2 msb H position main screen 1 msb V position screen background color msb V position subscreen msb V position main screen 2 msb V position main screen 1 msb *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-37/106 LC74736PT 18 COMMAND29 (Output control 5 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 2 identification code 6 - 0 Output control 1 5 - 1 4 - 0 3 - 1 2 - 0 1 - 0 0 - 1 Extended command 9 identification code (2) Second byte DA0 to 7 Content Register State 7 - 6 SVH1 0 0 SVH1 SVH0 1 5 SVH0 0 1 4 SHH1 0 SHH0 0 1 Subscreen vertical direction display range WVGA selection 0 1 line - QVGA: 4 lines (maximum) 0 1 2 line - WVGA: 2 lines (maximum) 1 0 3 line 1 line 1 1 4 line 2 line SHH1 SHH0 Subscreen horizontal direction display range Display area QVGA WVGA selection 0 0 1 character - QVGA: 4 characters (maximum) 0 1 2 characters - WVGA: 2 characters (maximum) 1 0 3 characters 1 character 1 1 4 characters 2 characters 2 - 0 1 - 0 ML 0 LSB first CHG 1 MSB first 0 Display area QVGA 0 1 3 Notes Function 3-wire control transfer direction selection *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-38/106 LC74736PT 18 COMMAND2A (Display area control 1 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 2 identification code 6 - 0 Output control 1 5 - 1 4 - 0 3 - 1 2 - 0 1 - 1 0 - 0 Extended command A identification code (2) Second byte DA0 to 7 Content Register State Notes Function 7 - 0 6 HIN 0 Normal (LC oscillator control route) HSYNC input selection DIN 1 Direct taking in Direct taking-in specification (1) must be HI 0 HID1 HID0 D1 1 0 used in modes other than LC oscillator. 5 4 3 2 delay HSYNC taking in 0 ±0 (initial) Enabled when HINDIN is set to 1. 0 1 +1 1 0 +2 1 1 HI 0 D0 1 VI 0 VID1 VID0 D1 1 0 0 ±0 (initial) VI 0 0 1 +1 1 0 +2 1 1 +3 D0 1 1 - 0 0 - 0 +3 delay VSYNC taking in *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-39/106 LC74736PT 25 COMMAND30 (Main screen 1: vertical display start position setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 3 identification code 6 - 0 Main screen 1 vertical display start position setting 5 - 1 4 - 1 3 - 0 2 - 0 1 - 0 0 - 0 Extended command 0 identification code (2) Second byte DA0 to 7 Content Register State 7 VPM17 0 1 Notes Function The vertical display start position, VSM 1, is given by: 8 VSM1=1H×(Σ2 VPM1n) by the 9 bits VPM18 to VPM10. n=0 6 VPM16 Main screen 1 The vertical display start position is specified n 0 The weight of the LSB is 1H. 1 5 VPM15 0 4 VPM14 0 This setting applies in screen units. HSYNC 1 VSM1 3 VPM13 0 1 2 VPM12 0 1 1 VPM11 VSYNC 1 HSM1 Main screen display area 0 1 0 VPM10 0 (LSB) 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-40/106 LC74736PT 26 COMMAND31 (Main screen 1: horizontal display start position setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 3 identification code 6 - 0 Main screen: horizontal display start position setting 5 - 1 4 - 1 3 - 0 2 - 0 1 - 1 0 HPM18 0 Extended command 1 identification code 1 (2) Second byte DA0 to 7 7 Content Register HPM17 Notes State Function 0 The horizontal display start position, HSM1, is given by: 1 9 HSM1=1Tc×(Σ2 HPM1n)+ α specified by the 10 bits HPM19 to HPM10. n=0 6 HPM16 0 1 5 HPM15 0 1 4 HPM14 0 2 HPM13 HPM12 The weight of the LSB is 1TC. α=45Tc(QVGA) 41Tc(WVGA) This setting applies in screen units. Tc: The input clock frequency in operating mode. Setting disable range 1 3 QVGA WVGA 0 Sub H 0 character 00HEX 00HEX 1 Sub H 1 character 00 to 05HEX 00 to 15HEX (00 to 0CHEX) 0 1 Main screen 1 The horizontal display start position is n Sub H 2 characters 00 to 0DHEX 00 to 2CHEX (00 to 1CHEX) 1 HPM11 0 Sub H 3 characters 00 to 15HEX 1 Sub H 4 characters 00 to 1DHEX 0 HPM10 0 The values in parentheses apply when ROM access (LSB) 1 No. 2 and No. 3 are set. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-41/106 LC74736PT 27 COMMAND32 (Main screen 2: vertical display start position setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 3 identification code 6 - 0 Main screen 2 vertical display start position setting 5 - 1 4 - 1 3 - 0 2 - 1 1 - 0 0 - 0 Extended command 2 identification code (2) Second byte DA0 to 7 Content Register State 7 VPM27 0 1 Notes Function The vertical display start position, VSM2, is given by: 8 VSM2=1H×(Σ2 VPM2n) by the 9 bits VPM28 to VPM20. n=0 6 VPM26 Main screen 2 The vertical display start position is specified n 0 The weight of the LSB is 1H. 1 5 VPM25 0 4 VPM24 0 This setting applies in screen units. HSYNC 1 VSM2 3 VPM23 0 1 2 VPM22 0 1 1 VPM21 VSYNC 1 HSM2 Main screen display area 0 1 0 VPM20 0 (LSB) 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-42/106 LC74736PT 28 COMMAND33 (Main screen 2: horizontal display start position setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 3 identification code 6 - 0 Main screen: horizontal display start position setting 5 - 1 4 - 1 3 - 0 2 - 1 1 - 1 0 HPM28 0 Extended command 3 identification code 1 (2) Second byte DA0 to 7 7 Content Register HPM27 Notes State Function 0 The horizontal display start position, HSM2, is given by: 1 9 HSM2=1Tc×(Σ2 HPM2n)+ α specified by the 10 bits HPM29 to HPM20. n=0 6 5 HPM26 HPM25 0 α=45Tc(QVGA) 1 41Tc(WVGA) 0 Main screen 2 The horizontal display start position is n The weight of the LSB is 1TC. Tc: The input clock frequency in operating mode. This setting applies in screen units. 1 4 3 HPM24 HPM23 0 Setting disable range QVGA WVGA 1 Sub H 0 character 00HEX 00HEX 0 Sub H 1 character 00 to 05HEX 1 2 HPM22 0 1 1 0 HPM21 00 to 15HEX (00 to 0CHEX) Sub H 2 characters 00 to 0DHEX 00 to 2CHEX (00 to 1CHEX) Sub H 3 characters 00 to 15HEX 0 Sub H 4 characters 00 to 1DHEX 1 The values in parentheses apply when ROM access HPM20 0 No. 2 and No. 3 are set. (LSB) 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-43/106 LC74736PT 29 COMMAND34 (Subscreen: vertical display start position setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 3 identification code 6 - 0 Subscreen: vertical display start position setting 5 - 1 4 - 1 3 - 1 2 - 0 1 - 0 0 - 0 Extended command 4 identification code (2) Second byte DA0 to 7 Content Register State 7 VPS7 0 1 Notes Function The vertical display start position, VSS, is given by: 8 VSS=1H×(Σ2 VPSn) by the 9 bits VPS8 to VPS0. n=0 6 VPS6 Subscreen (wallpaper) The vertical display start position is specified n 0 The weight of the LSB is 1H. 1 5 VPS5 HSYNC 0 This setting applies in screen units. 4 VPS4 0 1 3 VPS3 0 1 2 VPS2 0 1 VPS1 0 VSYNC 1 VSS HSS Subscreen (wallpaper) display area 1 1 0 VPS0 0 (LSB) 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-44/106 LC74736PT 30 COMMAND35 (Subscreen: horizontal display start position setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 3 identification code 6 - 0 Subscreen: horizontal display start position setting 5 - 1 4 - 1 3 - 1 2 - 0 1 - 1 0 HPS8 0 Extended command 5 identification code 1 (2) Second byte DA0 to 7 Content Register State 7 HPS7 0 1 Notes Function The horizontal display start position, HSS, is given by: 9 HSS=1Tc×(Σ2 HPSn)+ α specified by the 9 bits HPS9 to HPS0. n=0 6 5 HPS6 HPS5 0 α=15Tc 1 Tc: The input clock frequency in operating mode. The weight of the LSB is 1TC. 0 1 4 HPS4 0 3 HPS3 0 This setting applies in screen units. Setting disable range Sub H 1 character QVGA WVGA 00 to 13HEX 00 to 22HEX 1 (00 to 1AHEX) Sub H 2 characters 00 to 1BHEX HPS2 0 1 1 HPS1 0 00 to 3AHEX (00 to 2AHEX) 1 2 Subscreen (wallpaper) The horizontal display start position is n Sub H 3 characters 00 to 23HEX Sub H 4 characters 00 to 2BHEX The values in parentheses apply when ROM access No. 2 and No. 3 are set. 1 0 HPS0 0 (LSB) 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-45/106 LC74736PT 31 COMMAND36 (Screen background color: vertical display start position setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 3 identification code 6 - 0 Screen background color: vertical display start position 5 - 1 4 - 1 3 - 1 2 - 1 1 - 0 0 - 0 setting Extended command 6 identification code (2) Second byte DA0 to 7 Content Register State 7 VPG7 0 1 Notes Function The vertical display start position, VSG, is given by: 8 VSG=1H×(Σ2 VPGn) by the 8 bits VPG8 to VPG0. n=0 6 VPG6 Screen background color The vertical display start position is specified n 0 The weight of the LSB is 1H. 1 5 VPG5 HSYNC 0 This setting applies in screen units. 1 VPG4 0 1 3 VPG3 0 1 2 VPG2 0 1 VPG1 0 VSG VSYNC 4 HSG Screen background color display area 1 1 0 VPG0 0 (LSB) 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-46/106 LC74736PT 32 COMMAND37 (Screen background color: horizontal display start position setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 3 identification code 6 - 0 Screen background color: horizontal display start 5 - 1 4 - 1 3 - 1 2 - 1 1 - 1 0 HPG8 0 position setting Extended command 7 identification code 1 (2) Second byte DA0 to 7 7 Content Register HPG7 State Function 0 The horizontal display start position, HSG, is given by: 1 9 n HSG=1Tc×(Σ2 HPGn) n=0 6 HPG6 0 Tc: The input clock frequency in operating mode. Notes Screen background color The horizontal display start position is specified by the 10 bits HPG9 to HPG0. The weight of the LSB is 1TC. 1 5 HPG5 0 This setting applies in screen units. 1 4 HPG4 0 3 HPG3 0 2 HPG2 0 1 HPG1 0 0 HPG0 0 (LSB) 1 1 1 1 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-47/106 LC74736PT 33 COMMAND40 (Character size control setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 4 identification code 6 - 1 Character size control settings 5 - 0 4 - 0 3 - 0 2 - 0 1 - 0 0 - 0 Extended command 0 identification code (2) Second byte DA0 to 7 Content Register State 7 - 0 6 - 0 5 - 0 4 - 0 3 SZV1 0 1 2 SZV0 0 1 1 SZH1 0 1 0 SZH0 0 1 Notes Function Character size Specifies the character size in the vertical 0 0 1× direction. 0 1 2× This setting applies in line units. 1 0 3× 1 1 4× SZV1 SZV0 Character size Specifies the character size in the horizontal 0 0 1× direction. 0 1 2× This setting applies in line units. 1 0 3× 1 1 4× SZH1 SZH0 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-48/106 LC74736PT 34 COMMAND41 (Character size line U control main 1 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 4 identification code 6 - 1 Character size line U control main 1 5 - 0 4 - 0 3 - 0 2 - 0 1 - 0 0 - 1 Extended command 1 identification code (2) Second byte DA0 to 7 Content Register State 7 6 LSZ7 LSZ6 0 Do not set for line 8. Character size line setting control 1 Set for line 8. Upper lines 0 Do not set for line 7. 1 Set for line 7. Do not set for line 6. 5 LSZ5 0 1 Set for line 6. 4 LSZ4 0 Do not set for line 5. 1 Set for line 5. 0 Do not set for line 4. 3 2 1 0 LSZ3 LSZ2 LSZ1 LSZ0 Notes Function 1 Set for line 4. 0 Do not set for line 3. 1 Set for line 3. 0 Do not set for line 2. 1 Set for line 2. 0 Do not set for line 1. 1 Set for line 1. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-49/106 LC74736PT 35 COMMAND42 (Character size line D control main 1 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 4 identification code 6 - 1 Character size line D control main 1 5 - 0 4 - 0 3 - 0 2 - 0 1 - 1 0 - 0 Extended command 2 identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 LSZ15 LSZ14 LSZ13 0 Do not set for line 16. Character size line setting control 1 Set for line 16. Lower lines 0 Do not set for line 15. 1 Set for line 15. 0 Do not set for line 14. 1 Set for line 14. Do not set for line 13. 4 LSZ12 0 1 Set for line 13. 3 LSZ11 0 Do not set for line 12. 1 Set for line 12. 0 Do not set for line 11. 2 1 0 LSZ10 LSZ9 LSZ8 Notes Function 1 Set for line 11. 0 Do not set for line 10. 1 Set for line 10. 0 Do not set for line 9. 1 Set for line 9. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-50/106 LC74736PT 36 COMMAND43 (Character size line D2 control main 1 setting command) (1) First byte DA0 to 7 Register Content Notes State Function 7 - 1 Command 4 identification code 6 - 1 Character size line D2 control main 1 5 - 0 4 - 0 3 - 0 2 - 0 1 - 1 0 - 1 Extended command 3 identification code (2) Second byte DA0 to 7 Register Content Notes State Function 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 1 LSZ17 0 Do not set for line 18. Character size line setting control 1 Set for line 18. Lower lines 2 0 Do not set for line 17. 1 Set for line 17. 0 LSZ16 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-51/106 LC74736PT 37 COMMAND44 (Character size line U control main 2 setting command) (1) First byte DA0 to 7 Register Content Notes State Function 7 - 1 Command 4 identification code 6 - 1 Character size line U control main 2 5 - 0 4 - 0 3 - 0 2 - 1 1 - 0 0 - 0 Extended command 4 identification code (2) Second byte DA0 to 7 Register Content Notes State 7 6 5 LSZ7 LSZ6 LSZ5 Function 0 Do not set for line 8. Character size line setting control 1 Set for line 8. Upper lines 0 Do not set for line 7. 1 Set for line 7. 0 Do not set for line 6. 1 Set for line 6. Do not set for line 5. 4 LSZ4 0 1 Set for line 5. 3 LSZ3 0 Do not set for line 4. 1 Set for line 4. 0 Do not set for line 3. 2 1 0 LSZ2 LSZ1 LSZ0 1 Set for line 3. 0 Do not set for line 2. 1 Set for line 2. 0 Do not set for line 1. 1 Set for line 1. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-52/106 LC74736PT 38 COMMAND45 (Character size line D control main 2 setting command) (1) First byte DA0 to 7 Register Content Notes State Function 7 - 1 Command 4 identification code 6 - 1 Character size line D control main 2 5 - 0 4 - 0 3 - 0 2 - 1 1 - 0 0 - 1 Extended command 5 identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 LSZ15 LSZ14 LSZ13 0 Do not set for line 16. Character size line setting control 1 Set for line 16. Lower lines 0 Do not set for line 15. 1 Set for line 15. 0 Do not set for line 14. 1 Set for line 14. Do not set for line 13. 4 LSZ12 0 1 Set for line 13. 3 LSZ11 0 Do not set for line 12. 1 Set for line 12. 0 Do not set for line 11. 2 1 0 LSZ10 LSZ9 LSZ8 Notes Function 1 Set for line 11. 0 Do not set for line 10. 1 Set for line 10. 0 Do not set for line 9. 1 Set for line 9. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-53/106 LC74736PT 39 COMMAND46 (Character size line D control main 2 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 4 identification code 6 - 1 Character size line D control main 2 5 - 0 4 - 0 3 - 0 2 - 1 1 - 1 0 - 0 Extended command 6 identification code (2) Second byte DA0 to 7 Content Register State Notes Function 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 1 LSZ17 0 Do not set for line 18. Character size line setting control 1 Set for line 18. Lower lines 2 0 Do not set for line 17. 1 Set for line 17. 0 LSZ16 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-54/106 LC74736PT 46 COMMAND50 (Box control: U setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 5 identification code 6 - 1 Box control U settings 5 - 0 4 - 1 3 - 0 2 - 0 1 - 0 0 - 0 Extended command 0 identification code (2) Second byte DA0 to 7 Content Register State 7 BXL W1 6 5 BXL 4 3 0 W1 W0 1 0 0 1 dot Dot width. This setting applies in line units. 0 1 2 dots It does not depend on the character size. 1 0 3 dots 1 1 4 dots 0 W0 1 BXU 0 CT1 BXU 1 0 CT0 1 BXU 0 C3 1 2 BXU C2 1 1 BXU 0 0 Notes Function 0 C1 1 BXU 0 C0 1 Box display: left side BXUCT1 0 Box display: upper side 0 0 Color table number 1 Color table specification 0 1 Color table number 2 This setting applies in line units. 1 0 Color table number 3 1 1 Color table number 4 Box display: upper side color specification Box display: upper side 0000 to 1111 Color specification 0 to F (hexadecimal) This setting applies in line units. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-55/106 LC74736PT 47 COMMAND51 (Box control: D setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 5 identification code 6 - 1 Box control D settings 5 - 0 4 - 1 3 - 0 2 - 0 1 - 0 0 - 1 Extended command 1 identification code (2) Second byte DA0 to 7 Content Register State 7 BXR W1 6 5 BXR 4 3 0 W1 W0 1 0 0 1 dot Dot width. This setting applies in line units. 0 1 2 dots It does not depend on the character size. 1 0 3 dots 1 1 4 dots 0 W0 1 BXD 0 CT1 BXD 1 0 CT0 1 BXD 0 C3 1 2 BXD C2 1 1 BXD 0 0 Notes Function 0 C1 1 BXD 0 C0 1 Box display: right side BXDCT1 0 Box display: lower side 0 0 Color table number 1 Color table specification 0 1 Color table number 1 This setting applies in line units. 1 0 Color table number 3 1 1 Color table number 4 Box display: lower side color specification Box display: lower side 0000 to 1111 Color specification 0 to F (hexadecimal) This setting applies in line units. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-56/106 LC74736PT 48 COMMAND52 (Box control: U line main 1 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 5 identification code 6 - 1 Box control U line main 1 setting 5 - 0 4 - 1 3 - 0 2 - 0 1 - 1 0 - 0 Extended command 2 identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 LBX7 LBX6 LBX5 0 Do not set for line 8. Box control line setting control 1 Set for line 8. Upper lines 0 Do not set for line 7. 1 Set for line 7. 0 Do not set for line 6. 1 Set for line 6. Do not set for line 5. 4 LBX4 0 1 Set for line 5. 3 LBX3 0 Do not set for line 4. 1 Set for line 4. 0 Do not set for line 3. 2 1 0 LBX2 LBX1 LBX0 Notes Function 1 Set for line 3. 0 Do not set for line 2. 1 Set for line 2. 0 Do not set for line 1. 1 Set for line 1. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-57/106 LC74736PT 49 COMMAND53 (Box control: D line main 1 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 5 identification code 6 - 1 Box control D line main 1 setting 5 - 0 4 - 1 3 - 0 2 - 0 1 - 1 0 - 1 Extended command 3 identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 LBX15 LBX14 LBX13 0 Do not set for line 16. Box control line setting control 1 Set for line 16. Lower lines 0 Do not set for line 15. 1 Set for line 15. 0 Do not set for line 14. 1 Set for line 14. Do not set for line 13. 4 LBX12 0 1 Set for line 13. 3 LBX11 0 Do not set for line 12. 1 Set for line 12. 0 Do not set for line 11. 2 1 0 LBX10 LBX9 LBX8 Notes Function 1 Set for line 11. 0 Do not set for line 10. 1 Set for line 10. 0 Do not set for line 9. 1 Set for line 9. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-58/106 LC74736PT 50 COMMAND54 (Box control: D2 line main 1 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 5 identification code 6 - 1 Box control D2 line main 1 setting 5 - 0 4 - 1 3 - 0 2 - 1 1 - 0 0 - 0 Extended command 4 identification code (2) Second byte DA0 to 7 Content Register State Notes Function 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 1 LBX17 0 Do not set for line 18. Box control line setting control 1 Set for line 18. Lower lines 0 Do not set for line 17. 1 Set for line 17. 0 LBX16 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-59/106 LC74736PT 51 COMMAND55 (Box control: U line main 2 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 5 identification code 6 - 1 Box control U line main 2 setting 5 - 0 4 - 1 3 - 0 2 - 1 1 - 0 0 - 1 Extended command 5 identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 LBX7 LBX6 LBX5 0 Do not set for line 8. Box control line setting control 1 Set for line 8. Upper lines 0 Do not set for line 7. 1 Set for line 7. 0 Do not set for line 6. 1 Set for line 6. Do not set for line 5. 4 LBX4 0 1 Set for line 5. 3 LBX3 0 Do not set for line 4. 1 Set for line 4. 0 Do not set for line 3. 2 1 0 LBX2 LBX1 LBX0 Notes Function 1 Set for line 3. 0 Do not set for line 2. 1 Set for line 2. 0 Do not set for line 1. 1 Set for line 1. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-60/106 LC74736PT 52 COMMAND56 (Box control: D line main 2 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 5 identification code 6 - 1 Box control D line main 2 setting 5 - 0 4 - 1 3 - 0 2 - 1 1 - 1 0 - 0 Extended command 6 identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 LBX15 LBX14 LBX13 0 Do not set for line 16. Box control line setting control 1 Set for line 16. Lower lines 0 Do not set for line 15. 1 Set for line 15. 0 Do not set for line 14. 1 Set for line 14. Do not set for line 13. 4 LBX12 0 1 Set for line 13. 3 LBX11 0 Do not set for line 12. 1 Set for line 12. 0 Do not set for line 11. 2 1 0 LBX10 LBX9 LBX8 Notes Function 1 Set for line 11. 0 Do not set for line 10. 1 Set for line 10. 0 Do not set for line 9. 1 Set for line 9. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-61/106 LC74736PT 53 COMMAND57 (Box control: D line main 2 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 5 identification code 6 - 1 Box control D2 line main 2 setting 5 - 0 4 - 1 3 - 0 2 - 1 1 - 1 0 - 1 Extended command 7 identification code (2) Second byte DA0 to 7 Content Register State Notes Function 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 1 LBX17 0 Do not set for line 18. Box control line setting control 1 Set for line 18. Lower lines 2 0 Do not set for line 17. 1 Set for line 17. 0 LBX16 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-62/106 LC74736PT 54 COMMAND58 (Line spacing control 1 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 5 identification code 6 - 1 Line spacing control 1 setting 5 - 0 4 - 1 3 - 1 2 - 0 1 - 0 0 - 0 Extended command 8 identification code (2) Second byte DA0 to 7 Content Register State Notes Function 7 0 0 6 GYB 0 Line spacing basic clock: 1V CK 1 Line spacing basic clock: Depending on the character GS1 0 Line spacing basic unit (clock) setting size 5 1 4 GS0 0 1 GS1 GS0 Character Graphic Line spacing mode setting 0 0 Transparent Transparent This setting applies in line units 0 1 Transparent Transparent 1 0 Char. bkg. color CB specified color 1 1 Transparent Transparent ±1 (char. bkg color) ±1 (CB specified color) (Border enabled) 3 2 GY3 GY2 0 GY3 2 1 0 Line spacing (×H) Line spacing dot number setting 1 0 0 0 0 0 This setting applies in line units of 1H 0 0 0 1 -1 (upper) +1 (lower) 0 0 1 0 -1 +2 0 0 1 1 -1 +3 0 0 1 0 0 -1 +4 1 0 1 0 1 -1 +5 0 0 1 1 0 -1 +6 0 1 1 1 -1 +7 1 0 0 0 -1 +8 1 0 0 1 -1 +9 1 0 1 0 -1 +10 1 0 1 1 -1 +11 1 1 0 0 -1 +12 1 1 0 1 -1 +13 1 1 1 0 -1 +14 1 1 1 1 -1 +15 0 1 1 0 GY1 GY0 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-63/106 LC74736PT 55 COMMAND59 (Line spacing control 2 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 5 identification code 6 - 1 Line spacing control 2 setting 5 - 0 4 - 1 3 - 1 2 - 0 1 - 0 0 - 1 Extended command 9 identification code (2) Second byte DA0 to 7 Content Register State 7 Notes Function BXW 0 Box display: lower side is 1 dot Box display D 1 Box display: lower side is 2 dots Lower side. This setting applies in line units. BXW 0 Box display: upper side is 1 dot Box display U 1 Box display: upper side is 2 dots Upper side. This setting applies in line units. (Invalid when line spacing is specified.) Depending on the character size Depending on the character size 6 5 GYHSL 0 Normal display Line spacing area when halftone is specified 1 Line spacing area: halftone This setting applies in line units. 0 Normal display Box area when halftone is specified 1 Box area: halftone This setting applies in line units Transparent is supported except for 00. 4 3 2 BXHSL FCHSL BXC3 0 Depending on the character Border area when halftone is specified 1 Depending on the character background This setting applies in line units 0 Displayed in upper part of character lower line spacing Box upper and lower display control 2 1 Displayed in lower part of character lower line spacing Valid when line spacing is specified. 0 Inside the character range (V1&V16 dots) Box upper and lower display control 1 1 Outside the character range (line spacing area): Valid This setting applies in line units This setting applies in line units 1 BXC2 only when line spacing is specified. 0 BXC1 0 Inside the character range Box left and ight display control 1 Outside the character range This setting applies in line units *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-64/106 LC74736PT 56 COMMAND5A (Line spacing control: U line main 1 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 5 identification code 6 - 1 Control the line spacing control line setting U main 1 5 - 0 4 - 1 3 - 1 2 - 0 1 - 1 0 - 0 Extended command A identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 LGY7 LGY6 LGY5 0 Do not set for line 8. Control the line spacing control line setting 1 Set for line 8. Upper lines 0 Do not set for line 7. 1 Set for line 7. 0 Do not set for line 6. 1 Set for line 6. Do not set for line 5. 4 LGY4 0 1 Set for line 5. 3 LGY3 0 Do not set for line 4. 1 Set for line 4. 0 Do not set for line 3. 2 1 0 LGY2 LGY1 LGY0 Notes Function 1 Set for line 3. 0 Do not set for line 2. 1 Set for line 2. 0 Do not set for line 1. 1 Set for line 1. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-65/106 LC74736PT 57 COMMAND5B (Line spacing control: D line main 1 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 5 identification code 6 - 1 Control the line spacing control line setting D main 1 5 - 0 4 - 1 3 - 1 2 - 0 1 - 1 0 - 1 Extended command B identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 LGY15 LGY14 LGY13 0 Do not set for line 16. Control the line spacing control line setting 1 Set for line 16. Lower lines 0 Do not set for line 15. 1 Set for line 15. 0 Do not set for line 14. 1 Set for line 14. Do not set for line 13. 4 LGY12 0 1 Set for line 13. 3 LGY11 0 Do not set for line 12. 1 Set for line 12. 0 Do not set for line 11. 2 1 0 LGY10 LGY9 LGY8 Notes Function 1 Set for line 11. 0 Do not set for line 10. 1 Set for line 10. 0 Do not set for line 9. 1 Set for line 9. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-66/106 LC74736PT 58 COMMAND5C (Line spacing control: D line main 1 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 5 identification code 6 - 1 Control the line spacing control line setting D main 1 5 - 0 4 - 1 3 - 1 2 - 1 1 - 0 0 - 0 Extended command C identification code (2) Second byte DA0 to 7 Content Register State Notes Function 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 1 LGY17 0 Do not set for line 18. Control the line spacing control line setting 1 Set for line 18. Lower lines 2 0 Do not set for line 17. 1 Set for line 17. 0 LGY16 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-67/106 LC74736PT 59 COMMAND5D (Line spacing control: U line main 2 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 5 identification code 6 - 1 Control the line spacing control line setting U main 2 5 - 0 4 - 1 3 - 1 2 - 1 1 - 0 0 - 1 Extended command D identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 LGY7 LGY6 LGY5 0 Do not set for line 8. Control the line spacing control line setting 1 Set for line 8. Upper lines 0 Do not set for line 7. 1 Set for line 7. 0 Do not set for line 6. 1 Set for line 6. Do not set for line 5. 4 LGY4 0 1 Set for line 5. 3 LGY3 0 Do not set for line 4. 1 Set for line 4. 0 Do not set for line 3. 2 1 0 LGY2 LGY1 LGY0 Notes Function 1 Set for line 3. 0 Do not set for line 2. 1 Set for line 2. 0 Do not set for line 1. 1 Set for line 1. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-68/106 LC74736PT 60 COMMAND5E (Line spacing control: D line main 2 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 5 identification code 6 - 1 Control the line spacing control line setting D main 2. 5 - 0 4 - 1 3 - 1 2 - 1 1 - 1 0 - 0 Extended command E identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 LGY15 LGY14 LGY13 0 Do not set for line 16. Control the line spacing control line setting 1 Set for line 16. Lower lines 0 Do not set for line 15. 1 Set for line 15. 0 Do not set for line 14. 1 Set for line 14. Do not set for line 13. 4 LGY12 0 1 Set for line 13. 3 LGY11 0 Do not set for line 12. 1 Set for line 12. 0 Do not set for line 11. 2 1 0 LGY10 LGY9 LGY8 Notes Function 1 Set for line 11. 0 Do not set for line 10. 1 Set for line 10. 0 Do not set for line 9. 1 Set for line 9. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-69/106 LC74736PT 61 COMMAND5F (Line spacing control: D line main 2 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 5 identification code 6 - 1 Control the line spacing control line setting D main 2. 5 - 0 4 - 1 3 - 1 2 - 1 1 - 1 0 - 1 Extended command F identification code (2) Second byte DA0 to 7 Content Register State Notes Function 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 1 LGY17 0 Do not set for line 18. Control the line spacing control line setting 1 Set for line 18. Lower lines 0 Do not set for line 17. 1 Set for line 17. 0 LGY16 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-70/106 LC74736PT 62 COMMAND60 (Border control setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 6 identification code 6 - 1 Border control setting 5 - 1 4 - 0 3 - 0 2 - 0 1 - 0 0 - 0 Extended command 0 identification code (2) Second byte DA0 to 7 Content Register State 7 BLK1 0 Border mode specification Border mode specification 0 0 Normal display This setting applies in line units. 0 1 Border 1 0 Shadow 1 (lower side) 1 1 Shadow 2 (lower and right sides) 0 EGCT1 0 1 0 0 Color table number 1 Color table specification 0 1 Color table number 2 This setting applies in line units. 1 0 Color table number 3 1 1 Color table number 4 1 6 BLK0 0 1 5 EG CT1 4 3 EG 0 CT0 1 EG 0 C3 1 2 EG C2 1 1 EG 0 0 Notes Function 0 C1 1 EG 0 C0 1 BLK1 BLK0 Border display Border display: color specification Border display 0000 to 1111 color specification 0 to F (hexadecimal) This setting applies in line units. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-71/106 LC74736PT 63 COMMAND61 (Border control U line main 1 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 6 identification code 6 - 1 Border line setting U main 1 control 5 - 1 4 - 0 3 - 0 2 - 0 1 - 0 0 - 1 Extended command 1 identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 LFC7 LFC6 LFC5 0 Do not set for line 8. Border control line settings control main 1 1 Set for line 8. Upper lines 0 Do not set for line 7. 1 Set for line 7. 0 Do not set for line 6. 1 Set for line 6. Do not set for line 5. 4 LFC4 0 1 Set for line 5. 3 LFC3 0 Do not set for line 4. 1 Set for line 4. 0 Do not set for line 3. 2 1 0 LFC2 LFC1 LFC0 Notes Function 1 Set for line 3. 0 Do not set for line 2. 1 Set for line 2. 0 Do not set for line 1. 1 Set for line 1. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-72/106 LC74736PT 64 COMMAND62 (Border control D line main 1 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 6 identification code 6 - 1 Border line setting D main 1 control 5 - 1 4 - 0 3 - 0 2 - 0 1 - 1 0 - 0 Extended command 2 identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 LFC15 LFC14 LFC13 0 Do not set for line 16. Border control line settings control main 1 1 Set for line 16. Lower lines 0 Do not set for line 15. 1 Set for line 15. 0 Do not set for line 14. 1 Set for line 14. Do not set for line 13. 4 LFC12 0 1 Set for line 13. 3 LFC11 0 Do not set for line 12. 1 Set for line 12. 0 Do not set for line 11. 2 1 0 LFC10 LFC9 LFC8 Notes Function 1 Set for line 11. 0 Do not set for line 10. 1 Set for line 10. 0 Do not set for line 9. 1 Set for line 9. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-73/106 LC74736PT 65 COMMAND63 (Border control D line main 1 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 6 identification code 6 - 1 Border line setting D main 1 control 5 - 1 4 - 0 3 - 0 2 - 0 1 - 1 0 - 1 Extended command 3 identification code (2) Second byte DA0 to 7 Content Register State Notes Function 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 1 LFC17 0 Do not set for line 18. Border control line settings control main 1 1 Set for line 18. Lower lines 0 Do not set for line 17. 1 Set for line 17. 0 LFC16 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-74/106 LC74736PT 66 COMMAND64 (Border control U line main 2 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 6 identification code 6 - 1 Border line setting U main 2 control 5 - 1 4 - 0 3 - 0 2 - 1 1 - 0 0 - 0 Extended command 4 identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 LFC7 LFC6 LFC5 0 Do not set for line 8. Border control line settings control main 2 1 Set for line 8. Upper lines 0 Do not set for line 7. 1 Set for line 7. 0 Do not set for line 6. 1 Set for line 6. Do not set for line 5. 4 LFC4 0 1 Set for line 5. 3 LFC3 0 Do not set for line 4. 1 Set for line 4. 0 Do not set for line 3. 2 1 0 LFC2 LFC1 LFC0 Notes Function 1 Set for line 3. 0 Do not set for line 2. 1 Set for line 2. 0 Do not set for line 1. 1 Set for line 1. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-75/106 LC74736PT 67 COMMAND65 (Border control D line main 2 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 6 identification code 6 - 1 Border line setting D main 2 control 5 - 1 4 - 0 3 - 0 2 - 1 1 - 0 0 - 1 Extended command 5 identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 LFC15 LFC14 LFC13 0 Do not set for line 16. Border control line settings control main 2 1 Set for line 16. Lower lines 0 Do not set for line 15. 1 Set for line 15. 0 Do not set for line 14. 1 Set for line 14. Do not set for line 13. 4 LFC12 0 1 Set for line 13. 3 LFC11 0 Do not set for line 12. 1 Set for line 12. 0 Do not set for line 11. 2 1 0 LFC10 LFC9 LFC8 Notes Function 1 Set for line 11. 0 Do not set for line 10. 1 Set for line 10. 0 Do not set for line 9. 1 Set for line 9. *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-76/106 LC74736PT 68 COMMAND66 (Border control D line main 2 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 6 identification code 6 - 1 Border line setting D main 2 control 5 - 1 4 - 0 3 - 0 2 - 1 1 - 1 0 - 0 Extended command 6 identification code (2) Second byte DA0 to 7 Content Register State Notes Function 7 - 0 6 - 0 5 - 0 4 - 0 3 - 0 2 - 0 1 LFC17 0 Do not set for line 18. Border control line settings control main 2 1 Set for line 18. Lower lines 0 Do not set for line 17. 1 Set for line 17. 0 LFC16 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-77/106 LC74736PT 69 COMMAND67 (PLL control 1 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 6 identification code 6 - 1 PLL control 1 5 - 1 4 - 0 3 - 0 2 - 1 1 - 1 0 - 1 Extended command 7 identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 4 3 2 1 0 Notes Function EVO 0 External VCO on Oscillator-related control OFF 1 External VCO off Initial LC oscillation LC 0 LC oscillator on OFF 1 LC oscillatior off ECK 0 External clock on OFF 1 External clock off VCO 0 VCO oscillator on OFF 1 VCO oscillator off VCO 0 VCOSL1 0 SL1 1 VCO selection 0 0 Internal VCO 1/1 Clock selection required 0 1 Internal VCO 1/2 CKSL = 10 1 0 Internal VCO 1/4 External VCO VCO 0 SL0 1 1 1 CKSL 0 CKSL1 0 1 1 0 0 CKSL 0 0 1 Clock selection LC 0 1 External clock 1 0 Internal VCO (PLL) or external VCO *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-78/106 LC74736PT 70 COMMAND68 (PLL control 2 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 6 identification code 6 - 1 PLL control 2 5 - 1 4 - 0 3 - 1 2 - 0 1 - 0 0 - 0 Extended command 8 identification code (2) Second byte DA0 to 7 Content Register State 7 - 0 6 - 0 5 - 0 4 DIV 0 12 1 3 2 1 DIV 0 11 1 DIV 0 10 1 DIV 0 9 Notes Function PLL-circuit frequency division ratio setting 1 1 0 DIV 0 8 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-79/106 LC74736PT 71 COMMAND69 (PLL control 3 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 6 identification code 6 - 1 PLL control 3 5 - 1 4 - 0 3 - 1 2 - 0 1 - 0 0 - 1 Extended command 9 identification code (2) Second byte DA0 to 7 Register Content State 7 6 5 4 3 2 1 0 DIV 0 7 1 DIV 0 6 1 DIV 0 5 1 DIV 0 4 1 DIV 0 3 1 DIV 0 2 1 DIV 0 1 1 DIV 0 0 1 Notes Function 12 PLL-circuit frequency division ratio setting n=0 Initial values: N2=Σ2nDIVn 27BHEX N2: 48 to 8196 30 to 1FFF (hexadecimal) FVCO = fH×N2 VCO oscillation frequency fH = 15.734kHz FVCO = 10MHz Horizontal frequency input *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-80/106 LC74736PT 72 COMMAND6A (PLL control 5 setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 6 identification code 6 - 1 PLL control 5 5 - 1 4 - 0 3 - 1 2 - 0 1 - 1 0 - 0 Extended command A identification code (2) Second byte DA0 to 7 Content Register State 7 6 5 4 - Notes Function 0 HD 0 HD (AFC) H sync signal switch at AFC SEL 1 HIN (input) Enabled when Com67-2 CKSL is set to 10. DZ1 0 DZ1 DZ0 1 0 0 DZA 0 1 DZB 0.5ns 1 0 DZC 2.5ns DZ0 0 Dead zone specification 0.0ns 1 3 2 0 HREF (sync) SL 1 HREF (directly) DID 0 DID2 1 0 Frequency division ratio (N1) Dot clock frequency division ratio 1 0 0 0 1/1 specification 0 0 1 1/2 0 1 0 1/3 0 1 1 1/4 1 0 0 1/6 2 1 0 HREF selection HREF DID 0 1 1 DID 0 0 1 FDOT = FVCO×N1 Dot clock VCO oscillation frequency *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-81/106 LC74736PT 73 COMMAND6C0 (Color table write address setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 6 identification code 6 - 1 Color table write address setting 5 - 1 4 - 0 3 - 1 2 - 1 1 - 0 0 - 0 Sub-identifier code CO (2) Second byte DA0 to 7 Content Register State 7 - 6 - 5 CTN1 0 1 4 CTN0 0 1 3 Notes Function CTA3 0 (MSB) 1 2 CTA2 0 1 CTA1 CTN1 CTN0 Color table selection 0 0 Color table number 1 0 1 Color table number 2 1 0 Color table number 3 1 1 Color table number 4 Color table address Address of the color tables 0 to 15 0 to F (hexadecimal) 16 values 1 0 1 0 CTA0 0 (LSB) 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-82/106 LC74736PT 74 COMMAND6C1 (Color table data write setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 6 identification code When this command has been issued, the 6 - 1 Color table write setting 5 - 1 IC remains in display character data write mode until the CS pin is set high. 4 - 0 3 - 1 2 - 1 1 - 1 0 RM3 Sub-identifier code C1 0 RM3 1 0 [1][2] End Mode 1 [1][2] Continuous Continuous write mode selection (2) Second byte-[1] DA0 to 7 Content Register State 7 - 0 6 - 0 5 HFT 4 3 2 TOK TB3 TB2 0 Halftone: off 1 Halftone: on (HFTOT output is high.) 0 Color 1 Transparent (BLK output: low) 0 Color table 1 B output 0 Notes Function Color table setting B 0000 to 1111 0 to F (hexadecimal) 1 1 TB1 0 1 0 TB0 0 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-83/106 LC74736PT (3) Second byte-[2] DA0 to 7 Content Register State 7 6 TG3 TG2 0 Color table 1 G output 0 Notes Function Color table setting G 0000 to 1111 0 to F (hexadecimal) 1 5 TG1 0 1 4 TG0 0 1 3 2 TR3 TR2 0 Color table 1 R output 0 Color table setting R 0000 to 1111 0 to F (hexadecimal) 1 1 TR1 0 1 0 TR0 0 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. When transparent is selected, the BLK output is set to the low level. (Transparent state) The RGB outputs are values from the color table. The transparent specification is best for color table 1, address 0000. Since the data is set to all zeros by a RAM clear operation, the RGB output will be 000 (black) and the BLK output will be 1. Transparent is specified by setting the TOK bit to 1. (The BLK output will go to the low level.) No.A0569-84/106 LC74736PT 75 COMMAND700 (Character RAM write address setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 7 identification code 6 - 1 Character RAM write address setting 5 - 1 4 - 1 3 - 0 2 - 0 1 - 0 0 - 0 Sub-identifier code 000 (2) Second byte DA0 to 7 Content Register State 7 6 FAD1 FAD0 Notes Function 0 QVGA mode Character RAM 1 Character RAM address QVGA: address 0 0 to 3 WVGA: PNo. 0 to 3 (hexadecimal) 1 WVGA mode PNo. 0 to 3 P1 to P4 5 FRN1 0 1 4 FRN0 0 ROM No.1 to 4 0 to 3 Character RAM ROM No. 0 to 3 (hexadecimal) No.1 to No.4 1 3 2 FVA3 0 (MSB) 1 FVA2 0 Character RAM V dot addresses 0 to 15 Character RAM V dot address 0 to F (hexadecimal) 1 1 FVA1 0 0 FVA0 0 (LSB) 1 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-85/106 LC74736PT 76 COMMAND701 (Character RAM data write setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 7 identification code When this command has been issued, the 6 - 1 Character RAM data write address setting 5 - 1 IC remains in display character data write mode until the CS pin is set high. 4 - 1 3 - 0 2 - 0 1 - 1 0 RM3 Sub-identifier code 001 0 RM3 1 0 [1][2] End Mode 1 [1][2] Continuous Continuous write mode selection (2) Second byte-[1] DA0 to 7 Content Register State 7 6 D15 D14 Notes Function 0 Character RAM write data 1 D15 to D0 Character RAM write data 0 1 5 D13 0 1 4 D12 3 D11 0 1 0 1 2 D10 0 1 1 D9 0 D8 0 1 0 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-86/106 LC74736PT (3) Second byte-[2] DA0 to 7 Content Register State 7 D7 Notes Function 0 Character RAM write data 1 6 D6 5 D5 0 1 0 1 4 D4 0 1 3 D3 2 D2 0 1 0 1 1 D1 0 1 0 D0 0 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-87/106 LC74736PT 77 COMMAND710 (WVGA: ROM access setting command) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 7 identification code 6 - 1 WVGA ROM access setting 5 - 1 4 - 1 3 - 0 2 - 1 1 - 0 0 - 0 Sub-identifier code 0100 (2) Second byte DA0 to 7 Content Register State 7 0 6 5 4 0 CKOS1 CKOS0 0 CKOS1 0 1 0 0 0 1 3 Notes Function WFCMD CLKout output selection CLK 0 1 PHASECP(HD1BFQ) 1 0 NCHCP 1 1 PCHCP 0 No border WVGA mode 1 Border (displayed for each upper and lower 1V) Specifies border display when ROM access 0 When WRAM210 DCLK=33.3MHz WVGA mode 1 • No.1 3CLK = 90ns ROM access specification mode is set to 011 or 100. 2 1 WRAM2 WRAM1 0 000 Main 1 only (Main 2 display off) 1 0 WRAM0 001 0 Main 2 only (Main 1 display off) because box is displayed 1 • No.2 2CLK 60ns Main 1 Main 2 010 Character Character 011 Graphic Character HPM1≤HPM2 * The character has no border. 100 Character Graphic HPM1≥HPM2 * The character has no border. • No.3 1CLK = 30ns 101 Equivalent to QVGA (external ROM only) *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-88/106 LC74736PT 78 COMMAND711 (PLL setting command 6) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 7 identification code 6 - 1 PLL setting command 6 5 - 1 4 - 1 3 - 0 2 - 1 1 - 0 0 - 1 Sub-identifier code 0101 (2) Second byte DA0 to 7 Content Register State Notes Function 7 RSETB 0 VCOR: Internal RSETB"H" 1 VCOR: External "L" 6 - 0 5 VCR 0 S1 4 1 VCOR selection RSET0 1 2 Internal VCOR value setting 0 0 5.6K 1 1 0 Large resistance → low gain 0 1 6.6K 1 0 0 1 0 7.6K 0 0 0 1 1 4.6K 1 1 1 VCRS1 VCRS0 VCR 0 S0 1 CPI 0 The following set current ×1 X2 1 The following set current ×3 2 - 0 1 CPI 0 CPIS1 CPIS0 CPIS0 1 2 S1 1 0 0 40µA 0 0 0 CPI 0 0 1 44µA 1 0 0 1 0 52µA 0 1 0 1 1 60µA 0 0 1 3 0 S0 1 CP current value setting 2 CP current value setting 1 *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-89/106 LC74736PT 79 COMMAND712 (PLL setting command 7) (1) First byte DA0 to 7 Content Register State Notes Function 7 - 1 Command 7 identification code 6 - 1 Display character data write setting 5 - 1 4 - 1 3 - 0 2 - 1 1 - 1 0 - 0 Sub-identifier code 0110 (2) Second byte DA0 to 7 Content Register State Notes Function 7 - 0 6 STYB 0 Normal operation: STYB"H" CP 1 CP, VCO standby: PD0 = "Z" 5 RESETBCP 0 Normal operation: RESETB"H" 1 PD reset: PD0 = "Z" 4 SCP1 0 CP enable: SCP1"H" CP 1 CP disable 3 2 DIV 0 Normal operation: DIVENB"H" 1 Frequency divider reset GAIN 0 1 1 GAIN 0 1 1 0 GAIN 0 0 1 GAIN Fmin PD reset setting CP control ENB 2 CP, VCO standby setting Frequency divider control Fmax Gain[MHz] 2 1 0 0 0 0 7 40 20/V 0 0 1 7 -20% -22.5% 0 1 0 -20% 40 +2.5% 0 1 1 -20% -20% -20% 1 0 0 +20% +10% +8.75% 1 0 1 +20% -10% -13.75% 1 1 0 7 +10% +11.25% 1 1 1 7 -10% +11.25% VCO adjustment *: This resistor is set to the all bits zero state when the IC is reset by the RST pin. No.A0569-90/106 LC74736PT Display Structure The display screen consists of a 34-character×18-line grid (maximum). • QVGA mode (16×16 dot characters) QVGA panel (480×234) 30-character×15-line • WVGA mode (24×32 dot characters) WVGA panel (800×480) 33-character×15-line Up to a maximum of 612 characters can be displayed. If the character size is increased, the number of characters that can be displayed will decrease to be fewer than 612 characters. Display memory is addressed by specifying a line address (00 to 17 (hexadecimal) and a character position address (00 to 32 (hexadecimal)). Display memory is addressed by specifying a line address (00 to 11 (hexadecimal) and a character position address (00 to 21 (hexadecimal)). Display structure (Display memory address): 34 characters×18 lines (maximum) 00 00 33 21 No.A0569-91/106 LC74736PT Operational Description 1. Command transfer method 1.1 Overview (1) Commands are transferred in 8-bit units, LSB first. Always send a first byte and a second byte (16 bits). (2) COMMAND10 (Main screen 1 RAM write) COMMAND11 (Main screen 2 RAM write) COMMAND12 (Subscreen write) COMMNAD6C1 (Color table write) COMMAND701 (Character RAM write) is locked in continuous write mode when a continuous mode is specified (RM2, 1 RM3). (Continuous mode is cleared by setting the CS pin high.) 1.2 Writing Data to VRAM (1) Write start address specification Write start address is set using: COMMAND00, COMMAND01 (Main screen 1) COMMAND02, COMMAND03 (Main screen 2) COMMAND04 (Subscreen) V4 to V0: Vertical direction; H5 to H0: Horizontal direction (2) Data write Continuous write mode differs depending on the write mode specification. (RM1, RM2) 1. Normal (RM2 = 0, RM1 = 0: initial state) *Continuous mode not used* -- COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-5 command wait state -2. Write continuous (RM2 = 0, RM1 = 1): Mode 2 COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-5 3. Write continuous (RM2 = 1, RM1 = 0): Mode 3 COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-5 10-2-3 10-2-4 10-2-5 4. Write continuous (RM2 = 1, RM1 = 1): Mode 4 COM10-1 10-2-1 10-2-2 10-2-3 10-2-4 10-2-5 10-2-2 10-2-3 10-2-4 10-2-5 *: In modes 2, 3, and 4, the IC remains locked in continuous write mode until the CS pin is set high. • The write address is automatically incremented. • The write address is retained unless the IC is reset or a new write address is issued. No.A0569-92/106 LC74736PT 1.3 Color Table write (1) Write start address specification Use command 6C0 to set the color table write start address. CTN1 to CTN0: Color table specification (No.1 to No.4), CTA3 to CTA0: Address specification No.1 0000 XX B G R XXXX XXXX XXXX 0001 0010 Address 1110 1111 (2) Data write Continuous write mode differs depending on the write mode specification. (RM3) 1. Normal (RM3 = 0: initial state) *Continuous mode not used* ---COM6C1-1 6C1-2-1 6C1-2-2 command wait state --2. Write continuous (RM3 = 1) mode COM6C1-1 6C1-2-1 6C1-2-2 *: In mode 2, the IC remains locked in continuous write mode until the CS pin is set high. • The write address is automatically incremented. • The write address is retained unless the IC is reset or a new write address is issued. No.A0569-93/106 LC74736PT 1.4 Character RAM write (1) Write start address specification Use COMMAND700 to specify the character RAM write start address. FAD1to FAD0: Character RAM address P-No specification QVGA: 0 to 3, hexadecimal, (4 characters) WVGA: 1 character only 0 to 3 (hexadecimal) P1 to P4 FVA3 to FVA0: Character RAM V dot address specificatrion 0 to F (hexadecimal) FRN1 to FRN0: ROM No. specification 0 to 3 (hexadecimal) No.1 to No.4 D15 to D0 0000 0001 0010 V dot Address 1110 1111 (2) Data write Continuous write mode differs depending on the write mode specification. (RM3) 1. Normal (RM3 = 0: initial state) *Continuous mode not used* ---COM701-1 701-2-1 701-2-2 command wait state --2. Write continuous (RM3 = 1) mode COM701-1 701-2-1 701-2-2 *: In mode 2, the IC remains locked in continuous write mode until the CS pin is set high. • The write address is automatically incremented. • The write address is retained unless the IC is reset or a new write address is issued. No.A0569-94/106 LC74736PT 2. Display format 2.1 Color Specification Related Items (1) When a character is specified Specify color with the character color (character area) and character background color (outside the character area) Character color: 1 of 16 colors Character background color: 1 of 16 colors Color tables: Table No. 1 to No. 4 specified by CT1 to CT0. (COM10-2-3: VRAM) 1 of 64 types Character color Specified by CC0 to CC3: 1of 16 colors (COM10-2-2: VRAM) Character background color Specified by CB0 to CB3: 1 of 16 colors (COM10-2-2: VRAM) (2) When a graphic 1 is specified Specify color is in dot units (16×16) 1 of 16 colors (FROM) Color tables: Table No. 1 to No. 4 specified by CT1 to CT0. (COM10-2-3: VRAM) 1 of 64 types Specified by FROM: 1 of 16 types No.A0569-95/106 LC74736PT (3) When a graphic 2 is specified Specify color is in dot units (16×16) 1 of 16 colors (FROM) Color tables: Table No. 1 to No. 4 specified by CT1 to CT0. (COM10-2-3: VRAM) 1 of 64 types The CTB address display color shown with CB3 to CB0 is changed to the CTB address display color shown with CC3 to CC0. One color in the graphic character display can be changed by setting CB and CC. Specified by FROM: 1 of 16 types (4) When a graphic 3 is specified Specify color is in dot units (16×16) 1 of 16 colors (FROM) Color tables: Table No. 1 to No. 4 specified by CT1 to CT0. (COM10-2-3: VRAM) 1 of 64 types CTB No. in the address shown with CB3 to CB0 is changed to CTB No. shown with CC1 to CC0 and display it. CTB No. of one color in the graphic character display can be changed by setting CB and CC. Specified by FROM: 1 of 16 types No.A0569-96/106 LC74736PT 2.2 Display Control Related Items (1) Blinking: In character units 1. Normal at1 = 0 (COM10-2-1: VRAM) 2. Blinking at1 = 1 Display alternates between normal and transparent with the blinking period. (COM21-2: BK1, BK0) (2) Border display: Only valid for font specified characters 1. Border color: 1 of 16 colors (COM60-2 EGC3 to EGC0) Color table specification (COM60-2 EGCT1 to EGCT0) → 1 of 64 types specified in line units 2. Border mode control (COM60-2 BLK1, BLK0) specified in line units i. Border ii. Shadow 1: lower iii. Shadow 2: lower + right No.A0569-97/106 LC74736PT (3) Character size: Specified in line units The character size is specified as 1x to 4x independently for the vertical and horizontal directions. (COM40-2) 2.3 Box Display (raised/recessed) raised 16 dots recessed 16 dots (1) Raised/recessed specification: In character units (COM10-2-1 BXS) (2) Left side-displayed/undisplayed specification: in character units (COM10-2-1 BXL) (3) Right side-displayed/undisplayed specification: in character units (COM10-2-1 BXR) (4) Upper side-displayed/undisplayed specification: in character units (COM10-2-1 BXU) (5) Lower side-displayed/undisplayed specification: in character units (COM10-2-1 BXD) (6) Color specification: In line units COM50 (Upper side) COM51 (Lower side) BXUC3 to BXDC0: 1 of 16 colors BXDC3 to BXDC0: 1 of 16 colors Color table specification BXUCT1 to BXUCT0 BXDCT1 to BXUCT0 1 of 64 types Box dot width specification Each of left, right, upper, and lower can be specified independently. Left: BXLW1 to BXLW0 1 to 4 dots Right: BXRW1 to BXRW0 1 to 4 dots Upper and lower (COM59-2) Upper BXWU 1 to 2 dots (It depends on the character size.) Lower BXWD 1 to 2 dots (It depends on the character size.) No.A0569-98/106 LC74736PT 2.4 Line spacing control (Command 58-2: GY3, GY2, GY1, GY0) -1 16 dots 16 dots +1 to +15 Line spacing -1 16 dots 16 dots 16 dots Line spacing +1 to +15 -1 16 dots +1 to +15 • Line spacing display control COM58-2: GS1, GS0 Character (1) Transparent (2) Transparent ±1(character background color) (3) Character background color (4) Transparent (Border enabled) Graphic Transparent Transparent ±1(CB specified color) CB setting color Transparent No.A0569-99/106 LC74736PT • Basic line spacing unit GYBCK "0": 1V "1": It depends on the character size. • Box display (COM59-2) Character display range 16 16 Box display Inside the character BXC1 = "0" BXC2 = "0" Outside the character 1 (Valid only when line spacing is set.) BXC1 = "1" BXC2 = "1" BXC3 = "0" Outside the character 2 (Valid only when line spacing is set.) BXC1 = "1" BXC2 = "1" BXC3 = "1" No.A0569-100/106 LC74736PT 2.5 Screen Structure Screen background color Wallpaper display screen Main screen 2 16×16 dot characters 30-character×15-line QVGA panel Main screen 1 16×16 dot characters 30-character×15-line • For each screen: Display on/off (transparent) can be specified independently. • For each screen: The display start position can be specified independently. The wallpaper display screen and the main screen require xxxx clocks before the horizontal start position is reached. No.A0569-101/106 LC74736PT • Display Format 1) QVGA Character specification 16 dots Graphic 16 dots 16H 2) WVGA Character specification 24 dots Graphic 24 dots 32H • ROM structure (1) No internal ROM (2) Internal character RAM QVGA: 4 characters, WVGA: 1 character 1) Character font QVGA: 16×16-dot structure WVGA: 24×32-dot structure 2) Graphics QVGA: 16×16-dot structure WVGA: 24×32-dot structure No.A0569-102/106 LC74736PT (3) External ROM (QVGA: 16384 characters, WVGA: 4096 characters) ×16 types, 16M 1) Conditions • QVGA mode Access time = 2× dot clock frequency or shorter Example: DCLK = 10MHz = 100ns×2 = 200ns or shorter • WVGA mode 1) Access time =3× dot clock frequency or shorter, with display limitations Example: DCLK = 33MHz = 30ns×3 = 90ns or shorter 2) Access time =2× dot clock frequency or shorter, with display limitations Example: DCLK = 33MHz = 30ns×2 = 60ns or shorter 3) Access time =1× dot clock frequency or shorter Example: DCLK = 33MHz = 30ns×1 = 30ns or shorter 2) ROM map • QVGA • Address A19 to A0 • Data D15 to D0 Used A1 to A0 00 01 10 11 Color information 16 dots A5 to A2 16 dots N1 N2 N3 N4 A19 to A6 (14 bits) = 16384 characters = character codes No.A0569-103/106 LC74736PT • WVGA • Address A19 to A0 • Data D15 to D12, D11 to D0 Unused Used A3 to A2 Location information 12 dots 12 dots 16 dots P1 00 P2 01 16 dots P3 10 P4 11 On each of P1 to P4 A1 to A0 00 01 10 11 Color information 12 dots A7 to A4 16 dots N1 N2 N3 N4 A19 to A8 (12 bits) = 4096 characters = character codes No.A0569-104/106 LC74736PT 3) Display appearance • QVGA: 1 character = 16×16 dots Character N1 or N2 or N3 or N4, VRAM selectable Graphic N1+N2+N3+N4 Character Graphic 16 16 N1 or N2 or N3 or N4 N1+N2 +N3+N4 16 16 • WVGA: 1 character = 24×32 dots Character P1+P2+P3+P4 (12×16×4) N1 or N2 or N3 or N4, VRAM selectable Graphic P1+P2+P3+P4 (12×16×4) N1+N2+N3+N4 Character Graphic 24 24 N1 or N2 or N3 or N4 N1+N2 +N3+N4 32 32 12 12 16 P1 P2 16 16 P3 P4 16 12 12 No.A0569-105/106 LC74736PT SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of June, 2007. Specifications and information herein are subject to change without notice. PS No.A0569-106/106