Ordering number : ENA1995 STK672-622A-E Thick-Film Hybrid IC 2-phase Stepping Motor Driver Overview The STK672-622A-E is a hybrid IC for use as a unipolar, 2-phase stepping motor driver with PWM current control. Applications • Office photocopiers, printers, etc. Features • Built-in overcurrent detection function (output current OFF). • Built-in overheat detection function (output current OFF). • If either over-current or overheat detection function is activated, the FAULT1 signal (active low) is output. The FAULT2 signal is used to output the result of activation of protection circuit detection at 2 levels. • Built-in power on reset function. • The motor speed is controlled by the frequency of an external clock signal. • 2 phase or 1-2 phase excitation switching function. • Using either or both edges of the clock signal switching function. • Phase is maintained even when the excitation mode is switched. • Rotational direction switching function. • Supports schmitt input for 2.5V high level input. • Incorporating a current detection resistor (0.222Ω: resistor tolerance ±2%), motor current can be set using two external resistors. • The ENABLE pin can be used to cut output current while maintaining the excitation mode. • With a wide current setting range, power consumption can be reduced during standby. • No motor sound is generated during hold mode due to external excitation current control. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. N0211HKPC 018-10-0052 No. A1995-1/23 STK672-622A-E Specifications Absolute Maximum Ratings at Tc = 25°C Parameter Symbol Conditions Maximum supply voltage 1 VCC max ENABLE=GND Maximum supply voltage 2 VDD max Input voltage VIN max Output current 1 IOP max Output current 2 Ratings unit 50 V No signal -0.3 to +6.0 V Logic input pins -0.3 to +6.0 V 10μA, 1 pulse (resistance load) 10 A IOH max VDD=5V, CLOCK≥200Hz 1.6 A Output current 3 IOF max Pin16 output current 10 mA Allowable power dissipation 1 PdMF max With an arbitrarily large heat sink. Per MOSFET 7.3 W Allowable power dissipation 2 PdPK max No heat sink 2.8 W Operating substrate temperature Tc Metal surface temperature of the package -20 to +105 °C Junction temperature Tj max 150 °C Storage temperature Tstg -40 to +125 °C Allowable Operating Ranges at Ta=25°C Parameter Symbol Conditions Ratings unit Operating supply voltage 1 VCC With signals applied 0 to 46 V Operating supply voltage 2 VDD With signals applied 5±5% V Input high voltage VIH Pins 10, 12, 13, 14, 15, 17, VDD=5±5% 2.5 to VDD V 0 to 0.8 V 1.2 A 1.3 A Input low voltage VIL Pins 10, 12, 13, 14, 15, 17, VDD=5±5% Output current 1 IOH1 Tc=105°C, CLOCK≥200Hz, Continuous operation, duty=100% Output current 2 IOH2 Tc=80°C, CLOCK≥200Hz, Continuous operation, duty=100%, See the motor current (IOH) derating curve CLOCK frequency fCL Recommended Vref range Vref Minimum pulse width: at least 10μs 0 to 50 0.14 to 1.34 kHz V Electrical Characteristics at Tc=25°C, VCC=24V, VDD=5.0V Parameter Symbol Conditions VDD supply current ICCO Pin 9 current Output average current* Ioave R/L=1Ω/0.62mH in each phase FET diode forward voltage Vdf If=1A (RL=23Ω) Output saturation voltage Vsat RL=23Ω Input high voltage VIH Pins 10, 12, 13, 14, 15, 17 Input low voltage VIL Pins 10, 12, 13, 14, 15, 17 FAULT1 low output voltage VOLF Pin 16 (IO=5mA) 5V level FAULT1 leakage IILF Pin 16=5V VOF2 Pin 8 (when all protection functions have min typ 0.12 max unit 5 8 0.16 0.20 A 1.0 1.7 V 0.42 0.57 V 2.5 mA V 0.8 0.25 V 0.5 V 10 μA current FAULT2 Overcurrent detection output voltage FAULT2 Overheat detection 2.4 2.5 2.6 3.1 3.3 3.5 50 75 μA 10 μA been activated) VOF3 V output voltage 5V level input current IILH Pins 10, 12, 13, 14, 15, 17=5V GND level input current IILL Pins 10, 12, 13, 14, 15, 17=GND Vref input bias current IIB Pin 19=1.0V PWM frequency fc Overheat detection temperature TSD Design guarantee Drain-source cut-off current IDSS VDS=100V, Pins 2, 6, 9, 18=GND 29 45 1 μA 61 kHz 1 μA °C 144 * Operation at the maximum VCC value may not be possible, depending on the motor current. See “8. Other Notes on Use” in the Data Sheet for details. *Ioave values are for when the lead frame of the product is soldered to the mounting substrate. Notes: A fixed-voltage power supply must be used. No. A1995-2/23 STK672-622A-E Package Dimensions unit:mm (typ) 24.2 (18.4) 4.5 11.0 (11.0) 14.4 14.4 (R1.47) 19 (3.5) 1 1.0 0.4 0.5 2.0 18 1.0=18.0 4.0 4.45 Derating curve of motor current, IOH, vs. STK672-622A-E Operating substrate temperature, Tc IOH - Tc 1.8 200Hz 2-phase excitation 1.6 Hold mode Motor current, IOH - A 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 10 20 30 40 50 60 70 80 90 100 110 Operating Substrate Temperature, Tc - °C Notes • The current range given above represents conditions when output voltage is not in the avalanche state. If the output voltage is in the avalanche state, see the allowable avalanche energy for STK672-6** series hybrid ICs given in a separate document. • The operating substrate temperature, Tc, given above is measured while the motor is operating. Because Tc varies depending on the ambient temperature, Ta, the value of IOH, and the continuous or intermittent operation of IOH, always verify this value using an actual set. • The Tc temperature should be checked in the center of the metal surface of the product package. No. A1995-3/23 STK672-622A-E Block Diagram FAULT2 N.C 8 VDD=5V 9 7 A AB B BB 4 5 3 1 VDD F1 MODE1 10 N.C 11 Excitation mode selection MODE2 17 Phase excitation signal generator Phase advance counter CLOCK 12 F2 F3 F4 FAO FAB FBO FBB CWB 13 R1 Power-on reset RESETB 14 Latch Circuit ENABLE 15 R2 Overcurrent detection 2 P.G2 6 P.G1 AI FAULT1 16 Current control chopper circuit FAULT1 FAULT2 signal Overheating detection BI Vref/4.9 Latch Circuit Vref Amplifier VSS VSS N.C 18 Vref 19 Sample Application Circuit STK672-622A-E VDD(5V) 9 CLOCK 12 MODE1 10 MODE2 17 CWB 13 ENABLE 15 RESETB R01 2 phase stepping motor driver 4 5 3 14 1 A B BB + R03 16 FAULT1 2 8 FAULT2 Vref R02 0.1μF C02 VCC 24V AB 6 19 C01 at least 100μF P.G2 P.G1 P.GND 18 N.C No. A1995-4/23 STK672-622A-E Precautions [GND wiring] • To reduce noise on the 5V system, be sure to place the GND of C01 in the circuit given above as close as possible to Pin 2 and Pin 6 of the hybrid IC. Also, to achieve accurate current settings, be sure to connect Vref GND to Pin 18 (S.G) used to set the current and to the point where P.G1 and P.G2 share a connection. [Input pins] • If VDD is being applied, use care that each input pin does not apply a negative voltage less than -0.3V to S.G, Pin 18, and do not apply a voltage greater than or equal to VDD voltage. • Do not wire by connecting the circuit pattern on the P.C.B side to Pin 7 and Pin 11 on the N.C. shown in the internal block diagram. • Apply 2.5V high level input to pins 10, 12, 13, 14, 15, and 17. • Since the input pins do not have built-in pull-up resistors, when the open-collector type pins 10, 12, 13, 14, 15, and 17 are used as inputs, a 1 to 20kΩ pull-up resistor (to VDD) must be used. At this time, use a device for the open collector driver that has output current specifications that pull the voltage down to less than 0.8V at Low level (less than 0.8V at Low level when IOL=5mA). [Current setting Vref] If the motor current is temporarily reduced, the circuit given below (STK672-622A-E : IOH>0.12A) is recommended. 5V 5V R01 R01 Vref Vref R02 R3 R3 R02 • Motor current peak value IOH setting IOH 0 IOH=(Vref÷4.9) ÷Rs The value of 4.9 in Equation above represents the Vref voltage as divided by a circuit inside the control IC. Vref=(R02÷ (R01+R02)) ×5V(or 3.3V) Rs is an internal current detection resistor value of the hybrid IC. Rs=0.222Ω when using the STK672-622A-E No. A1995-5/23 STK672-622A-E [Smoke Emission Precuations] If Pin 18 (S.G terminal) is attached to the PCB without using solder, overcurrent may flow into the MOSFET at VCCON (24V ON), causing the STK672-622A-E to emit smoke because 5V circuits cannot be controlled. Input Pin Functions Pin Name Pin No. Function CLOCK 12 Reference clock for motor phase current switching MODE1 10 Excitation mode selection Input Conditions When Operating Operates on the rising edge of the signal (MODE2=H) Low: 2-phase excitation High: 1-2 phase excitation MODE2 17 High: Rising edge CWB 13 Motor direction switching RESETB 14 System reset Low: Rising and falling edge Low: CW (forward) High: CCW (reverse) A reset is applied by a low level Initial state of A and BB phase excitation in the timing charts is set by switching from low to high. ENABLE 15 The A, AB, B, and BB outputs are turned off, and after The A, AB, B, and BB outputs are turned off by a low- operation is restored by returning the ENABLE pin to the level input. high level, operation continues with the same excitation timing as before the low-level input. Output Pin Functions Pin No. Function FAULT1 Pin Name 16 Monitor pin used when over-current detection or overheat FAULT2 8 Input Conditions When Operating Low level is output when detected. detection function is activated. The output voltage of this pin differs according to the 2 levels output detected abnormality. Note: See the timing chart for the concrete details on circuit operation. No. A1995-6/23 STK672-622A-E Timing Charts 2-phase excitation VDD Power On Reset (or RESETB) MODE1 MODE2 CWB CLOCK ENABLE FAO FAB FBO FBB 1-2 phase excitation VDD Power On Reset (or RESETB) MODE1 MODE2 CWB CLOCK ENABLE FAO FAB FBO FBB No. A1995-7/23 STK672-622A-E 1-2 phase excitation (CWB) VDD Power On Reset (or RESETB) MODE1 MODE2 CWB CLOCK ENABLE FAO FAB FBO FBB 2 phase excitation → Switch to 1-2 phase excitation VDD Power On Reset (or RESETB) MODE1 MODE2 CWB CLOCK ENABLE FAO FAB FBO FBB No. A1995-8/23 STK672-622A-E 1-2 phase excitation (ENABLE) VDD Power On Reset (or RESETB) MODE1 MODE2 CWB CLOCK ENABLE FAO FAB FBO FBB 1-2 phase excitation (Hold operation results during fixed CLOCK) VDD Power On Reset (or RESETB) MODE1 MODE2 CWB CLOCK ENABLE Hold operation FAO FAB FBO FBB No. A1995-9/23 STK672-622A-E 2 phase excitation (MODE 2) VDD Power On Reset (or RESETB) MODE1 MODE2 CWB CLOCK ENABLE FAO FAB FBO FBB 1-2 phase excitation (MODE 2) VDD Power On Reset (or RESETB) MODE1 MODE2 CWB CLOCK ENABLE FAO FAB FBO FBB No. A1995-10/23 STK672-622A-E Usage Notes 1. Input signal functions and timing [ENABLE, CLOCK and power on reset, RESETB (Input signal timing when power is first applied)] The control IC of the driver is equipped with a power on reset function capable of initializing internal IC operations when power is supplied. A 4V typ setting is used for power on reset. Because the specification for the MOSFET gate voltage is 5V±5%, conduction of current to output at the time of power on reset adds electromotive stress to the MOSFET due to lack of gate voltage. To prevent electromotive stress, be sure to set ENABLE=Low while VDD, which is outside the operating supply voltage, is less than 4.75V. In addition, if the RESETB terminal is used to initialize output timing, be sure to allow at least 10μs until CLOCK input. 3.8V typ 4V typ Control IC power (VDD) rising edge Control IC power on reset RESETB signal input No time specification ENABLE signal input CLOCK signal input At least 10μs At least 10μs ENABLE, CLOCK, and RESETB Signals Input Timing [CLOCK (Phase switching clock)] • Input frequency: DC to 50kHz • Minimum pulse width: 10μs • MODE2=1(High) Signals are read on the rising edge. • MODE2=0(Low) Signals are read on the rising and falling edges. [CWB (Motor direction setting)] The direction of rotation is switched by setting CWB to 1 (high) or 0 (low). See the timing charts for details on the operation of the outputs. Note: The state of the CWB input must not be changed during the 6.25μs period before and after the rising edge of the CLOCK input. [ENABLE (Forcible on/off control of the A, AB, B, and BB outputs, and hybrid IC internal operation)] ENABLE=1: Normal operation ENABLE=0: Outputs A, AB, B, and BB forced to the off state. If, during the state where CLOCK signal input is provided, the ENABLE pin is set to 0 and then is later restored to the 1 state, the IC will resume operation with the excitation timing continued from before the point ENABLE was set to 0. If sudden stop is applied to the CLOCK signal used for motor rotation, the motor axis may advance beyond the theoretical position due to inertia. To stop at the theoretical position, the SLOW DOWN setting for gradually slowing the CLOCK cycle is required. No. A1995-11/23 STK672-622A-E [MODE1 and MODE2 (Excitation mode selection)] MODE1=0: 2-phase excitation MODE2=1: Rising edge of CLOCK MODE1=1: 1-2 phase excitation MODE2=0: Rising and falling edges of CLOCK See the timing charts for details on output operation in these modes. Note: The state of the MODE input must not be changed during the 5μs period before and after the rising edge of the CLOCK input. The CLOCK input must not be changed during the period from when the signal changes from high to low or low to high in MODE1 or MODE2, till when the signal changes from high to low or low to high in CWB. [Configuration of Each Input Pin] <Configuration of the MODE1, MODE2, CLOCK, CWB, ENABLE, and RESETB input pins> 5V <Configuration of the FAULT2 pin> Output pin Pin 8 10kΩ Input pin 5V 50kΩ 50kΩ 50kΩ 100kΩ VSS Overcurrent Overheating (The buffer has an open drain configuration.) All input pins of this driver support schmitt input. Typ specifications at Tc = 25°C are given below. Hysteresis voltage is 0.3V (VIHa-VILa). When rising When falling 1.8V typ 1.5V typ Input voltage VILa VIHa Input voltage specifications are as follows. VIH=2.5V min VIL=0.8V max <Configuration of the Vref input pin> <Configuration of the FAULT1 output pin> 5V Output pin Pin 16 Vref/4.9 − Amplifier VSS Overcurrent + Overheating Input pin Pin 19 VSS No. A1995-12/23 STK672-622A-E <FAULT1, FAULT2 output> FAULT1 Output FAULT1 is an open drain output. Low is output if either overcurrent or overheating is detected. FAULT2 output Output is resistance divided (2 levels) and the type of abnormality detected is converted to the corresponding output voltage. • Overcurrent: 2.5V (typ) • Overheat: 3.3V (typ) Abnormality detection can be released by a RESETB operation or turning VDD voltage on/off. 2. Overcurrent Detection and Overheat Detection Functions of the STK672-622A-E Each detection function operates using a latch system and turns output off. Because a RESET signal is required to restore output operations, once the power supply, VDD, is turned off, you must either again apply power on reset with VDDON or apply a RESETB=High→Low→High signal. [Overcurrent detection] This hybrid IC is equipped with a function for detecting overcurrent that arises when the motor burns out or when there is a short between the motor terminals. Overcurrent detection occurs at 2.2A typ with the STK672-622A-E. Current when motor terminals are shorted PWM period Set motor current, IOH Over-current detection IOH max MOSFET all OFF No detection interval (5.5μs typ) Normal operation 5.5μs typ Operation when motor pins are shorted Overcurrent detection begins after an interval of no detection (a dead time of 5.5μs typ) during the initial ringing part during PWM operations. The no detection interval is a period of time where overcurrent is not detected even if the current exceeds IOH. [Overheat detection] Rather than directly detecting the temperature of the semiconductor device, overheat detection detects the temperature of the aluminum substrate (144°C typ). Within the allowed operating range recommended in the specification manual, if a heat sink attached for the purpose of reducing the operating substrate temperature, Tc, comes loose, the semiconductor can operate without breaking. However, we cannot guarantee operations without breaking in the case of operations other than those recommended, such as operations at a current exceeding IOH max that occurs before overcurrent detection is activated. No. A1995-13/23 STK672-622A-E 3. Calculating STK672-622A-E HIC Internal Power Loss The average internal power loss in each excitation mode of the STK672-622A-E can be calculated from the following formulas. Each excitation mode 2-phase excitation mode 2PdAVex=2×Vsat×0.5×CLOCK×IOH×t2+0.5×CLOCK×IOH× (Vsat×t1+Vdf×t3) 1-2 Phase excitation mode 1-2PdAVex=2×Vsat×0.25×CLOCK×IOH×t2+0.25×CLOCK×IOH× (Vsat×t1+Vdf×t3) Motor hold mode HoldPdAVex= 2×Vsat×IOH Vsat: Combined voltage represented by the Ron voltage drop+shunt resistor Vdf: Combined voltage represented by the MOSFET body diode+shunt resistor CLOCK: Input CLOCK (CLOCK pin signal frequency) t1, t2, and t3 represent the waveforms shown in the figure below. t1: Time required for the winding current to reach the set current (IOH) t2: Time in the constant current control (PWM) region t3: Time from end of phase input signal until inverse current regeneration is complete IOH 0A t1 t2 t3 Motor COM Current Waveform Model t1= (-L/(R+0.42)) ln (1-((R+0.42)/VCC) ×IOH) t3= (-L/R) ln ((VCC+0.42)/(IOH×R+VCC+0.42)) VCC: Motor supply voltage (V) L: Motor inductance (H) R: Motor winding resistance (Ω) IOH: Motor set output current crest value (A) Relationship of CLOCK, t1, t2, and t3 in each excitation mode 2-phase excitation mode: t2= (2/CLOCK) - (t1+t3) 1-2 phase excitation mode: t2= (3/CLOCK) -t1 For Vsat and Vdf, be sure to substitute values from the graphs of Vsat vs. IOH and Vdf vs. IOH while the set current value is IOH. Then, determine whether a heat sink is required by comparing with the graph of ΔTc vs. Pd based on the average HIC power loss calculated. When designing a heat sink, refer to the section “Thermal design” found on the next page. The average HIC power loss, PdAV, described above does not have the avalanche’s loss. To include the avalanche’s loss, be sure to add Equation (2), “STK672-6** Allowable Avalanche Energy Value” to PdAV above. When using this IC without a fin always check for temperature increases in the set, because the HIC substrate temperature, Tc, varies due to effects of convection around the HIC. No. A1995-14/23 STK672-622A-E STK672-622A-E Output saturation voltage, Vsat - Output current, IOH Vsat - IOH 0.7 0.6 Tc =1 05 °C Output saturation voltage, Vsat - V 0.8 0.5 °C 25 0.4 0.3 0.2 0.1 0 0.5 0 1.0 1.5 2.0 Output current, IOH - A STK672-622A-E Forward voltage, Vdf -Output current, IOH Vdf- IOH 1.4 Forward voltage, Vdf - V 1.2 25 Tc= 1.0 °C 105 0.8 °C 0.6 0.4 0.2 0 0 0.5 1.0 1.5 2.0 Output current, IOH - A Substrate temperature rise, ΔTc (no heat sink) - Internal average power dissipation, PdAV ΔTc - PdAV Substrate temperature rise, ΔTc - °C 80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 Hybrid IC internal average power dissipation, PdAV - W 3.0 ITF02717 No. A1995-15/23 STK672-622A-E 4. STK672-622A-E Allowable Avalanche Energy Value (1) Allowable Range in Avalanche Mode When driving a 2-phase stepping motor with constant current chopping using an STK672-6** Series hybrid IC, the waveforms shown in Figure 1 below result for the output current, ID, and voltage, VDS. VDSS: Voltage during avalanche operations VDS IOH: Motor current peak value IAVL: Current during avalanche operations ID tAVL: Time of avalanche operations ITF02557 Figure 1 Output Current, ID, and Voltage, VDS, Waveforms 1 of the STK672-6** Series when Driving a 2-Phase Stepping Motor with Constant Current Chopping When operations of the MOSFET built into STK672-6** Series ICs is turned off for constant current chopping, the ID signal falls like the waveform shown in the figure above. At this time, the output voltage, VDS, suddenly rises due to electromagnetic induction generated by the motor coil. In the case of voltage that rises suddenly, voltage is restricted by the MOSFET VDSS. Voltage restriction by VDSS results in a MOSFET avalanche. During avalanche operations, ID flows and the instantaneous energy at this time, EAVL1, is represented by Equation (1). EAVL1=VDSS×IAVL×0.5×tAVL ------------------------------------------- (1) VDSS: V units, IAVL: A units, tAVL: sec units The coefficient 0.5 in Equation (1) is a constant required to convert the IAVL triangle wave to a square wave. During STK672-6** Series operations, the waveforms in the figure above repeat due to the constant current chopping operation. The allowable avalanche energy, EAVL, is therefore represented by Equation (2) used to find the average power loss, PAVL, during avalanche mode multiplied by the chopping frequency in Equation (1). PAVL=VDSS×IAVL×0.5×tAVL×fc ------------------------------------------- (2) fc: Hz units (fc is set to the PWM frequency of 50kHz.) For VDSS, IAVL, and tAVL, be sure to actually operate the STK672-6** Series and substitute values when operations are observed using an oscilloscope. Ex. If VDSS=110V, IAVL=1A, tAVL=0.2μs when using a STK672-622A-E driver, the result is: PAVL=110×1×0.5×0.2×10-6×50×103=0.55W VDSS=110V is a value actually measured using an oscilloscope. The allowable loss range for the allowable avalanche energy value, PAVL, is shown in the graph in Figure 3. When examining the avalanche energy, be sure to actually drive a motor and observe the ID, VDSS, and tAVL waveforms during operation, and then check that the result of calculating Equation (2) falls within the allowable range for avalanche operations. No. A1995-16/23 STK672-622A-E (2) ID and VDSS Operating Waveforms in Non-avalanche Mode Although the waveforms during avalanche mode are given in Figure 1, sometimes an avalanche does not result during actual operations. Factors causing avalanche are listed below. • Poor coupling of the motor’s phase coils (electromagnetic coupling of A phase and AB phase, B phase and BB phase). • Increase in the lead inductance of the harness caused by the circuit pattern of the P.C. board and motor. • Increases in VDSS, tAVL, and IAVL in Figure 1 due to an increase in the supply voltage from 24V to 36V. If the factors above are negligible, the waveforms shown in Figure 1 become waveforms without avalanche as shown in Figure 2. Under operations shown in Figure 2, avalanche does not occur and there is no need to consider the allowable loss range of PAVL shown in Figure 3. VDS IOH: Motor current peak value ID ITF02558 Figure 2 Output Current, ID, and Voltage, VDS, Waveforms 2 of the STK672-6** Series when Driving a 2-Phase Stepping Motor with Constant Current Chopping Average power loss in the avalanche state, PAVL - W Figure 3 Allowable Loss Range, PAVL-IOH During Avalanche Operations PAVL - IOH 4.0 Tc=80°C 3.5 3.0 105°C 2.5 2.0 1.5 1.0 0.5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 Motor phase current, IOH - A Note: The operating conditions given above represent a loss when driving a 2-phase stepping motor with constant current chopping. Because it is possible to apply 2.6W or more at IOH=0A, be sure to avoid using the MOSFET body diode that is used to drive the motor as a zener diode. No. A1995-17/23 STK672-622A-E 5. Thermal design [Operating range in which a heat sink is not used] Use of a heat sink to lower the operating substrate temperature of the HIC (Hybrid IC) is effective in increasing the quality of the HIC. The size of heat sink for the HIC varies depending on the magnitude of the average power loss, PdAV, within the HIC. The value of PdAV increases as the output current increases. To calculate PdAV, refer to “Calculating Internal HIC Loss for the STK672-622A-E”. Calculate the internal HIC loss, PdAV, assuming repeat operation such as shown in Figure 1 below, since conduction during motor rotation and off time both exist during actual motor operations, IO1 Motor phase current (sink side) IO2 0A -IO1 T1 T2 T3 T0 Figure 1 Motor Current Timing T1: Motor rotation operation time T2: Motor hold operation time T3: Motor current off time T2 may be reduced, depending on the application. T0: Single repeated motor operating cycle IO1 and IO2: Motor current peak values Due to the structure of motor windings, the phase current is a positive and negative current with a pulse form. Note that figure 1 presents the concepts here, and that the on/off duty of the actual signals will differ. The hybrid IC internal average power dissipation PdAV can be calculated from the following formula. PdAV= (T1×P1+T2×P2+T3×0) ÷TO ---------------------------- (I) (Here, P1 is the PdAV for IO1 and P2 is the PdAV for IO2) If the value calculated using Equation (I) is 1.5W or less, and the ambient temperature, Ta, is 60°C or less, there is no need to attach a heat sink. Refer to Figure 2 for operating substrate temperature data when no heat sink is used. [Operating range in which a heat sink is used] Although a heat sink is attached to lower Tc if PdAV increases, the resulting size can be found using the value of θc-a in Equation (II) below and the graph depicted in Figure 3. θc-a= (Tc max-Ta) ÷PdAV ---------------------------- (II) Tc max: Maximum operating substrate temperature =105°C Ta: HIC ambient temperature Although a heat sink can be designed based on equations (I) and (II) above, be sure to mount the HIC in a set and confirm that the substrate temperature, Tc, is 105°C or less. The average HIC power loss, PdAV, described above represents the power loss when there is no avalanche operation. To add the loss during avalanche operations, be sure to add Equation (2), “Allowable STK672-6** Avalanche Energy Value”, to PdAV. No. A1995-18/23 STK672-622A-E Figure 2 Substrate temperature rise, ΔTc (no heat sink) - Internal average power dissipation, PdAV ΔTc - PdAV Substrate temperature rise, ΔTc - °C 80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 Hybrid IC internal average power dissipation, PdAV - W ITF02717 Figure 3 Heat sink area (Board thickness: 2mm) - θc-a θc-a - S Heat sink thermal resistance, θc-a - °C/W 100 7 5 3 2 Wit 10 Wi t 7 5 ha 3 2 1.0 10 2 3 5 hn o su rfac e fi nish flat blac k su rfac e fi nish 7 100 2 3 5 Heat sink area, S - cm2 7 1000 ITF02554 6. Mitigated Curve of Package Power Loss, PdPK, vs. Ambient Temperature, Ta Package power loss, PdPK, refers to the average internal power loss, PdAV, allowable without a heat sink. The figure below represents the allowable power loss, PdPK, vs. fluctuations in the ambient temperature, Ta. Power loss of up to 2.8W is allowable at Ta=25°C, and of up to 1.5W at Ta=60°C. * The package thermal resistance θc-a is 28.6°C/W. Allowable power dissipation, PdPK(no heat sink) - Ambient temperature, Ta PdPK - Ta Allowable power dissipation, PdPK - W 3.0 2.5 2.0 1.0 1.5 0.5 0 0 20 40 60 80 Ambient Temperature, Ta - °C 100 120 ITF02718 No. A1995-19/23 STK672-622A-E 7. Example of Stepping Motor Driver Output Current Path (1-2 phase excitation) 2-phase stepping motor IOAB IOA FAULT2 N.C 8 VDD=5V 9 VDD MODE1 10 Excitatin mode setting N.C 11 MODE2 17 Latch circuit ENABLE 15 FAULT1, FAULT2 signal FAULT1 16 Over heat detection N.C 18 F1 B BB 1 3 F2 F3 F4 VCC 24V R1 Power on reset RESETB 14 5 Phase excitation signal generation Phase advnce counter CLOCK 12 CWB 13 AB A 4 7 Latch circuit Over current detection Current control chopper circuit AI BI Vref/4.9 R2 P.G2 2 P.G1 6 C02 at least 100μF P.GND Vref Amplifier VSS VSS Vref 19 CLOCK Phase A output current IOA PWM operations Phase AB output current When PWM operations of IOA are OFF, for IOAB, negative current flows through the parasitic diode, F2. IOAB When PWM operations of IOAB are OFF, for IOA, negative current flows through the parasitic diode, F1. No. A1995-20/23 STK672-622A-E 8. Other Notes on Use In addition to the “Notes” indicated in the Sample Application Circuit, care should also be given to the following contents during use. (1) Allowable operating range Operation of this product assumes use within the allowable operating range. If a supply voltage or an input voltage outside the allowable operating range is applied, an overvoltage may damage the internal control IC or the MOSFET. If a voltage application mode that exceeds the allowable operating range is anticipated, connect a fuse or take other measures to cut off power supply to the product. (2) Input pins If the input pins are connected directly to the PC board connectors, electrostatic discharge or other overvoltage outside the specified range may be applied from the connectors and may damage the product. Current generated by this overvoltage can be suppressed to effectively prevent damage by inserting 100Ω to 1kΩ resistors in lines connected to the input pins. Take measures such as inserting resistors in lines connected to the input pins. (3) Power connectors If the motor power supply VCC is applied by mistake without connecting the GND part of the power connector when the product is operated, such as for test purposes, an overcurrent flows through the VCC decoupling capacitor, C1, to the parasitic diode between the VDD of the internal control IC and GND, and may damage the power supply pin block of the internal control IC. To prevent destruction in this case, connect a 10Ω resistor to the VDD pin, or insert a diode between the VCC decoupling capacitor C1 GND and the VDD pin. Overcurrent protection measure: Insert a resistor. VDD=5V 5V Reg. 9 A 4 VDD AB 5 F1 F2 B 3 BB 1 F3 F4 FAO MODE1 FABO FBO CLOCK FBBO VCC CWB RESETB R1 ENABLE AI MODE2 BI R2 GND 2 C1 24V Reg. 6 Vref FAULT1 Vref 18 VSS N.C open Overcurrent protection measure: Insert a diode. Over-current path (4) Input Signal Lines 1) Do not use an IC socket to mount the driver, and instead solder the driver directly to the PC board to minimize fluctuations in the GND potential due to the influence of the resistance component and inductance component of the GND pattern wiring. 2) To reduce noise caused by electromagnetic induction to small signal lines, do not design small signal lines (sensor signal lines, and 5V or 3.3V power supply signal lines) that run parallel in close proximity to the motor output line A (Pin 4), AB (Pin 5), B (Pin 3), or BB (Pin 1) phases. 3) Pin 7 and Pin 11 of this product are N.C pins. Do not connect any wiring to these pins. No. A1995-21/23 STK672-622A-E (5) When mounting multiple drivers on a single PC board When mounting multiple drivers on a single PC board, the GND design should mount a VCC decoupling capacitor, C1, for each driver to stabilize the GND potential of the other drivers. The key wiring points are as follows. 24V 5V 9 9 Motor 1 Input 9 Motor 2 Input Motor 3 Input IC2 IC1 IC3 2 2 6 6 2 6 19 18 19 18 19 18 GND GND Short Thick Thick and short (6) VCC operating limit When the output (for example F1) of a 2-phase stepping motor driver is turned OFF, the AB phase back electromotive force eab produced by current flowing to the paired F2 parasitic diode is induced in the F1 side, causing the output voltage VFB to become twice or more the VCC voltage. This is expressed by the following formula. VFB = VCC + eab = VCC + VCC + IOH x RM + Vdf (1.5 V) VCC: Motor supply voltage, IOH: Motor current set by Vref Vdf: Voltage drop due to F2 parasitic diode and current detection resistor R1, RM: Motor winding resistance value Using the above formula, make sure that VFB is always less than the MOSFET withstand voltage of 100V. This is because there is a possibility that operating limit of VCC falls below the allowable operating range of 46V, due to the RM and IOH specifications. VCC VCC AB phase A phase AB phase A phase eab eab is generated by the mutual induction M. Current path VFB M eab F2 OFF F1 ON R1 GND Current path M VCC F2 OFF F1 OFF R1 GND The oscillating voltage in excess of VFB is caused by LCRM (inductance, capacitor, resistor, mutual inductance) oscillation that includes micro capacitors C, not present in the circuit. Since M is affected by the motor characteristics, there is some difference in oscillating voltage according to the motor specifications. In addition, constant voltage drive without constant current drive enables motor rotation at VCC > 0V. No. A1995-22/23 STK672-622A-E SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of November, 2011. Specifications and information herein are subject to change without notice. PS No. A1995-23/23