Ordering number : EN5350A
Wideband Output Module (Video Pack)
VP553
CRT Display Video Output Amplifier
Features
Package Dimensions
• Active load circuits
• Wide bandwidth and high output voltage. Optimal for
use in fH (horizontal deflection frequency) = 90 kHz
class ultrahigh precision monitors.
• Single 15-pin SIP molded package houses three
channels.
unit: mm
2127A
[VP553]
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
VCC max
Allowable power dissipation
Pd max
With an ideal heat sink at Ta = 25°C
Unit
90
V
25
W
Maximum junction temperature
Tj max
150
°C
Maximum case temperature
Tc max
100
°C
–20 to +110
°C
Storage temperature
Tstg
Operating Conditions at Ta = 25°C
Parameter
Recommended supply voltage
Symbol
Conditions
Ratings
VCC
Unit
80
V
Electrical Characteristics at Ta = 25°C (For a single channel, with Rin = 680 Ω, Rip = 22 Ω, Cip = 56 pF)
Parameter
Clock frequency bandwidth (–3 dB)
Frequency bandwidth (–3 dB)
Pulse response
Voltage gain
Symbol
f (clock)
Conditions
Ratings
min
VCC = 80 V, CL = 10 pF
typ
max
Unit
160
MHz
fc
VIN (DC) = 2.0 V, VOUT (p-p) = 40 V
80
MHz
tr
VCC = 80 V, CL = 10 pF
4.8
ns
tf
VIN (DC) = 2.0 V, VOUT (p-p) = 40 V
4.5
VG (DC)
13
15
ns
17
Double
ICC(1)
VCC = 80 V, VIN (DC) = 2.0 V, f = 10 MHz
clock, CL = 10 pF, VOUT (p-p) = 40 V
32
mA
ICC(2)
VCC = 80 V, VIN (DC) = 2.0 V, f = 100 MHz
clock, CL = 10 pF, VOUT (p-p) = 40 V
75
mA
Current drain
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13097HA (OT) No. 5350-1/5
VP553
Internal Equivalent Circuit
Test Circuit (for a single channel)
No. 5350-2/5
VP553
Thermal Design
Thermal design requires that the two conditions Tj (max) ≤ 150°C and Tc ≤ 100°C be met.
(a) Concerning Tj (max), the chip temperature Tj for each transistor is given by equation (1).
Tj = (Tri) = θj–c (Tri) × PC (Tri) + ∆Tc + Ta (°C) ................................................(1)
θj–c (Tri): The thermal resistance of each transistor chip itself
PC (Tri): The collector loss for each transistor
∆Tc: Increase in the case temperature
Ta: Ambient temperature
θj–c (Tri) for each chip will be:
θj–c (Tr1) to (Tr4) = 35°C/W ................................................................................(2)
The loss in transistors in a video pack varies with frequency. The loss increases with the frequency.
For example, if the maximum frequency will be 100 MHz (clock), then the transistors with the largest losses will be
transistors 3 and 4 in the emitter-follower (EF) stage. From the Pd – f (clock) figure, we see that that loss will be 25%
of the total for a single channel. That is:
PC (EF stage) f = 100 MHz = Pd (1ch) f = 100 MHz × 0.25 [W]..................................(3)
The thermal design must assure that Tj does not exceed 150°C at this time.
(b) Concerning Tc (max), the relationship between θh and ∆Tc is:
∆Tc = Pd (total) × θh .............................................................................................(4)
Taking the increase due to Ta into account, the condition the thermal design must meet becomes Tc = ∆Tc + Ta <
100°C.
Next we design thermal conditions for the VP553 that meet the conditions in sections (a) and (b) above.
No. 5350-3/5
VP553
Sample Thermal Design for the VP553
Conditions: For an fH = 90 kHz class monitor, fV = 100 MHz (clock).
VCC = 80 V, VOUT = 40 Vp-p (CL = 10 pF)
Here we consider the case where such a monitor is to be operated at ambient temperatures up to Ta = 60°C and at a
maximum frequency of f = 100 MHz (clock).
As mentioned previously, the chips with the maximum loss will be transistors 3 and 4 in the emitter-follower stage.
Equation (5) follows from deriving that value from the figure below and equation (3).
PC (Tr3, 4)f = 100 MHz = 6.2 × 0.25 ≈ 1.55 [W] ......................................................(5)
However, the actual usage conditions include a blanking period. If we calculate the power during this period
approximately at a 1-MHz power ratio, from Pd – f (clock) and PC (Tri)Ratio – f (clock) figures, we see that PC (BLK)
for transistors 3 and 4 will be:
PC BLK (Tr3, 4) = 2.2 × 0.08 = 0.18 [W]..............................................................(6)
If the blanking period is 20% of the total, from the data of equation (5) and formula (6) we see that the loss in transistors
3 and 4 will be:
PC (Tr3, 4) = PC (Tr3, 4) f = 100 MHz × 0.8 + PCBLK (Tr3, 4) × 0.2 ≈ 1.28 [W] ...(7)
Next, applying the value of θj–c to equation (7), shows ∆Tj to be:
∆Tj = 1.28 × 35 ≈ 45 [°C]
Since ∆Tj ≤ 50°C, it suffices to only consider the Tc ≤ 100°C condition in the thermal design. That is, in the thermal
design we design θh so that Tc will be under 100°C when Pd (total) = Pd (1ch) × 3 for the time when all three channels
are operating at their maximum levels.
∆Tc will be: ∆Tc = 100 – 60 = 40°C
θh = ∆Tc ÷ Pd (total) = 40 ÷ {(6.2 × 0.8 + 2.2 × 0.2) × 3} = 2.5
Thus:
θh = 2.5°C/W
In actual use, due to the actual ambient temperature, the operating conditions, and other factors, it will be possible to use
a heat sink smaller than the one required by the above design. Users should design an optimal heat sink using the data
presented above and their actual conditions.
VCC (V)
VOUT (V)
VO (center)
80
40
40
No. 5350-4/5
VP553
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of January, 1997. Specifications and information herein are subject to
change without notice.
No. 5350-5/5